1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3
4 / {
5 compatible = "brcm,bcm2712";
6
7 #address-cells = <2>;
8 #size-cells = <2>;
9
10 interrupt-parent = <&gicv2>;
11
12 clocks {
13 /* The oscillator is the root of the clock tree. */
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
19 };
20
21 clk_vpu: clk-vpu {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <750000000>;
25 clock-output-names = "vpu-clock";
26 };
27
28 clk_uart: clk-uart {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <9216000>;
32 clock-output-names = "uart-clock";
33 };
34
35 clk_emmc2: clk-emmc2 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
39 clock-output-names = "emmc2-clock";
40 };
41 };
42
43 cpus: cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 /* Source for L1 d/i cache-line-size, cache-sets, cache-size
48 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
49 * Source for L2 cache-line-size and cache-sets:
50 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
51 * and for cache-size:
52 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
53 */
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a76";
57 reg = <0x000>;
58 enable-method = "psci";
59 d-cache-size = <0x10000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
62 i-cache-size = <0x10000>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
65 next-level-cache = <&l2_cache_l0>;
66
67 l2_cache_l0: l2-cache-l0 {
68 compatible = "cache";
69 cache-size = <0x80000>;
70 cache-line-size = <128>;
71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
72 cache-level = <2>;
73 cache-unified;
74 next-level-cache = <&l3_cache>;
75 };
76 };
77
78 cpu1: cpu@1 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a76";
81 reg = <0x100>;
82 enable-method = "psci";
83 d-cache-size = <0x10000>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
86 i-cache-size = <0x10000>;
87 i-cache-line-size = <64>;
88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
89 next-level-cache = <&l2_cache_l1>;
90
91 l2_cache_l1: l2-cache-l1 {
92 compatible = "cache";
93 cache-size = <0x80000>;
94 cache-line-size = <128>;
95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&l3_cache>;
99 };
100 };
101
102 cpu2: cpu@2 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a76";
105 reg = <0x200>;
106 enable-method = "psci";
107 d-cache-size = <0x10000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
110 i-cache-size = <0x10000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
113 next-level-cache = <&l2_cache_l2>;
114
115 l2_cache_l2: l2-cache-l2 {
116 compatible = "cache";
117 cache-size = <0x80000>;
118 cache-line-size = <128>;
119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
120 cache-level = <2>;
121 cache-unified;
122 next-level-cache = <&l3_cache>;
123 };
124 };
125
126 cpu3: cpu@3 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a76";
129 reg = <0x300>;
130 enable-method = "psci";
131 d-cache-size = <0x10000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
134 i-cache-size = <0x10000>;
135 i-cache-line-size = <64>;
136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
137 next-level-cache = <&l2_cache_l3>;
138
139 l2_cache_l3: l2-cache-l3 {
140 compatible = "cache";
141 cache-size = <0x80000>;
142 cache-line-size = <128>;
143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&l3_cache>;
147 };
148 };
149
150 /* Source for cache-line-size and cache-sets:
151 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
152 * Source for cache-size:
153 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
154 */
155 l3_cache: l3-cache {
156 compatible = "cache";
157 cache-size = <0x200000>;
158 cache-line-size = <64>;
159 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
160 cache-level = <3>;
161 cache-unified;
162 };
163 };
164
165 psci {
166 method = "smc";
167 compatible = "arm,psci-1.0", "arm,psci-0.2";
168 };
169
170 rmem: reserved-memory {
171 ranges;
172 #address-cells = <2>;
173 #size-cells = <2>;
174
175 atf@0 {
176 reg = <0x0 0x0 0x0 0x80000>;
177 no-map;
178 };
179
180 cma: linux,cma {
181 compatible = "shared-dma-pool";
182 size = <0x0 0x4000000>; /* 64MB */
183 reusable;
184 linux,cma-default;
185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
186 };
187 };
188
189 soc: soc@107c000000 {
190 compatible = "simple-bus";
191 ranges = <0x00000000 0x10 0x00000000 0x80000000>;
192 #address-cells = <1>;
193 #size-cells = <1>;
194
195 sdio1: mmc@fff000 {
196 compatible = "brcm,bcm2712-sdhci",
197 "brcm,sdhci-brcmstb";
198 reg = <0x00fff000 0x260>,
199 <0x00fff400 0x200>;
200 reg-names = "host", "cfg";
201 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clk_emmc2>;
203 clock-names = "sw_sdio";
204 mmc-ddr-3_3v;
205 };
206
207 system_timer: timer@7c003000 {
208 compatible = "brcm,bcm2835-system-timer";
209 reg = <0x7c003000 0x1000>;
210 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
214 clock-frequency = <1000000>;
215 };
216
217 mailbox: mailbox@7c013880 {
218 compatible = "brcm,bcm2835-mbox";
219 reg = <0x7c013880 0x40>;
220 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
221 #mbox-cells = <0>;
222 };
223
224 local_intc: interrupt-controller@7cd00000 {
225 compatible = "brcm,bcm2836-l1-intc";
226 reg = <0x7cd00000 0x100>;
227 };
228
229 uart10: serial@7d001000 {
230 compatible = "arm,pl011", "arm,primecell";
231 reg = <0x7d001000 0x200>;
232 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clk_uart>, <&clk_vpu>;
234 clock-names = "uartclk", "apb_pclk";
235 arm,primecell-periphid = <0x00241011>;
236 status = "disabled";
237 };
238
239 interrupt-controller@7d517000 {
240 compatible = "brcm,bcm7271-l2-intc";
241 reg = <0x7d517000 0x10>;
242 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-controller;
244 #interrupt-cells = <1>;
245 };
246
247 gio_aon: gpio@7d517c00 {
248 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
249 reg = <0x7d517c00 0x40>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 brcm,gpio-bank-widths = <17 6>;
253 /* The lack of 'interrupt-controller' property here is intended:
254 * don't use GIO_AON as an interrupt controller because it will
255 * clash with the firmware monitoring the PMIC interrupt via the VPU.
256 */
257 };
258
259 gicv2: interrupt-controller@7fff9000 {
260 compatible = "arm,gic-400";
261 reg = <0x7fff9000 0x1000>,
262 <0x7fffa000 0x2000>,
263 <0x7fffc000 0x2000>,
264 <0x7fffe000 0x2000>;
265 interrupt-controller;
266 #interrupt-cells = <3>;
267 };
268 };
269
270 timer {
271 compatible = "arm,armv8-timer";
272 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
273 IRQ_TYPE_LEVEL_LOW)>,
274 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
275 IRQ_TYPE_LEVEL_LOW)>,
276 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
277 IRQ_TYPE_LEVEL_LOW)>,
278 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
279 IRQ_TYPE_LEVEL_LOW)>,
280 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
281 IRQ_TYPE_LEVEL_LOW)>;
282 };
283 };
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