1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 Broadcom Ltd.
4 */
5
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8
9 / {
10 compatible = "brcm,bcm4912", "brcm,bcmbca";
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 interrupt-parent = <&gic>;
15
16 cpus {
17 #address-cells = <2>;
18 #size-cells = <0>;
19
20 B53_0: cpu@0 {
21 compatible = "brcm,brahma-b53";
22 device_type = "cpu";
23 reg = <0x0 0x0>;
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
26 };
27
28 B53_1: cpu@1 {
29 compatible = "brcm,brahma-b53";
30 device_type = "cpu";
31 reg = <0x0 0x1>;
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
34 };
35
36 B53_2: cpu@2 {
37 compatible = "brcm,brahma-b53";
38 device_type = "cpu";
39 reg = <0x0 0x2>;
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
42 };
43
44 B53_3: cpu@3 {
45 compatible = "brcm,brahma-b53";
46 device_type = "cpu";
47 reg = <0x0 0x3>;
48 next-level-cache = <&L2_0>;
49 enable-method = "psci";
50 };
51
52 L2_0: l2-cache0 {
53 compatible = "cache";
54 cache-level = <2>;
55 cache-unified;
56 };
57 };
58
59 timer {
60 compatible = "arm,armv8-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 };
66
67 pmu: pmu {
68 compatible = "arm,cortex-a53-pmu";
69 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
73 interrupt-affinity = <&B53_0>, <&B53_1>,
74 <&B53_2>, <&B53_3>;
75 };
76
77 clocks: clocks {
78 periph_clk: periph-clk {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <200000000>;
82 };
83
84 uart_clk: uart-clk {
85 compatible = "fixed-factor-clock";
86 #clock-cells = <0>;
87 clocks = <&periph_clk>;
88 clock-div = <4>;
89 clock-mult = <1>;
90 };
91
92 hsspi_pll: hsspi-pll {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <200000000>;
96 };
97 };
98
99 psci {
100 compatible = "arm,psci-0.2";
101 method = "smc";
102 };
103
104 axi@81000000 {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0x0 0x0 0x81000000 0x8000>;
109
110 gic: interrupt-controller@1000 {
111 compatible = "arm,gic-400";
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
115 reg = <0x1000 0x1000>,
116 <0x2000 0x2000>,
117 <0x4000 0x2000>,
118 <0x6000 0x2000>;
119 };
120 };
121
122 bus@ff800000 {
123 compatible = "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges = <0x0 0x0 0xff800000 0x800000>;
127
128 hsspi: spi@1000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
132 reg = <0x1000 0x600>, <0x2610 0x4>;
133 reg-names = "hsspi", "spim-ctrl";
134 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&hsspi_pll &hsspi_pll>;
136 clock-names = "hsspi", "pll";
137 num-cs = <8>;
138 status = "disabled";
139 };
140
141 nand_controller: nand-controller@1800 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
145 reg = <0x1800 0x600>, <0x2000 0x10>;
146 reg-names = "nand", "nand-int-base";
147 status = "disabled";
148
149 nandcs: nand@0 {
150 compatible = "brcm,nandcs";
151 reg = <0>;
152 };
153 };
154
155 uart0: serial@12000 {
156 compatible = "arm,pl011", "arm,primecell";
157 reg = <0x12000 0x1000>;
158 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&uart_clk>, <&uart_clk>;
160 clock-names = "uartclk", "apb_pclk";
161 status = "disabled";
162 };
163 };
164 };
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