1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5433 SoC device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 *
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
9 * values for board specific bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
13 * additional nodes can be added to this file.
14 */
15
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18
19 / {
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 interrupt-parent = <&gic>;
25
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
28 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
33 };
34
35 arm-a57-pmu {
36 compatible = "arm,cortex-a57-pmu";
37 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
42 };
43
44 xxti: clock {
45 /* XXTI */
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
48 #clock-cells = <0>;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu-map {
56 cluster0 {
57 core0 {
58 cpu = <&cpu0>;
59 };
60 core1 {
61 cpu = <&cpu1>;
62 };
63 core2 {
64 cpu = <&cpu2>;
65 };
66 core3 {
67 cpu = <&cpu3>;
68 };
69 };
70
71 cluster1 {
72 core0 {
73 cpu = <&cpu4>;
74 };
75 core1 {
76 cpu = <&cpu5>;
77 };
78 core2 {
79 cpu = <&cpu6>;
80 };
81 core3 {
82 cpu = <&cpu7>;
83 };
84 };
85 };
86
87 cpu0: cpu@100 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 reg = <0x100>;
92 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
93 clock-names = "apolloclk";
94 operating-points-v2 = <&cluster_a53_opp_table>;
95 #cooling-cells = <2>;
96 i-cache-size = <0x8000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000>;
100 d-cache-line-size = <64>;
101 d-cache-sets = <128>;
102 next-level-cache = <&cluster_a53_l2>;
103 };
104
105 cpu1: cpu@101 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53";
108 enable-method = "psci";
109 reg = <0x101>;
110 operating-points-v2 = <&cluster_a53_opp_table>;
111 #cooling-cells = <2>;
112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
118 next-level-cache = <&cluster_a53_l2>;
119 };
120
121 cpu2: cpu@102 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a53";
124 enable-method = "psci";
125 reg = <0x102>;
126 operating-points-v2 = <&cluster_a53_opp_table>;
127 #cooling-cells = <2>;
128 i-cache-size = <0x8000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <128>;
134 next-level-cache = <&cluster_a53_l2>;
135 };
136
137 cpu3: cpu@103 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a53";
140 enable-method = "psci";
141 reg = <0x103>;
142 operating-points-v2 = <&cluster_a53_opp_table>;
143 #cooling-cells = <2>;
144 i-cache-size = <0x8000>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <0x8000>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <128>;
150 next-level-cache = <&cluster_a53_l2>;
151 };
152
153 cpu4: cpu@0 {
154 device_type = "cpu";
155 compatible = "arm,cortex-a57";
156 enable-method = "psci";
157 reg = <0x0>;
158 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
159 clock-names = "atlasclk";
160 operating-points-v2 = <&cluster_a57_opp_table>;
161 #cooling-cells = <2>;
162 i-cache-size = <0xc000>;
163 i-cache-line-size = <64>;
164 i-cache-sets = <256>;
165 d-cache-size = <0x8000>;
166 d-cache-line-size = <64>;
167 d-cache-sets = <256>;
168 next-level-cache = <&cluster_a57_l2>;
169 };
170
171 cpu5: cpu@1 {
172 device_type = "cpu";
173 compatible = "arm,cortex-a57";
174 enable-method = "psci";
175 reg = <0x1>;
176 operating-points-v2 = <&cluster_a57_opp_table>;
177 #cooling-cells = <2>;
178 i-cache-size = <0xc000>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <0x8000>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <256>;
184 next-level-cache = <&cluster_a57_l2>;
185 };
186
187 cpu6: cpu@2 {
188 device_type = "cpu";
189 compatible = "arm,cortex-a57";
190 enable-method = "psci";
191 reg = <0x2>;
192 operating-points-v2 = <&cluster_a57_opp_table>;
193 #cooling-cells = <2>;
194 i-cache-size = <0xc000>;
195 i-cache-line-size = <64>;
196 i-cache-sets = <256>;
197 d-cache-size = <0x8000>;
198 d-cache-line-size = <64>;
199 d-cache-sets = <256>;
200 next-level-cache = <&cluster_a57_l2>;
201 };
202
203 cpu7: cpu@3 {
204 device_type = "cpu";
205 compatible = "arm,cortex-a57";
206 enable-method = "psci";
207 reg = <0x3>;
208 operating-points-v2 = <&cluster_a57_opp_table>;
209 #cooling-cells = <2>;
210 i-cache-size = <0xc000>;
211 i-cache-line-size = <64>;
212 i-cache-sets = <256>;
213 d-cache-size = <0x8000>;
214 d-cache-line-size = <64>;
215 d-cache-sets = <256>;
216 next-level-cache = <&cluster_a57_l2>;
217 };
218
219 cluster_a57_l2: l2-cache0 {
220 compatible = "cache";
221 cache-level = <2>;
222 cache-unified;
223 cache-size = <0x200000>;
224 cache-line-size = <64>;
225 cache-sets = <2048>;
226 };
227
228 cluster_a53_l2: l2-cache1 {
229 compatible = "cache";
230 cache-level = <2>;
231 cache-unified;
232 cache-size = <0x40000>;
233 cache-line-size = <64>;
234 cache-sets = <256>;
235 };
236 };
237
238 cluster_a53_opp_table: opp-table-0 {
239 compatible = "operating-points-v2";
240 opp-shared;
241
242 opp-400000000 {
243 opp-hz = /bits/ 64 <400000000>;
244 opp-microvolt = <900000>;
245 };
246 opp-500000000 {
247 opp-hz = /bits/ 64 <500000000>;
248 opp-microvolt = <925000>;
249 };
250 opp-600000000 {
251 opp-hz = /bits/ 64 <600000000>;
252 opp-microvolt = <950000>;
253 };
254 opp-700000000 {
255 opp-hz = /bits/ 64 <700000000>;
256 opp-microvolt = <975000>;
257 };
258 opp-800000000 {
259 opp-hz = /bits/ 64 <800000000>;
260 opp-microvolt = <1000000>;
261 };
262 opp-900000000 {
263 opp-hz = /bits/ 64 <900000000>;
264 opp-microvolt = <1050000>;
265 };
266 opp-1000000000 {
267 opp-hz = /bits/ 64 <1000000000>;
268 opp-microvolt = <1075000>;
269 };
270 opp-1100000000 {
271 opp-hz = /bits/ 64 <1100000000>;
272 opp-microvolt = <1112500>;
273 };
274 opp-1200000000 {
275 opp-hz = /bits/ 64 <1200000000>;
276 opp-microvolt = <1112500>;
277 };
278 opp-1300000000 {
279 opp-hz = /bits/ 64 <1300000000>;
280 opp-microvolt = <1150000>;
281 };
282 };
283
284 cluster_a57_opp_table: opp-table-1 {
285 compatible = "operating-points-v2";
286 opp-shared;
287
288 opp-500000000 {
289 opp-hz = /bits/ 64 <500000000>;
290 opp-microvolt = <900000>;
291 };
292 opp-600000000 {
293 opp-hz = /bits/ 64 <600000000>;
294 opp-microvolt = <900000>;
295 };
296 opp-700000000 {
297 opp-hz = /bits/ 64 <700000000>;
298 opp-microvolt = <912500>;
299 };
300 opp-800000000 {
301 opp-hz = /bits/ 64 <800000000>;
302 opp-microvolt = <912500>;
303 };
304 opp-900000000 {
305 opp-hz = /bits/ 64 <900000000>;
306 opp-microvolt = <937500>;
307 };
308 opp-1000000000 {
309 opp-hz = /bits/ 64 <1000000000>;
310 opp-microvolt = <975000>;
311 };
312 opp-1100000000 {
313 opp-hz = /bits/ 64 <1100000000>;
314 opp-microvolt = <1012500>;
315 };
316 opp-1200000000 {
317 opp-hz = /bits/ 64 <1200000000>;
318 opp-microvolt = <1037500>;
319 };
320 opp-1300000000 {
321 opp-hz = /bits/ 64 <1300000000>;
322 opp-microvolt = <1062500>;
323 };
324 opp-1400000000 {
325 opp-hz = /bits/ 64 <1400000000>;
326 opp-microvolt = <1087500>;
327 };
328 opp-1500000000 {
329 opp-hz = /bits/ 64 <1500000000>;
330 opp-microvolt = <1125000>;
331 };
332 opp-1600000000 {
333 opp-hz = /bits/ 64 <1600000000>;
334 opp-microvolt = <1137500>;
335 };
336 opp-1700000000 {
337 opp-hz = /bits/ 64 <1700000000>;
338 opp-microvolt = <1175000>;
339 };
340 opp-1800000000 {
341 opp-hz = /bits/ 64 <1800000000>;
342 opp-microvolt = <1212500>;
343 };
344 opp-1900000000 {
345 opp-hz = /bits/ 64 <1900000000>;
346 opp-microvolt = <1262500>;
347 };
348 };
349
350 psci {
351 compatible = "arm,psci";
352 method = "smc";
353 cpu_off = <0x84000002>;
354 cpu_on = <0xc4000003>;
355 };
356
357 soc: soc@0 {
358 compatible = "simple-bus";
359 #address-cells = <1>;
360 #size-cells = <1>;
361 ranges = <0x0 0x0 0x0 0x18000000>;
362
363 chipid@10000000 {
364 compatible = "samsung,exynos5433-chipid",
365 "samsung,exynos4210-chipid";
366 reg = <0x10000000 0x100>;
367 };
368
369 cmu_top: clock-controller@10030000 {
370 compatible = "samsung,exynos5433-cmu-top";
371 reg = <0x10030000 0x1000>;
372 #clock-cells = <1>;
373
374 clock-names = "oscclk",
375 "sclk_mphy_pll",
376 "sclk_mfc_pll",
377 "sclk_bus_pll";
378 clocks = <&xxti>,
379 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
380 <&cmu_mif CLK_SCLK_MFC_PLL>,
381 <&cmu_mif CLK_SCLK_BUS_PLL>;
382 };
383
384 cmu_cpif: clock-controller@10fc0000 {
385 compatible = "samsung,exynos5433-cmu-cpif";
386 reg = <0x10fc0000 0x1000>;
387 #clock-cells = <1>;
388
389 clock-names = "oscclk";
390 clocks = <&xxti>;
391 };
392
393 cmu_mif: clock-controller@105b0000 {
394 compatible = "samsung,exynos5433-cmu-mif";
395 reg = <0x105b0000 0x2000>;
396 #clock-cells = <1>;
397
398 clock-names = "oscclk",
399 "sclk_mphy_pll";
400 clocks = <&xxti>,
401 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
402 };
403
404 cmu_peric: clock-controller@14c80000 {
405 compatible = "samsung,exynos5433-cmu-peric";
406 reg = <0x14c80000 0x1000>;
407 #clock-cells = <1>;
408 };
409
410 cmu_peris: clock-controller@10040000 {
411 compatible = "samsung,exynos5433-cmu-peris";
412 reg = <0x10040000 0x1000>;
413 #clock-cells = <1>;
414 };
415
416 cmu_fsys: clock-controller@156e0000 {
417 compatible = "samsung,exynos5433-cmu-fsys";
418 reg = <0x156e0000 0x1000>;
419 #clock-cells = <1>;
420
421 clock-names = "oscclk",
422 "sclk_ufs_mphy",
423 "aclk_fsys_200",
424 "sclk_pcie_100_fsys",
425 "sclk_ufsunipro_fsys",
426 "sclk_mmc2_fsys",
427 "sclk_mmc1_fsys",
428 "sclk_mmc0_fsys",
429 "sclk_usbhost30_fsys",
430 "sclk_usbdrd30_fsys";
431 clocks = <&xxti>,
432 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
433 <&cmu_top CLK_ACLK_FSYS_200>,
434 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
435 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
436 <&cmu_top CLK_SCLK_MMC2_FSYS>,
437 <&cmu_top CLK_SCLK_MMC1_FSYS>,
438 <&cmu_top CLK_SCLK_MMC0_FSYS>,
439 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
440 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
441 };
442
443 cmu_g2d: clock-controller@12460000 {
444 compatible = "samsung,exynos5433-cmu-g2d";
445 reg = <0x12460000 0x1000>;
446 #clock-cells = <1>;
447
448 clock-names = "oscclk",
449 "aclk_g2d_266",
450 "aclk_g2d_400";
451 clocks = <&xxti>,
452 <&cmu_top CLK_ACLK_G2D_266>,
453 <&cmu_top CLK_ACLK_G2D_400>;
454 power-domains = <&pd_g2d>;
455 };
456
457 cmu_disp: clock-controller@13b90000 {
458 compatible = "samsung,exynos5433-cmu-disp";
459 reg = <0x13b90000 0x1000>;
460 #clock-cells = <1>;
461
462 clock-names = "oscclk",
463 "sclk_dsim1_disp",
464 "sclk_dsim0_disp",
465 "sclk_dsd_disp",
466 "sclk_decon_tv_eclk_disp",
467 "sclk_decon_vclk_disp",
468 "sclk_decon_eclk_disp",
469 "sclk_decon_tv_vclk_disp",
470 "aclk_disp_333";
471 clocks = <&xxti>,
472 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
473 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
474 <&cmu_mif CLK_SCLK_DSD_DISP>,
475 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
476 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
477 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
478 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
479 <&cmu_mif CLK_ACLK_DISP_333>;
480 power-domains = <&pd_disp>;
481 };
482
483 cmu_aud: clock-controller@114c0000 {
484 compatible = "samsung,exynos5433-cmu-aud";
485 reg = <0x114c0000 0x1000>;
486 #clock-cells = <1>;
487 clock-names = "oscclk", "fout_aud_pll";
488 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
489 power-domains = <&pd_aud>;
490 };
491
492 cmu_bus0: clock-controller@13600000 {
493 compatible = "samsung,exynos5433-cmu-bus0";
494 reg = <0x13600000 0x1000>;
495 #clock-cells = <1>;
496
497 clock-names = "aclk_bus0_400";
498 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
499 };
500
501 cmu_bus1: clock-controller@14800000 {
502 compatible = "samsung,exynos5433-cmu-bus1";
503 reg = <0x14800000 0x1000>;
504 #clock-cells = <1>;
505
506 clock-names = "aclk_bus1_400";
507 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
508 };
509
510 cmu_bus2: clock-controller@13400000 {
511 compatible = "samsung,exynos5433-cmu-bus2";
512 reg = <0x13400000 0x1000>;
513 #clock-cells = <1>;
514
515 clock-names = "oscclk", "aclk_bus2_400";
516 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
517 };
518
519 cmu_g3d: clock-controller@14aa0000 {
520 compatible = "samsung,exynos5433-cmu-g3d";
521 reg = <0x14aa0000 0x2000>;
522 #clock-cells = <1>;
523
524 clock-names = "oscclk", "aclk_g3d_400";
525 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
526 power-domains = <&pd_g3d>;
527 };
528
529 cmu_gscl: clock-controller@13cf0000 {
530 compatible = "samsung,exynos5433-cmu-gscl";
531 reg = <0x13cf0000 0x1000>;
532 #clock-cells = <1>;
533
534 clock-names = "oscclk",
535 "aclk_gscl_111",
536 "aclk_gscl_333";
537 clocks = <&xxti>,
538 <&cmu_top CLK_ACLK_GSCL_111>,
539 <&cmu_top CLK_ACLK_GSCL_333>;
540 power-domains = <&pd_gscl>;
541 };
542
543 cmu_apollo: clock-controller@11900000 {
544 compatible = "samsung,exynos5433-cmu-apollo";
545 reg = <0x11900000 0x2000>;
546 #clock-cells = <1>;
547
548 clock-names = "oscclk", "sclk_bus_pll_apollo";
549 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
550 };
551
552 cmu_atlas: clock-controller@11800000 {
553 compatible = "samsung,exynos5433-cmu-atlas";
554 reg = <0x11800000 0x2000>;
555 #clock-cells = <1>;
556
557 clock-names = "oscclk", "sclk_bus_pll_atlas";
558 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
559 };
560
561 cmu_mscl: clock-controller@150d0000 {
562 compatible = "samsung,exynos5433-cmu-mscl";
563 reg = <0x150d0000 0x1000>;
564 #clock-cells = <1>;
565
566 clock-names = "oscclk",
567 "sclk_jpeg_mscl",
568 "aclk_mscl_400";
569 clocks = <&xxti>,
570 <&cmu_top CLK_SCLK_JPEG_MSCL>,
571 <&cmu_top CLK_ACLK_MSCL_400>;
572 power-domains = <&pd_mscl>;
573 };
574
575 cmu_mfc: clock-controller@15280000 {
576 compatible = "samsung,exynos5433-cmu-mfc";
577 reg = <0x15280000 0x1000>;
578 #clock-cells = <1>;
579
580 clock-names = "oscclk", "aclk_mfc_400";
581 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
582 power-domains = <&pd_mfc>;
583 };
584
585 cmu_hevc: clock-controller@14f80000 {
586 compatible = "samsung,exynos5433-cmu-hevc";
587 reg = <0x14f80000 0x1000>;
588 #clock-cells = <1>;
589
590 clock-names = "oscclk", "aclk_hevc_400";
591 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
592 power-domains = <&pd_hevc>;
593 };
594
595 cmu_isp: clock-controller@146d0000 {
596 compatible = "samsung,exynos5433-cmu-isp";
597 reg = <0x146d0000 0x1000>;
598 #clock-cells = <1>;
599
600 clock-names = "oscclk",
601 "aclk_isp_dis_400",
602 "aclk_isp_400";
603 clocks = <&xxti>,
604 <&cmu_top CLK_ACLK_ISP_DIS_400>,
605 <&cmu_top CLK_ACLK_ISP_400>;
606 power-domains = <&pd_isp>;
607 };
608
609 cmu_cam0: clock-controller@120d0000 {
610 compatible = "samsung,exynos5433-cmu-cam0";
611 reg = <0x120d0000 0x1000>;
612 #clock-cells = <1>;
613
614 clock-names = "oscclk",
615 "aclk_cam0_333",
616 "aclk_cam0_400",
617 "aclk_cam0_552";
618 clocks = <&xxti>,
619 <&cmu_top CLK_ACLK_CAM0_333>,
620 <&cmu_top CLK_ACLK_CAM0_400>,
621 <&cmu_top CLK_ACLK_CAM0_552>;
622 power-domains = <&pd_cam0>;
623 };
624
625 cmu_cam1: clock-controller@145d0000 {
626 compatible = "samsung,exynos5433-cmu-cam1";
627 reg = <0x145d0000 0x1000>;
628 #clock-cells = <1>;
629
630 clock-names = "oscclk",
631 "sclk_isp_uart_cam1",
632 "sclk_isp_spi1_cam1",
633 "sclk_isp_spi0_cam1",
634 "aclk_cam1_333",
635 "aclk_cam1_400",
636 "aclk_cam1_552";
637 clocks = <&xxti>,
638 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
639 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
640 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
641 <&cmu_top CLK_ACLK_CAM1_333>,
642 <&cmu_top CLK_ACLK_CAM1_400>,
643 <&cmu_top CLK_ACLK_CAM1_552>;
644 power-domains = <&pd_cam1>;
645 };
646
647 cmu_imem: clock-controller@11060000 {
648 compatible = "samsung,exynos5433-cmu-imem";
649 reg = <0x11060000 0x1000>;
650 #clock-cells = <1>;
651
652 clock-names = "oscclk",
653 "aclk_imem_sssx_266",
654 "aclk_imem_266",
655 "aclk_imem_200";
656 clocks = <&xxti>,
657 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
658 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
659 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
660 };
661
662 slim_sss: slim-sss@11140000 {
663 compatible = "samsung,exynos5433-slim-sss";
664 reg = <0x11140000 0x1000>;
665 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
666 clock-names = "pclk", "aclk";
667 clocks = <&cmu_imem CLK_PCLK_SLIMSSS>,
668 <&cmu_imem CLK_ACLK_SLIMSSS>;
669 };
670
671 pd_gscl: power-domain@105c4000 {
672 compatible = "samsung,exynos5433-pd";
673 reg = <0x105c4000 0x20>;
674 #power-domain-cells = <0>;
675 label = "GSCL";
676 };
677
678 pd_cam0: power-domain@105c4020 {
679 compatible = "samsung,exynos5433-pd";
680 reg = <0x105c4020 0x20>;
681 #power-domain-cells = <0>;
682 power-domains = <&pd_cam1>;
683 label = "CAM0";
684 };
685
686 pd_mscl: power-domain@105c4040 {
687 compatible = "samsung,exynos5433-pd";
688 reg = <0x105c4040 0x20>;
689 #power-domain-cells = <0>;
690 label = "MSCL";
691 };
692
693 pd_g3d: power-domain@105c4060 {
694 compatible = "samsung,exynos5433-pd";
695 reg = <0x105c4060 0x20>;
696 #power-domain-cells = <0>;
697 label = "G3D";
698 };
699
700 pd_disp: power-domain@105c4080 {
701 compatible = "samsung,exynos5433-pd";
702 reg = <0x105c4080 0x20>;
703 #power-domain-cells = <0>;
704 label = "DISP";
705 };
706
707 pd_cam1: power-domain@105c40a0 {
708 compatible = "samsung,exynos5433-pd";
709 reg = <0x105c40a0 0x20>;
710 #power-domain-cells = <0>;
711 label = "CAM1";
712 };
713
714 pd_aud: power-domain@105c40c0 {
715 compatible = "samsung,exynos5433-pd";
716 reg = <0x105c40c0 0x20>;
717 #power-domain-cells = <0>;
718 label = "AUD";
719 };
720
721 pd_g2d: power-domain@105c4120 {
722 compatible = "samsung,exynos5433-pd";
723 reg = <0x105c4120 0x20>;
724 #power-domain-cells = <0>;
725 label = "G2D";
726 };
727
728 pd_isp: power-domain@105c4140 {
729 compatible = "samsung,exynos5433-pd";
730 reg = <0x105c4140 0x20>;
731 #power-domain-cells = <0>;
732 power-domains = <&pd_cam0>;
733 label = "ISP";
734 };
735
736 pd_mfc: power-domain@105c4180 {
737 compatible = "samsung,exynos5433-pd";
738 reg = <0x105c4180 0x20>;
739 #power-domain-cells = <0>;
740 label = "MFC";
741 };
742
743 pd_hevc: power-domain@105c41c0 {
744 compatible = "samsung,exynos5433-pd";
745 reg = <0x105c41c0 0x20>;
746 #power-domain-cells = <0>;
747 label = "HEVC";
748 };
749
750 tmu_atlas0: tmu@10060000 {
751 compatible = "samsung,exynos5433-tmu";
752 reg = <0x10060000 0x200>;
753 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
755 <&cmu_peris CLK_SCLK_TMU0>;
756 clock-names = "tmu_apbif", "tmu_sclk";
757 #thermal-sensor-cells = <0>;
758 status = "disabled";
759 };
760
761 tmu_atlas1: tmu@10068000 {
762 compatible = "samsung,exynos5433-tmu";
763 reg = <0x10068000 0x200>;
764 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
766 <&cmu_peris CLK_SCLK_TMU0>;
767 clock-names = "tmu_apbif", "tmu_sclk";
768 #thermal-sensor-cells = <0>;
769 status = "disabled";
770 };
771
772 tmu_g3d: tmu@10070000 {
773 compatible = "samsung,exynos5433-tmu";
774 reg = <0x10070000 0x200>;
775 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
777 <&cmu_peris CLK_SCLK_TMU1>;
778 clock-names = "tmu_apbif", "tmu_sclk";
779 #thermal-sensor-cells = <0>;
780 status = "disabled";
781 };
782
783 tmu_apollo: tmu@10078000 {
784 compatible = "samsung,exynos5433-tmu";
785 reg = <0x10078000 0x200>;
786 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
788 <&cmu_peris CLK_SCLK_TMU1>;
789 clock-names = "tmu_apbif", "tmu_sclk";
790 #thermal-sensor-cells = <0>;
791 status = "disabled";
792 };
793
794 tmu_isp: tmu@1007c000 {
795 compatible = "samsung,exynos5433-tmu";
796 reg = <0x1007c000 0x200>;
797 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
799 <&cmu_peris CLK_SCLK_TMU1>;
800 clock-names = "tmu_apbif", "tmu_sclk";
801 #thermal-sensor-cells = <0>;
802 status = "disabled";
803 };
804
805 timer@101c0000 {
806 compatible = "samsung,exynos5433-mct",
807 "samsung,exynos4210-mct";
808 reg = <0x101c0000 0x800>;
809 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
822 clock-names = "fin_pll", "mct";
823 };
824
825 ppmu_d0_cpu: ppmu@10480000 {
826 compatible = "samsung,exynos-ppmu-v2";
827 reg = <0x10480000 0x2000>;
828 status = "disabled";
829 };
830
831 ppmu_d0_general: ppmu@10490000 {
832 compatible = "samsung,exynos-ppmu-v2";
833 reg = <0x10490000 0x2000>;
834 status = "disabled";
835 };
836
837 ppmu_d1_cpu: ppmu@104b0000 {
838 compatible = "samsung,exynos-ppmu-v2";
839 reg = <0x104b0000 0x2000>;
840 status = "disabled";
841 };
842
843 ppmu_d1_general: ppmu@104c0000 {
844 compatible = "samsung,exynos-ppmu-v2";
845 reg = <0x104c0000 0x2000>;
846 status = "disabled";
847 };
848
849 pinctrl_alive: pinctrl@10580000 {
850 compatible = "samsung,exynos5433-pinctrl";
851 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
852
853 wakeup-interrupt-controller {
854 compatible = "samsung,exynos5433-wakeup-eint",
855 "samsung,exynos7-wakeup-eint";
856 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
857 };
858 };
859
860 pinctrl_aud: pinctrl@114b0000 {
861 compatible = "samsung,exynos5433-pinctrl";
862 reg = <0x114b0000 0x1000>;
863 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
864 power-domains = <&pd_aud>;
865 };
866
867 pinctrl_cpif: pinctrl@10fe0000 {
868 compatible = "samsung,exynos5433-pinctrl";
869 reg = <0x10fe0000 0x1000>;
870 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
871 };
872
873 pinctrl_ese: pinctrl@14ca0000 {
874 compatible = "samsung,exynos5433-pinctrl";
875 reg = <0x14ca0000 0x1000>;
876 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
877 };
878
879 pinctrl_finger: pinctrl@14cb0000 {
880 compatible = "samsung,exynos5433-pinctrl";
881 reg = <0x14cb0000 0x1000>;
882 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
883 };
884
885 pinctrl_fsys: pinctrl@15690000 {
886 compatible = "samsung,exynos5433-pinctrl";
887 reg = <0x15690000 0x1000>;
888 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
889 };
890
891 pinctrl_imem: pinctrl@11090000 {
892 compatible = "samsung,exynos5433-pinctrl";
893 reg = <0x11090000 0x1000>;
894 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
895 };
896
897 pinctrl_nfc: pinctrl@14cd0000 {
898 compatible = "samsung,exynos5433-pinctrl";
899 reg = <0x14cd0000 0x1000>;
900 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
901 };
902
903 pinctrl_peric: pinctrl@14cc0000 {
904 compatible = "samsung,exynos5433-pinctrl";
905 reg = <0x14cc0000 0x1100>;
906 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
907 };
908
909 pinctrl_touch: pinctrl@14ce0000 {
910 compatible = "samsung,exynos5433-pinctrl";
911 reg = <0x14ce0000 0x1100>;
912 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
913 };
914
915 pmu_system_controller: system-controller@105c0000 {
916 compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon";
917 reg = <0x105c0000 0x5008>;
918 #clock-cells = <1>;
919 clock-names = "clkout16";
920 clocks = <&xxti>;
921
922 mipi_phy: mipi-phy {
923 compatible = "samsung,exynos5433-mipi-video-phy";
924 #phy-cells = <1>;
925 samsung,cam0-sysreg = <&syscon_cam0>;
926 samsung,cam1-sysreg = <&syscon_cam1>;
927 samsung,disp-sysreg = <&syscon_disp>;
928 };
929
930 reboot: syscon-reboot {
931 compatible = "syscon-reboot";
932 regmap = <&pmu_system_controller>;
933 offset = <0x400>; /* SWRESET */
934 mask = <0x1>;
935 };
936 };
937
938 gic: interrupt-controller@11001000 {
939 compatible = "arm,gic-400";
940 #interrupt-cells = <3>;
941 interrupt-controller;
942 reg = <0x11001000 0x1000>,
943 <0x11002000 0x2000>,
944 <0x11004000 0x2000>,
945 <0x11006000 0x2000>;
946 interrupts = <GIC_PPI 9 0xf04>;
947 };
948
949 decon: decon@13800000 {
950 compatible = "samsung,exynos5433-decon";
951 reg = <0x13800000 0x2104>;
952 clocks = <&cmu_disp CLK_PCLK_DECON>,
953 <&cmu_disp CLK_ACLK_DECON>,
954 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
955 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
956 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
957 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
958 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
959 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
960 <&cmu_disp CLK_SCLK_DECON_VCLK>,
961 <&cmu_disp CLK_SCLK_DECON_ECLK>,
962 <&cmu_disp CLK_SCLK_DSD>;
963 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
964 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
965 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
966 "pclk_smmu_decon1x", "sclk_decon_vclk",
967 "sclk_decon_eclk", "dsd";
968 power-domains = <&pd_disp>;
969 interrupt-names = "fifo", "vsync", "lcd_sys";
970 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
973 samsung,disp-sysreg = <&syscon_disp>;
974 status = "disabled";
975 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
976 iommu-names = "m0", "m1";
977
978 ports {
979 #address-cells = <1>;
980 #size-cells = <0>;
981
982 port@0 {
983 reg = <0>;
984 decon_to_mic: endpoint {
985 remote-endpoint =
986 <&mic_to_decon>;
987 };
988 };
989 };
990 };
991
992 decon_tv: decon@13880000 {
993 compatible = "samsung,exynos5433-decon-tv";
994 reg = <0x13880000 0x20b8>;
995 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
996 <&cmu_disp CLK_ACLK_DECON_TV>,
997 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
998 <&cmu_disp CLK_ACLK_XIU_TV0X>,
999 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1000 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1001 <&cmu_disp CLK_ACLK_XIU_TV1X>,
1002 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1003 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
1004 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
1005 <&cmu_disp CLK_SCLK_DSD>;
1006 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
1007 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
1008 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
1009 "pclk_smmu_decon1x", "sclk_decon_vclk",
1010 "sclk_decon_eclk", "dsd";
1011 samsung,disp-sysreg = <&syscon_disp>;
1012 power-domains = <&pd_disp>;
1013 interrupt-names = "fifo", "vsync", "lcd_sys";
1014 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1017 status = "disabled";
1018 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
1019 iommu-names = "m0", "m1";
1020 };
1021
1022 dsi: dsi@13900000 {
1023 compatible = "samsung,exynos5433-mipi-dsi";
1024 reg = <0x13900000 0xc0>;
1025 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1026 phys = <&mipi_phy 1>;
1027 phy-names = "dsim";
1028 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
1029 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
1030 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
1031 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
1032 <&cmu_disp CLK_SCLK_DSIM0>;
1033 clock-names = "bus_clk",
1034 "phyclk_mipidphy0_bitclkdiv8",
1035 "phyclk_mipidphy0_rxclkesc0",
1036 "sclk_rgb_vclk_to_dsim0",
1037 "sclk_mipi";
1038 power-domains = <&pd_disp>;
1039 status = "disabled";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042
1043 ports {
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046
1047 port@0 {
1048 reg = <0>;
1049 dsi_to_mic: endpoint {
1050 remote-endpoint = <&mic_to_dsi>;
1051 };
1052 };
1053 };
1054 };
1055
1056 mic: mic@13930000 {
1057 compatible = "samsung,exynos5433-mic";
1058 reg = <0x13930000 0x48>;
1059 clocks = <&cmu_disp CLK_PCLK_MIC0>,
1060 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
1061 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
1062 power-domains = <&pd_disp>;
1063 samsung,disp-syscon = <&syscon_disp>;
1064 status = "disabled";
1065
1066 ports {
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069
1070 port@0 {
1071 reg = <0>;
1072 mic_to_decon: endpoint {
1073 remote-endpoint =
1074 <&decon_to_mic>;
1075 };
1076 };
1077
1078 port@1 {
1079 reg = <1>;
1080 mic_to_dsi: endpoint {
1081 remote-endpoint = <&dsi_to_mic>;
1082 };
1083 };
1084 };
1085 };
1086
1087 hdmi: hdmi@13970000 {
1088 compatible = "samsung,exynos5433-hdmi";
1089 reg = <0x13970000 0x70000>;
1090 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cmu_disp CLK_PCLK_HDMI>,
1092 <&cmu_disp CLK_PCLK_HDMIPHY>,
1093 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
1094 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
1095 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
1096 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
1097 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
1098 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
1099 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
1100 clock-names = "hdmi_pclk", "hdmi_i_pclk",
1101 "i_tmds_clk", "i_pixel_clk",
1102 "tmds_clko", "tmds_clko_user",
1103 "pixel_clko", "pixel_clko_user",
1104 "oscclk", "i_spdif_clk";
1105 phy = <&hdmiphy>;
1106 ddc = <&hsi2c_11>;
1107 samsung,syscon-phandle = <&pmu_system_controller>;
1108 samsung,sysreg-phandle = <&syscon_disp>;
1109 #sound-dai-cells = <0>;
1110 status = "disabled";
1111 };
1112
1113 hdmiphy: hdmiphy@13af0000 {
1114 reg = <0x13af0000 0x80>;
1115 };
1116
1117 syscon_disp: syscon@13b80000 {
1118 compatible = "samsung,exynos5433-disp-sysreg",
1119 "samsung,exynos5433-sysreg", "syscon";
1120 reg = <0x13b80000 0x1010>;
1121 };
1122
1123 syscon_cam0: syscon@120f0000 {
1124 compatible = "samsung,exynos5433-cam0-sysreg",
1125 "samsung,exynos5433-sysreg", "syscon";
1126 reg = <0x120f0000 0x1020>;
1127 };
1128
1129 syscon_cam1: syscon@145f0000 {
1130 compatible = "samsung,exynos5433-cam1-sysreg",
1131 "samsung,exynos5433-sysreg", "syscon";
1132 reg = <0x145f0000 0x1038>;
1133 };
1134
1135 syscon_fsys: syscon@156f0000 {
1136 compatible = "samsung,exynos5433-fsys-sysreg",
1137 "samsung,exynos5433-sysreg", "syscon";
1138 reg = <0x156f0000 0x1044>;
1139 };
1140
1141 gsc_0: video-scaler@13c00000 {
1142 compatible = "samsung,exynos5433-gsc";
1143 reg = <0x13c00000 0x1000>;
1144 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1145 clock-names = "pclk", "aclk", "aclk_xiu",
1146 "aclk_gsclbend", "gsd";
1147 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1148 <&cmu_gscl CLK_ACLK_GSCL0>,
1149 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1150 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1151 <&cmu_gscl CLK_ACLK_GSD>;
1152 iommus = <&sysmmu_gscl0>;
1153 power-domains = <&pd_gscl>;
1154 };
1155
1156 gsc_1: video-scaler@13c10000 {
1157 compatible = "samsung,exynos5433-gsc";
1158 reg = <0x13c10000 0x1000>;
1159 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1160 clock-names = "pclk", "aclk", "aclk_xiu",
1161 "aclk_gsclbend", "gsd";
1162 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1163 <&cmu_gscl CLK_ACLK_GSCL1>,
1164 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1165 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1166 <&cmu_gscl CLK_ACLK_GSD>;
1167 iommus = <&sysmmu_gscl1>;
1168 power-domains = <&pd_gscl>;
1169 };
1170
1171 gsc_2: video-scaler@13c20000 {
1172 compatible = "samsung,exynos5433-gsc";
1173 reg = <0x13c20000 0x1000>;
1174 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1175 clock-names = "pclk", "aclk", "aclk_xiu",
1176 "aclk_gsclbend", "gsd";
1177 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1178 <&cmu_gscl CLK_ACLK_GSCL2>,
1179 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1180 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1181 <&cmu_gscl CLK_ACLK_GSD>;
1182 iommus = <&sysmmu_gscl2>;
1183 power-domains = <&pd_gscl>;
1184 };
1185
1186 gpu: gpu@14ac0000 {
1187 compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1188 reg = <0x14ac0000 0x5000>;
1189 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1192 interrupt-names = "job", "mmu", "gpu";
1193 clocks = <&cmu_g3d CLK_ACLK_G3D>;
1194 clock-names = "core";
1195 power-domains = <&pd_g3d>;
1196 operating-points-v2 = <&gpu_opp_table>;
1197 status = "disabled";
1198
1199 gpu_opp_table: opp-table {
1200 compatible = "operating-points-v2";
1201
1202 opp-160000000 {
1203 opp-hz = /bits/ 64 <160000000>;
1204 opp-microvolt = <1000000>;
1205 };
1206 opp-267000000 {
1207 opp-hz = /bits/ 64 <267000000>;
1208 opp-microvolt = <1000000>;
1209 };
1210 opp-350000000 {
1211 opp-hz = /bits/ 64 <350000000>;
1212 opp-microvolt = <1025000>;
1213 };
1214 opp-420000000 {
1215 opp-hz = /bits/ 64 <420000000>;
1216 opp-microvolt = <1025000>;
1217 };
1218 opp-500000000 {
1219 opp-hz = /bits/ 64 <500000000>;
1220 opp-microvolt = <1075000>;
1221 };
1222 opp-550000000 {
1223 opp-hz = /bits/ 64 <550000000>;
1224 opp-microvolt = <1125000>;
1225 };
1226 opp-600000000 {
1227 opp-hz = /bits/ 64 <600000000>;
1228 opp-microvolt = <1150000>;
1229 };
1230 opp-700000000 {
1231 opp-hz = /bits/ 64 <700000000>;
1232 opp-microvolt = <1150000>;
1233 };
1234 };
1235 };
1236
1237 scaler_0: scaler@15000000 {
1238 compatible = "samsung,exynos5433-scaler";
1239 reg = <0x15000000 0x1294>;
1240 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1241 clock-names = "pclk", "aclk", "aclk_xiu";
1242 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1243 <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1244 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1245 iommus = <&sysmmu_scaler_0>;
1246 power-domains = <&pd_mscl>;
1247 };
1248
1249 scaler_1: scaler@15010000 {
1250 compatible = "samsung,exynos5433-scaler";
1251 reg = <0x15010000 0x1294>;
1252 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1253 clock-names = "pclk", "aclk", "aclk_xiu";
1254 clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1255 <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1256 <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1257 iommus = <&sysmmu_scaler_1>;
1258 power-domains = <&pd_mscl>;
1259 };
1260
1261 jpeg: codec@15020000 {
1262 compatible = "samsung,exynos5433-jpeg";
1263 reg = <0x15020000 0x10000>;
1264 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1265 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1266 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1267 <&cmu_mscl CLK_ACLK_JPEG>,
1268 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1269 <&cmu_mscl CLK_SCLK_JPEG>;
1270 iommus = <&sysmmu_jpeg>;
1271 power-domains = <&pd_mscl>;
1272 };
1273
1274 mfc: codec@152e0000 {
1275 compatible = "samsung,exynos5433-mfc";
1276 reg = <0x152e0000 0x10000>;
1277 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1278 clock-names = "pclk", "aclk", "aclk_xiu";
1279 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1280 <&cmu_mfc CLK_ACLK_MFC>,
1281 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1282 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1283 iommu-names = "left", "right";
1284 power-domains = <&pd_mfc>;
1285 };
1286
1287 sysmmu_decon0x: sysmmu@13a00000 {
1288 compatible = "samsung,exynos-sysmmu";
1289 reg = <0x13a00000 0x1000>;
1290 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1291 clock-names = "aclk", "pclk";
1292 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1293 <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
1294 power-domains = <&pd_disp>;
1295 #iommu-cells = <0>;
1296 };
1297
1298 sysmmu_decon1x: sysmmu@13a10000 {
1299 compatible = "samsung,exynos-sysmmu";
1300 reg = <0x13a10000 0x1000>;
1301 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1302 clock-names = "aclk", "pclk";
1303 clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1304 <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
1305 #iommu-cells = <0>;
1306 power-domains = <&pd_disp>;
1307 };
1308
1309 sysmmu_tv0x: sysmmu@13a20000 {
1310 compatible = "samsung,exynos-sysmmu";
1311 reg = <0x13a20000 0x1000>;
1312 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1313 clock-names = "aclk", "pclk";
1314 clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1315 <&cmu_disp CLK_PCLK_SMMU_TV0X>;
1316 #iommu-cells = <0>;
1317 power-domains = <&pd_disp>;
1318 };
1319
1320 sysmmu_tv1x: sysmmu@13a30000 {
1321 compatible = "samsung,exynos-sysmmu";
1322 reg = <0x13a30000 0x1000>;
1323 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1324 clock-names = "aclk", "pclk";
1325 clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1326 <&cmu_disp CLK_PCLK_SMMU_TV1X>;
1327 #iommu-cells = <0>;
1328 power-domains = <&pd_disp>;
1329 };
1330
1331 sysmmu_gscl0: sysmmu@13c80000 {
1332 compatible = "samsung,exynos-sysmmu";
1333 reg = <0x13c80000 0x1000>;
1334 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1335 clock-names = "aclk", "pclk";
1336 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1337 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1338 #iommu-cells = <0>;
1339 power-domains = <&pd_gscl>;
1340 };
1341
1342 sysmmu_gscl1: sysmmu@13c90000 {
1343 compatible = "samsung,exynos-sysmmu";
1344 reg = <0x13c90000 0x1000>;
1345 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1346 clock-names = "aclk", "pclk";
1347 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1348 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1349 #iommu-cells = <0>;
1350 power-domains = <&pd_gscl>;
1351 };
1352
1353 sysmmu_gscl2: sysmmu@13ca0000 {
1354 compatible = "samsung,exynos-sysmmu";
1355 reg = <0x13ca0000 0x1000>;
1356 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1357 clock-names = "aclk", "pclk";
1358 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1359 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1360 #iommu-cells = <0>;
1361 power-domains = <&pd_gscl>;
1362 };
1363
1364 sysmmu_scaler_0: sysmmu@15040000 {
1365 compatible = "samsung,exynos-sysmmu";
1366 reg = <0x15040000 0x1000>;
1367 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1368 clock-names = "aclk", "pclk";
1369 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1370 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
1371 #iommu-cells = <0>;
1372 power-domains = <&pd_mscl>;
1373 };
1374
1375 sysmmu_scaler_1: sysmmu@15050000 {
1376 compatible = "samsung,exynos-sysmmu";
1377 reg = <0x15050000 0x1000>;
1378 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1379 clock-names = "aclk", "pclk";
1380 clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1381 <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
1382 #iommu-cells = <0>;
1383 power-domains = <&pd_mscl>;
1384 };
1385
1386 sysmmu_jpeg: sysmmu@15060000 {
1387 compatible = "samsung,exynos-sysmmu";
1388 reg = <0x15060000 0x1000>;
1389 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1390 clock-names = "aclk", "pclk";
1391 clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1392 <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
1393 #iommu-cells = <0>;
1394 power-domains = <&pd_mscl>;
1395 };
1396
1397 sysmmu_mfc_0: sysmmu@15200000 {
1398 compatible = "samsung,exynos-sysmmu";
1399 reg = <0x15200000 0x1000>;
1400 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1401 clock-names = "aclk", "pclk";
1402 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1403 <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
1404 #iommu-cells = <0>;
1405 power-domains = <&pd_mfc>;
1406 };
1407
1408 sysmmu_mfc_1: sysmmu@15210000 {
1409 compatible = "samsung,exynos-sysmmu";
1410 reg = <0x15210000 0x1000>;
1411 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1412 clock-names = "aclk", "pclk";
1413 clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1414 <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
1415 #iommu-cells = <0>;
1416 power-domains = <&pd_mfc>;
1417 };
1418
1419 serial_0: serial@14c10000 {
1420 compatible = "samsung,exynos5433-uart";
1421 reg = <0x14c10000 0x100>;
1422 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1423 clocks = <&cmu_peric CLK_PCLK_UART0>,
1424 <&cmu_peric CLK_SCLK_UART0>;
1425 clock-names = "uart", "clk_uart_baud0";
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&uart0_bus>;
1428 status = "disabled";
1429 };
1430
1431 serial_1: serial@14c20000 {
1432 compatible = "samsung,exynos5433-uart";
1433 reg = <0x14c20000 0x100>;
1434 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1435 clocks = <&cmu_peric CLK_PCLK_UART1>,
1436 <&cmu_peric CLK_SCLK_UART1>;
1437 clock-names = "uart", "clk_uart_baud0";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&uart1_bus>;
1440 status = "disabled";
1441 };
1442
1443 serial_2: serial@14c30000 {
1444 compatible = "samsung,exynos5433-uart";
1445 reg = <0x14c30000 0x100>;
1446 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&cmu_peric CLK_PCLK_UART2>,
1448 <&cmu_peric CLK_SCLK_UART2>;
1449 clock-names = "uart", "clk_uart_baud0";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&uart2_bus>;
1452 status = "disabled";
1453 };
1454
1455 spi_0: spi@14d20000 {
1456 compatible = "samsung,exynos5433-spi";
1457 reg = <0x14d20000 0x100>;
1458 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&pdma0 9>, <&pdma0 8>;
1460 dma-names = "tx", "rx";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1464 <&cmu_peric CLK_SCLK_SPI0>,
1465 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1466 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1467 samsung,spi-src-clk = <0>;
1468 pinctrl-names = "default";
1469 pinctrl-0 = <&spi0_bus>;
1470 num-cs = <1>;
1471 fifo-depth = <256>;
1472 status = "disabled";
1473 };
1474
1475 spi_1: spi@14d30000 {
1476 compatible = "samsung,exynos5433-spi";
1477 reg = <0x14d30000 0x100>;
1478 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1479 dmas = <&pdma0 11>, <&pdma0 10>;
1480 dma-names = "tx", "rx";
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1483 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1484 <&cmu_peric CLK_SCLK_SPI1>,
1485 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1486 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1487 samsung,spi-src-clk = <0>;
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&spi1_bus>;
1490 num-cs = <1>;
1491 fifo-depth = <64>;
1492 status = "disabled";
1493 };
1494
1495 spi_2: spi@14d40000 {
1496 compatible = "samsung,exynos5433-spi";
1497 reg = <0x14d40000 0x100>;
1498 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1499 dmas = <&pdma0 13>, <&pdma0 12>;
1500 dma-names = "tx", "rx";
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1504 <&cmu_peric CLK_SCLK_SPI2>,
1505 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1506 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1507 samsung,spi-src-clk = <0>;
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&spi2_bus>;
1510 num-cs = <1>;
1511 fifo-depth = <64>;
1512 status = "disabled";
1513 };
1514
1515 spi_3: spi@14d50000 {
1516 compatible = "samsung,exynos5433-spi";
1517 reg = <0x14d50000 0x100>;
1518 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1519 dmas = <&pdma0 23>, <&pdma0 22>;
1520 dma-names = "tx", "rx";
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1523 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1524 <&cmu_peric CLK_SCLK_SPI3>,
1525 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1526 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1527 samsung,spi-src-clk = <0>;
1528 pinctrl-names = "default";
1529 pinctrl-0 = <&spi3_bus>;
1530 num-cs = <1>;
1531 fifo-depth = <64>;
1532 status = "disabled";
1533 };
1534
1535 spi_4: spi@14d00000 {
1536 compatible = "samsung,exynos5433-spi";
1537 reg = <0x14d00000 0x100>;
1538 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1539 dmas = <&pdma0 25>, <&pdma0 24>;
1540 dma-names = "tx", "rx";
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1544 <&cmu_peric CLK_SCLK_SPI4>,
1545 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1546 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1547 samsung,spi-src-clk = <0>;
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&spi4_bus>;
1550 num-cs = <1>;
1551 fifo-depth = <64>;
1552 status = "disabled";
1553 };
1554
1555 adc: adc@14d10000 {
1556 compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc";
1557 reg = <0x14d10000 0x100>;
1558 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1559 clock-names = "adc";
1560 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1561 #io-channel-cells = <1>;
1562 status = "disabled";
1563 };
1564
1565 i2s1: i2s@14d60000 {
1566 compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
1567 reg = <0x14d60000 0x100>;
1568 dmas = <&pdma0 31>, <&pdma0 30>;
1569 dma-names = "tx", "rx";
1570 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1571 clocks = <&cmu_peric CLK_PCLK_I2S1>,
1572 <&cmu_peric CLK_PCLK_I2S1>,
1573 <&cmu_peric CLK_SCLK_I2S1>;
1574 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1575 #clock-cells = <1>;
1576 #sound-dai-cells = <1>;
1577 status = "disabled";
1578 };
1579
1580 pwm: pwm@14dd0000 {
1581 compatible = "samsung,exynos5433-pwm", "samsung,exynos4210-pwm";
1582 reg = <0x14dd0000 0x100>;
1583 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1588 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1589 clocks = <&cmu_peric CLK_PCLK_PWM>;
1590 clock-names = "timers";
1591 #pwm-cells = <3>;
1592 status = "disabled";
1593 };
1594
1595 hsi2c_0: i2c@14e40000 {
1596 compatible = "samsung,exynos5433-hsi2c",
1597 "samsung,exynos7-hsi2c";
1598 reg = <0x14e40000 0x1000>;
1599 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 pinctrl-names = "default";
1603 pinctrl-0 = <&hs_i2c0_bus>;
1604 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1605 clock-names = "hsi2c";
1606 status = "disabled";
1607 };
1608
1609 hsi2c_1: i2c@14e50000 {
1610 compatible = "samsung,exynos5433-hsi2c",
1611 "samsung,exynos7-hsi2c";
1612 reg = <0x14e50000 0x1000>;
1613 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 pinctrl-names = "default";
1617 pinctrl-0 = <&hs_i2c1_bus>;
1618 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1619 clock-names = "hsi2c";
1620 status = "disabled";
1621 };
1622
1623 hsi2c_2: i2c@14e60000 {
1624 compatible = "samsung,exynos5433-hsi2c",
1625 "samsung,exynos7-hsi2c";
1626 reg = <0x14e60000 0x1000>;
1627 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1630 pinctrl-names = "default";
1631 pinctrl-0 = <&hs_i2c2_bus>;
1632 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1633 clock-names = "hsi2c";
1634 status = "disabled";
1635 };
1636
1637 hsi2c_3: i2c@14e70000 {
1638 compatible = "samsung,exynos5433-hsi2c",
1639 "samsung,exynos7-hsi2c";
1640 reg = <0x14e70000 0x1000>;
1641 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1644 pinctrl-names = "default";
1645 pinctrl-0 = <&hs_i2c3_bus>;
1646 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1647 clock-names = "hsi2c";
1648 status = "disabled";
1649 };
1650
1651 hsi2c_4: i2c@14ec0000 {
1652 compatible = "samsung,exynos5433-hsi2c",
1653 "samsung,exynos7-hsi2c";
1654 reg = <0x14ec0000 0x1000>;
1655 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&hs_i2c4_bus>;
1660 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1661 clock-names = "hsi2c";
1662 status = "disabled";
1663 };
1664
1665 hsi2c_5: i2c@14ed0000 {
1666 compatible = "samsung,exynos5433-hsi2c",
1667 "samsung,exynos7-hsi2c";
1668 reg = <0x14ed0000 0x1000>;
1669 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&hs_i2c5_bus>;
1674 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1675 clock-names = "hsi2c";
1676 status = "disabled";
1677 };
1678
1679 hsi2c_6: i2c@14ee0000 {
1680 compatible = "samsung,exynos5433-hsi2c",
1681 "samsung,exynos7-hsi2c";
1682 reg = <0x14ee0000 0x1000>;
1683 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&hs_i2c6_bus>;
1688 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1689 clock-names = "hsi2c";
1690 status = "disabled";
1691 };
1692
1693 hsi2c_7: i2c@14ef0000 {
1694 compatible = "samsung,exynos5433-hsi2c",
1695 "samsung,exynos7-hsi2c";
1696 reg = <0x14ef0000 0x1000>;
1697 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1700 pinctrl-names = "default";
1701 pinctrl-0 = <&hs_i2c7_bus>;
1702 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1703 clock-names = "hsi2c";
1704 status = "disabled";
1705 };
1706
1707 hsi2c_8: i2c@14d90000 {
1708 compatible = "samsung,exynos5433-hsi2c",
1709 "samsung,exynos7-hsi2c";
1710 reg = <0x14d90000 0x1000>;
1711 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1714 pinctrl-names = "default";
1715 pinctrl-0 = <&hs_i2c8_bus>;
1716 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1717 clock-names = "hsi2c";
1718 status = "disabled";
1719 };
1720
1721 hsi2c_9: i2c@14da0000 {
1722 compatible = "samsung,exynos5433-hsi2c",
1723 "samsung,exynos7-hsi2c";
1724 reg = <0x14da0000 0x1000>;
1725 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1728 pinctrl-names = "default";
1729 pinctrl-0 = <&hs_i2c9_bus>;
1730 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1731 clock-names = "hsi2c";
1732 status = "disabled";
1733 };
1734
1735 hsi2c_10: i2c@14de0000 {
1736 compatible = "samsung,exynos5433-hsi2c",
1737 "samsung,exynos7-hsi2c";
1738 reg = <0x14de0000 0x1000>;
1739 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1742 pinctrl-names = "default";
1743 pinctrl-0 = <&hs_i2c10_bus>;
1744 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1745 clock-names = "hsi2c";
1746 status = "disabled";
1747 };
1748
1749 hsi2c_11: i2c@14df0000 {
1750 compatible = "samsung,exynos5433-hsi2c",
1751 "samsung,exynos7-hsi2c";
1752 reg = <0x14df0000 0x1000>;
1753 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1756 pinctrl-names = "default";
1757 pinctrl-0 = <&hs_i2c11_bus>;
1758 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1759 clock-names = "hsi2c";
1760 status = "disabled";
1761 };
1762
1763 usbdrd30: usb@15400000 {
1764 compatible = "samsung,exynos5433-dwusb3";
1765 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1766 <&cmu_fsys CLK_SCLK_USBDRD30>,
1767 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1768 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1769 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1770 #address-cells = <1>;
1771 #size-cells = <1>;
1772 ranges = <0x0 0x15400000 0x10000>;
1773 status = "disabled";
1774
1775 usbdrd_dwc3: usb@0 {
1776 compatible = "snps,dwc3";
1777 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1778 <&cmu_fsys CLK_ACLK_USBDRD30>,
1779 <&cmu_fsys CLK_SCLK_USBDRD30>;
1780 clock-names = "ref", "bus_early", "suspend";
1781 reg = <0x0 0x10000>;
1782 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1783 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1784 phy-names = "usb2-phy", "usb3-phy";
1785 };
1786 };
1787
1788 usbdrd30_phy: phy@15500000 {
1789 compatible = "samsung,exynos5433-usbdrd-phy";
1790 reg = <0x15500000 0x100>;
1791 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1792 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1793 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1794 <&cmu_fsys CLK_SCLK_USBDRD30>;
1795 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1796 "itp";
1797 #phy-cells = <1>;
1798 samsung,pmu-syscon = <&pmu_system_controller>;
1799 status = "disabled";
1800 };
1801
1802 usbhost30_phy: phy@15580000 {
1803 compatible = "samsung,exynos5433-usbdrd-phy";
1804 reg = <0x15580000 0x100>;
1805 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1806 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1807 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1808 <&cmu_fsys CLK_SCLK_USBHOST30>;
1809 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1810 "itp";
1811 #phy-cells = <1>;
1812 samsung,pmu-syscon = <&pmu_system_controller>;
1813 status = "disabled";
1814 };
1815
1816 usbhost30: usb@15a00000 {
1817 compatible = "samsung,exynos5433-dwusb3";
1818 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1819 <&cmu_fsys CLK_SCLK_USBHOST30>,
1820 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1821 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1822 clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1823 #address-cells = <1>;
1824 #size-cells = <1>;
1825 ranges = <0x0 0x15a00000 0x10000>;
1826 status = "disabled";
1827
1828 usbhost_dwc3: usb@0 {
1829 compatible = "snps,dwc3";
1830 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1831 <&cmu_fsys CLK_ACLK_USBHOST30>,
1832 <&cmu_fsys CLK_SCLK_USBHOST30>;
1833 clock-names = "ref", "bus_early", "suspend";
1834 reg = <0x0 0x10000>;
1835 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1836 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1837 phy-names = "usb2-phy", "usb3-phy";
1838 };
1839 };
1840
1841 mshc_0: mmc@15540000 {
1842 compatible = "samsung,exynos5433-dw-mshc-smu",
1843 "samsung,exynos7-dw-mshc-smu";
1844 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1845 #address-cells = <1>;
1846 #size-cells = <0>;
1847 reg = <0x15540000 0x2000>;
1848 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1849 <&cmu_fsys CLK_SCLK_MMC0>;
1850 clock-names = "biu", "ciu";
1851 fifo-depth = <0x40>;
1852 status = "disabled";
1853 };
1854
1855 mshc_1: mmc@15550000 {
1856 compatible = "samsung,exynos5433-dw-mshc-smu",
1857 "samsung,exynos7-dw-mshc-smu";
1858 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1861 reg = <0x15550000 0x2000>;
1862 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1863 <&cmu_fsys CLK_SCLK_MMC1>;
1864 clock-names = "biu", "ciu";
1865 fifo-depth = <0x40>;
1866 status = "disabled";
1867 };
1868
1869 mshc_2: mmc@15560000 {
1870 compatible = "samsung,exynos5433-dw-mshc-smu",
1871 "samsung,exynos7-dw-mshc-smu";
1872 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1875 reg = <0x15560000 0x2000>;
1876 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1877 <&cmu_fsys CLK_SCLK_MMC2>;
1878 clock-names = "biu", "ciu";
1879 fifo-depth = <0x40>;
1880 status = "disabled";
1881 };
1882
1883 pdma0: dma-controller@15610000 {
1884 compatible = "arm,pl330", "arm,primecell";
1885 reg = <0x15610000 0x1000>;
1886 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1887 clocks = <&cmu_fsys CLK_PDMA0>;
1888 clock-names = "apb_pclk";
1889 #dma-cells = <1>;
1890 };
1891
1892 pdma1: dma-controller@15600000 {
1893 compatible = "arm,pl330", "arm,primecell";
1894 reg = <0x15600000 0x1000>;
1895 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1896 clocks = <&cmu_fsys CLK_PDMA1>;
1897 clock-names = "apb_pclk";
1898 #dma-cells = <1>;
1899 };
1900
1901 audio-subsystem@11400000 {
1902 compatible = "samsung,exynos5433-lpass";
1903 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1904 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1905 clock-names = "sfr0_ctrl";
1906 power-domains = <&pd_aud>;
1907 #address-cells = <1>;
1908 #size-cells = <1>;
1909 ranges;
1910
1911 adma: dma-controller@11420000 {
1912 compatible = "arm,pl330", "arm,primecell";
1913 reg = <0x11420000 0x1000>;
1914 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1915 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1916 clock-names = "apb_pclk";
1917 #dma-cells = <1>;
1918 power-domains = <&pd_aud>;
1919 };
1920
1921 i2s0: i2s@11440000 {
1922 compatible = "samsung,exynos5433-i2s",
1923 "samsung,exynos7-i2s";
1924 reg = <0x11440000 0x100>;
1925 dmas = <&adma 0>, <&adma 2>;
1926 dma-names = "tx", "rx";
1927 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1928 #address-cells = <1>;
1929 #size-cells = <0>;
1930 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1931 <&cmu_aud CLK_SCLK_AUD_I2S>,
1932 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1933 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1934 #clock-cells = <1>;
1935 pinctrl-names = "default";
1936 pinctrl-0 = <&i2s0_bus>;
1937 power-domains = <&pd_aud>;
1938 #sound-dai-cells = <1>;
1939 status = "disabled";
1940 };
1941
1942 serial_3: serial@11460000 {
1943 compatible = "samsung,exynos5433-uart";
1944 reg = <0x11460000 0x100>;
1945 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1946 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1947 <&cmu_aud CLK_SCLK_AUD_UART>;
1948 clock-names = "uart", "clk_uart_baud0";
1949 pinctrl-names = "default";
1950 pinctrl-0 = <&uart_aud_bus>;
1951 power-domains = <&pd_aud>;
1952 status = "disabled";
1953 };
1954 };
1955
1956 pcie_phy: pcie-phy@15680000 {
1957 compatible = "samsung,exynos5433-pcie-phy";
1958 reg = <0x15680000 0x1000>;
1959 samsung,pmu-syscon = <&pmu_system_controller>;
1960 samsung,fsys-sysreg = <&syscon_fsys>;
1961 #phy-cells = <0>;
1962 status = "disabled";
1963 };
1964
1965 pcie: pcie@15700000 {
1966 compatible = "samsung,exynos5433-pcie";
1967 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1968 <0x0c000000 0x1000>;
1969 reg-names = "dbi", "elbi", "config";
1970 #address-cells = <3>;
1971 #size-cells = <2>;
1972 #interrupt-cells = <1>;
1973 device_type = "pci";
1974 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&cmu_fsys CLK_PCIE>,
1976 <&cmu_fsys CLK_PCLK_PCIE_PHY>;
1977 clock-names = "pcie", "pcie_bus";
1978 num-lanes = <1>;
1979 num-viewport = <3>;
1980 bus-range = <0x00 0xff>;
1981 phys = <&pcie_phy>;
1982 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1983 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
1984 status = "disabled";
1985 };
1986 };
1987
1988 timer: timer {
1989 compatible = "arm,armv8-timer";
1990 interrupts = <GIC_PPI 13
1991 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1992 <GIC_PPI 14
1993 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1994 <GIC_PPI 11
1995 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1996 <GIC_PPI 10
1997 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1998 };
1999 };
2000
2001 #include "exynos5433-bus.dtsi"
2002 #include "exynos5433-pinctrl.dtsi"
2003 #include "exynos5433-tmu.dtsi"
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