1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 *
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
13
14 / {
15 model = "LS1043A QDS Board";
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
17
18 aliases {
19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 serial0 = &duart0;
24 serial1 = &duart1;
25 serial2 = &duart2;
26 serial3 = &duart3;
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
30 sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
31 qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
32 qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
33 qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
34 qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
35 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
36 qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
37 qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
38 qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
39 emi1-slot1 = &ls1043mdio_s1;
40 emi1-slot2 = &ls1043mdio_s2;
41 emi1-slot3 = &ls1043mdio_s3;
42 emi1-slot4 = &ls1043mdio_s4;
43 };
44
45 chosen {
46 stdout-path = "serial0:115200n8";
47 };
48 };
49
50 &duart0 {
51 status = "okay";
52 };
53
54 &duart1 {
55 status = "okay";
56 };
57
58 &ifc {
59 #address-cells = <2>;
60 #size-cells = <1>;
61 /* NOR, NAND Flashes and FPGA on board */
62 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
63 0x1 0x0 0x0 0x7e800000 0x00010000
64 0x2 0x0 0x0 0x7fb00000 0x00000100>;
65 status = "okay";
66
67 flash@0,0 {
68 compatible = "cfi-flash";
69 reg = <0x0 0x0 0x8000000>;
70 big-endian;
71 bank-width = <2>;
72 device-width = <1>;
73 };
74
75 nand@1,0 {
76 compatible = "fsl,ifc-nand";
77 reg = <0x1 0x0 0x10000>;
78 };
79
80 fpga: board-control@2,0 {
81 compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
82 reg = <0x2 0x0 0x0000100>;
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges = <0 2 0 0x100>;
86 };
87 };
88
89 &i2c0 {
90 status = "okay";
91
92 i2c-mux@77 {
93 compatible = "nxp,pca9547";
94 reg = <0x77>;
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 i2c@0 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0x0>;
102
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 /* IRQ10_B */
107 interrupts = <0 150 0x4>;
108 };
109 };
110
111 i2c@2 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x2>;
115
116 ina220@40 {
117 compatible = "ti,ina220";
118 reg = <0x40>;
119 shunt-resistor = <1000>;
120 };
121
122 ina220@41 {
123 compatible = "ti,ina220";
124 reg = <0x41>;
125 shunt-resistor = <1000>;
126 };
127 };
128
129 i2c@3 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x3>;
133
134 eeprom@56 {
135 compatible = "atmel,24c512";
136 reg = <0x56>;
137 };
138
139 eeprom@57 {
140 compatible = "atmel,24c512";
141 reg = <0x57>;
142 };
143
144 temp-sensor@4c {
145 compatible = "adi,adt7461a";
146 reg = <0x4c>;
147 };
148 };
149 };
150 };
151
152 &lpuart0 {
153 status = "okay";
154 };
155
156 &qspi {
157 status = "okay";
158
159 qflash0: flash@0 {
160 compatible = "spansion,m25p80";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 spi-max-frequency = <20000000>;
164 spi-rx-bus-width = <4>;
165 spi-tx-bus-width = <4>;
166 reg = <0>;
167 };
168 };
169
170 &usb0 {
171 status = "okay";
172 };
173
174 #include "fsl-ls1043-post.dtsi"
175
176 &fman0 {
177 ethernet@e0000 {
178 phy-handle = <&qsgmii_phy_s2_p1>;
179 phy-connection-type = "sgmii";
180 };
181
182 ethernet@e2000 {
183 phy-handle = <&qsgmii_phy_s2_p2>;
184 phy-connection-type = "sgmii";
185 };
186
187 ethernet@e4000 {
188 phy-handle = <&rgmii_phy1>;
189 phy-connection-type = "rgmii";
190 };
191
192 ethernet@e6000 {
193 phy-handle = <&rgmii_phy2>;
194 phy-connection-type = "rgmii";
195 };
196
197 ethernet@e8000 {
198 phy-handle = <&qsgmii_phy_s2_p3>;
199 phy-connection-type = "sgmii";
200 };
201
202 ethernet@ea000 {
203 phy-handle = <&qsgmii_phy_s2_p4>;
204 phy-connection-type = "sgmii";
205 };
206
207 ethernet@f0000 { /* DTSEC9/10GEC1 */
208 fixed-link = <1 1 10000 0 0>;
209 phy-connection-type = "xgmii";
210 };
211 };
212
213 &fpga {
214 mdio-mux@54 {
215 compatible = "mdio-mux-mmioreg", "mdio-mux";
216 mdio-parent-bus = <&mdio0>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <0x54 1>; /* BRDCFG4 */
220 mux-mask = <0xe0>; /* EMI1 */
221
222 /* On-board RGMII1 PHY */
223 ls1043mdio0: mdio@0 {
224 reg = <0>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 rgmii_phy1: ethernet-phy@1 { /* MAC3 */
229 reg = <0x1>;
230 };
231 };
232
233 /* On-board RGMII2 PHY */
234 ls1043mdio1: mdio@20 {
235 reg = <0x20>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238
239 rgmii_phy2: ethernet-phy@2 { /* MAC4 */
240 reg = <0x2>;
241 };
242 };
243
244 /* Slot 1 */
245 ls1043mdio_s1: mdio@40 {
246 reg = <0x40>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 status = "disabled";
250
251 qsgmii_phy_s1_p1: ethernet-phy@4 {
252 reg = <0x4>;
253 };
254
255 qsgmii_phy_s1_p2: ethernet-phy@5 {
256 reg = <0x5>;
257 };
258
259 qsgmii_phy_s1_p3: ethernet-phy@6 {
260 reg = <0x6>;
261 };
262
263 qsgmii_phy_s1_p4: ethernet-phy@7 {
264 reg = <0x7>;
265 };
266
267 sgmii_phy_s1_p1: ethernet-phy@1c {
268 reg = <0x1c>;
269 };
270 };
271
272 /* Slot 2 */
273 ls1043mdio_s2: mdio@60 {
274 reg = <0x60>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277 status = "disabled";
278
279 qsgmii_phy_s2_p1: ethernet-phy@8 {
280 reg = <0x8>;
281 };
282
283 qsgmii_phy_s2_p2: ethernet-phy@9 {
284 reg = <0x9>;
285 };
286
287 qsgmii_phy_s2_p3: ethernet-phy@a {
288 reg = <0xa>;
289 };
290
291 qsgmii_phy_s2_p4: ethernet-phy@b {
292 reg = <0xb>;
293 };
294
295 sgmii_phy_s2_p1: ethernet-phy@1c {
296 reg = <0x1c>;
297 };
298 };
299
300 /* Slot 3 */
301 ls1043mdio_s3: mdio@80 {
302 reg = <0x80>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 status = "disabled";
306
307 sgmii_phy_s3_p1: ethernet-phy@1c {
308 reg = <0x1c>;
309 };
310 };
311
312 /* Slot 4 */
313 ls1043mdio_s4: mdio@a0 {
314 reg = <0xa0>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318
319 sgmii_phy_s4_p1: ethernet-phy@1c {
320 reg = <0x1c>;
321 };
322 };
323 };
324 };
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