1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree file for NXP LS1088A QDS Board.
4 *
5 * Copyright 2017 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11 /dts-v1/;
12
13 #include "fsl-ls1088a.dtsi"
14
15 / {
16 model = "LS1088A QDS Board";
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
18 };
19
20 &dspi {
21 bus-num = <0>;
22 status = "okay";
23
24 flash@0 {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
28 reg = <0>;
29 spi-max-frequency = <1000000>;
30 };
31
32 flash@1 {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "jedec,spi-nor";
36 spi-cpol;
37 spi-cpha;
38 spi-max-frequency = <3500000>;
39 reg = <1>;
40 };
41
42 flash@2 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "jedec,spi-nor";
46 spi-cpol;
47 spi-cpha;
48 spi-max-frequency = <3500000>;
49 reg = <2>;
50 };
51 };
52
53 &i2c0 {
54 status = "okay";
55
56 i2c-mux@77 {
57 compatible = "nxp,pca9547";
58 reg = <0x77>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 i2c@2 {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 reg = <0x2>;
66
67 ina220@40 {
68 compatible = "ti,ina220";
69 reg = <0x40>;
70 shunt-resistor = <1000>;
71 };
72
73 ina220@41 {
74 compatible = "ti,ina220";
75 reg = <0x41>;
76 shunt-resistor = <1000>;
77 };
78 };
79
80 i2c@3 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 reg = <0x3>;
84
85 temp-sensor@4c {
86 compatible = "adi,adt7461a";
87 reg = <0x4c>;
88 };
89
90 rtc@51 {
91 compatible = "nxp,pcf2129";
92 reg = <0x51>;
93 /* IRQ10_B */
94 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
95 };
96
97 eeprom@56 {
98 compatible = "atmel,24c512";
99 reg = <0x56>;
100 };
101
102 eeprom@57 {
103 compatible = "atmel,24c512";
104 reg = <0x57>;
105 };
106 };
107 };
108 };
109
110 &ifc {
111 ranges = <0 0 0x5 0x80000000 0x08000000
112 2 0 0x5 0x30000000 0x00010000
113 3 0 0x5 0x20000000 0x00010000>;
114 status = "okay";
115
116 flash@0,0 {
117 compatible = "cfi-flash";
118 reg = <0x0 0x0 0x8000000>;
119 bank-width = <2>;
120 device-width = <1>;
121 };
122
123 nand@2,0 {
124 compatible = "fsl,ifc-nand";
125 reg = <0x2 0x0 0x10000>;
126 };
127
128 fpga: board-control@3,0 {
129 compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
130 reg = <0x3 0x0 0x0000100>;
131 };
132 };
133
134 &duart0 {
135 status = "okay";
136 };
137
138 &duart1 {
139 status = "okay";
140 };
141
142 &esdhc {
143 status = "okay";
144 };
145
146 &qspi {
147 status = "okay";
148
149 s25fs512s0: flash@0 {
150 compatible = "jedec,spi-nor";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 spi-max-frequency = <50000000>;
154 spi-rx-bus-width = <4>;
155 spi-tx-bus-width = <1>;
156 reg = <0>;
157 };
158
159 s25fs512s1: flash@1 {
160 compatible = "jedec,spi-nor";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 spi-max-frequency = <50000000>;
164 spi-rx-bus-width = <4>;
165 spi-tx-bus-width = <1>;
166 reg = <1>;
167 };
168 };
169
170 &sata {
171 status = "okay";
172 };
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