1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 *
5 * Copyright 2017-2020 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 crypto = &crypto;
22 rtc1 = &ftm_alarm0;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 /* We have 2 clusters having 4 Cortex-A53 cores each */
30 cpu0: cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a53";
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 cpu-idle-states = <&CPU_PH20>;
36 #cooling-cells = <2>;
37 };
38
39 cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
44 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>;
46 };
47
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a53";
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 cpu-idle-states = <&CPU_PH20>;
54 #cooling-cells = <2>;
55 };
56
57 cpu3: cpu@3 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a53";
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 cpu-idle-states = <&CPU_PH20>;
63 #cooling-cells = <2>;
64 };
65
66 cpu4: cpu@100 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a53";
69 reg = <0x100>;
70 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>;
73 };
74
75 cpu5: cpu@101 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53";
78 reg = <0x101>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
80 cpu-idle-states = <&CPU_PH20>;
81 #cooling-cells = <2>;
82 };
83
84 cpu6: cpu@102 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a53";
87 reg = <0x102>;
88 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
89 cpu-idle-states = <&CPU_PH20>;
90 #cooling-cells = <2>;
91 };
92
93 cpu7: cpu@103 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a53";
96 reg = <0x103>;
97 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
98 cpu-idle-states = <&CPU_PH20>;
99 #cooling-cells = <2>;
100 };
101
102 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle-state";
104 idle-state-name = "PH20";
105 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <1000>;
107 exit-latency-us = <1000>;
108 min-residency-us = <3000>;
109 };
110 };
111
112 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
125
126 its: msi-controller@6020000 {
127 compatible = "arm,gic-v3-its";
128 msi-controller;
129 reg = <0x0 0x6020000 0 0x20000>;
130 };
131 };
132
133 thermal-zones {
134 core-cluster-thermal {
135 polling-delay-passive = <1000>;
136 polling-delay = <5000>;
137 thermal-sensors = <&tmu 0>;
138
139 trips {
140 core_cluster_alert: core-cluster-alert {
141 temperature = <85000>;
142 hysteresis = <2000>;
143 type = "passive";
144 };
145
146 core-cluster-crit {
147 temperature = <95000>;
148 hysteresis = <2000>;
149 type = "critical";
150 };
151 };
152
153 cooling-maps {
154 map0 {
155 trip = <&core_cluster_alert>;
156 cooling-device =
157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
165 };
166 };
167 };
168
169 soc-thermal {
170 polling-delay-passive = <1000>;
171 polling-delay = <5000>;
172 thermal-sensors = <&tmu 1>;
173
174 trips {
175 soc-crit {
176 temperature = <95000>;
177 hysteresis = <2000>;
178 type = "critical";
179 };
180 };
181 };
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
190 };
191
192 pmu {
193 compatible = "arm,cortex-a53-pmu";
194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
195 };
196
197 psci {
198 compatible = "arm,psci-0.2";
199 method = "smc";
200 };
201
202 sysclk: sysclk {
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <100000000>;
206 clock-output-names = "sysclk";
207 };
208
209 reboot {
210 compatible = "syscon-reboot";
211 regmap = <&reset>;
212 offset = <0x0>;
213 mask = <0x02>;
214 };
215
216 soc {
217 compatible = "simple-bus";
218 #address-cells = <2>;
219 #size-cells = <2>;
220 ranges;
221 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
222
223 clockgen: clocking@1300000 {
224 compatible = "fsl,ls1088a-clockgen";
225 reg = <0 0x1300000 0 0xa0000>;
226 #clock-cells = <2>;
227 clocks = <&sysclk>;
228 };
229
230 dcfg: dcfg@1e00000 {
231 compatible = "fsl,ls1088a-dcfg", "syscon";
232 reg = <0x0 0x1e00000 0x0 0x10000>;
233 little-endian;
234 };
235
236 reset: syscon@1e60000 {
237 compatible = "fsl,ls1088a-reset", "syscon";
238 reg = <0x0 0x1e60000 0x0 0x10000>;
239 };
240
241 isc: syscon@1f70000 {
242 compatible = "fsl,ls1088a-isc", "syscon";
243 reg = <0x0 0x1f70000 0x0 0x10000>;
244 little-endian;
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x1f70000 0x10000>;
248
249 extirq: interrupt-controller@14 {
250 compatible = "fsl,ls1088a-extirq";
251 #interrupt-cells = <2>;
252 #address-cells = <0>;
253 interrupt-controller;
254 reg = <0x14 4>;
255 interrupt-map =
256 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
257 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
258 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
259 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
260 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
261 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
262 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
263 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
264 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
265 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
266 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
267 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-map-mask = <0xf 0x0>;
269 };
270 };
271
272 sfp: efuse@1e80000 {
273 compatible = "fsl,ls1028a-sfp";
274 reg = <0x0 0x1e80000 0x0 0x10000>;
275 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
276 QORIQ_CLK_PLL_DIV(4)>;
277 clock-names = "sfp";
278 };
279
280 tmu: tmu@1f80000 {
281 compatible = "fsl,qoriq-tmu";
282 reg = <0x0 0x1f80000 0x0 0x10000>;
283 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
285 fsl,tmu-calibration =
286 /* Calibration data group 1 */
287 <0x00000000 0x00000023>,
288 <0x00000001 0x0000002a>,
289 <0x00000002 0x00000030>,
290 <0x00000003 0x00000037>,
291 <0x00000004 0x0000003d>,
292 <0x00000005 0x00000044>,
293 <0x00000006 0x0000004a>,
294 <0x00000007 0x00000051>,
295 <0x00000008 0x00000057>,
296 <0x00000009 0x0000005e>,
297 <0x0000000a 0x00000064>,
298 <0x0000000b 0x0000006b>,
299 /* Calibration data group 2 */
300 <0x00010000 0x00000022>,
301 <0x00010001 0x0000002a>,
302 <0x00010002 0x00000032>,
303 <0x00010003 0x0000003a>,
304 <0x00010004 0x00000042>,
305 <0x00010005 0x0000004a>,
306 <0x00010006 0x00000052>,
307 <0x00010007 0x0000005a>,
308 <0x00010008 0x00000062>,
309 <0x00010009 0x0000006a>,
310 /* Calibration data group 3 */
311 <0x00020000 0x00000021>,
312 <0x00020001 0x0000002b>,
313 <0x00020002 0x00000035>,
314 <0x00020003 0x00000040>,
315 <0x00020004 0x0000004a>,
316 <0x00020005 0x00000054>,
317 <0x00020006 0x0000005e>,
318 /* Calibration data group 4 */
319 <0x00030000 0x00000010>,
320 <0x00030001 0x0000001c>,
321 <0x00030002 0x00000027>,
322 <0x00030003 0x00000032>,
323 <0x00030004 0x0000003e>,
324 <0x00030005 0x00000049>,
325 <0x00030006 0x00000054>,
326 <0x00030007 0x00000060>;
327 little-endian;
328 #thermal-sensor-cells = <1>;
329 };
330
331 dspi: spi@2100000 {
332 compatible = "fsl,ls1088a-dspi",
333 "fsl,ls1021a-v1.0-dspi";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0x0 0x2100000 0x0 0x10000>;
337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "dspi";
339 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
340 QORIQ_CLK_PLL_DIV(2)>;
341 spi-num-chipselects = <6>;
342 status = "disabled";
343 };
344
345 duart0: serial@21c0500 {
346 compatible = "fsl,ns16550", "ns16550a";
347 reg = <0x0 0x21c0500 0x0 0x100>;
348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
349 QORIQ_CLK_PLL_DIV(4)>;
350 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
351 status = "disabled";
352 };
353
354 duart1: serial@21c0600 {
355 compatible = "fsl,ns16550", "ns16550a";
356 reg = <0x0 0x21c0600 0x0 0x100>;
357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
358 QORIQ_CLK_PLL_DIV(4)>;
359 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
360 status = "disabled";
361 };
362
363 gpio0: gpio@2300000 {
364 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
365 reg = <0x0 0x2300000 0x0 0x10000>;
366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
367 little-endian;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
373
374 gpio1: gpio@2310000 {
375 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
376 reg = <0x0 0x2310000 0x0 0x10000>;
377 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
378 little-endian;
379 gpio-controller;
380 #gpio-cells = <2>;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 gpio2: gpio@2320000 {
386 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
387 reg = <0x0 0x2320000 0x0 0x10000>;
388 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
389 little-endian;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 gpio3: gpio@2330000 {
397 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
398 reg = <0x0 0x2330000 0x0 0x10000>;
399 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
400 little-endian;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406
407 ifc: memory-controller@2240000 {
408 compatible = "fsl,ifc";
409 reg = <0x0 0x2240000 0x0 0x20000>;
410 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
411 little-endian;
412 #address-cells = <2>;
413 #size-cells = <1>;
414 status = "disabled";
415 };
416
417 i2c0: i2c@2000000 {
418 compatible = "fsl,vf610-i2c";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <0x0 0x2000000 0x0 0x10000>;
422 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
424 QORIQ_CLK_PLL_DIV(8)>;
425 status = "disabled";
426 };
427
428 i2c1: i2c@2010000 {
429 compatible = "fsl,vf610-i2c";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <0x0 0x2010000 0x0 0x10000>;
433 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
435 QORIQ_CLK_PLL_DIV(8)>;
436 status = "disabled";
437 };
438
439 i2c2: i2c@2020000 {
440 compatible = "fsl,vf610-i2c";
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <0x0 0x2020000 0x0 0x10000>;
444 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
446 QORIQ_CLK_PLL_DIV(8)>;
447 status = "disabled";
448 };
449
450 i2c3: i2c@2030000 {
451 compatible = "fsl,vf610-i2c";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x0 0x2030000 0x0 0x10000>;
455 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
457 QORIQ_CLK_PLL_DIV(8)>;
458 status = "disabled";
459 };
460
461 qspi: spi@20c0000 {
462 compatible = "fsl,ls2080a-qspi";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg = <0x0 0x20c0000 0x0 0x10000>,
466 <0x0 0x20000000 0x0 0x10000000>;
467 reg-names = "QuadSPI", "QuadSPI-memory";
468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 clock-names = "qspi_en", "qspi";
470 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
471 QORIQ_CLK_PLL_DIV(4)>,
472 <&clockgen QORIQ_CLK_PLATFORM_PLL
473 QORIQ_CLK_PLL_DIV(4)>;
474 status = "disabled";
475 };
476
477 esdhc: mmc@2140000 {
478 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
479 reg = <0x0 0x2140000 0x0 0x10000>;
480 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
481 clock-frequency = <0>;
482 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
483 voltage-ranges = <1800 1800 3300 3300>;
484 sdhci,auto-cmd12;
485 little-endian;
486 bus-width = <4>;
487 status = "disabled";
488 };
489
490 usb0: usb@3100000 {
491 compatible = "snps,dwc3";
492 reg = <0x0 0x3100000 0x0 0x10000>;
493 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
494 dr_mode = "host";
495 snps,quirk-frame-length-adjustment = <0x20>;
496 snps,dis_rxdet_inp3_quirk;
497 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
498 status = "disabled";
499 };
500
501 usb1: usb@3110000 {
502 compatible = "snps,dwc3";
503 reg = <0x0 0x3110000 0x0 0x10000>;
504 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
505 dr_mode = "host";
506 snps,quirk-frame-length-adjustment = <0x20>;
507 snps,dis_rxdet_inp3_quirk;
508 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
509 status = "disabled";
510 };
511
512 sata: sata@3200000 {
513 compatible = "fsl,ls1088a-ahci";
514 reg = <0x0 0x3200000 0x0 0x10000>,
515 <0x7 0x100520 0x0 0x4>;
516 reg-names = "ahci", "sata-ecc";
517 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
519 QORIQ_CLK_PLL_DIV(4)>;
520 dma-coherent;
521 status = "disabled";
522 };
523
524 crypto: crypto@8000000 {
525 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
526 fsl,sec-era = <8>;
527 #address-cells = <1>;
528 #size-cells = <1>;
529 ranges = <0x0 0x00 0x8000000 0x100000>;
530 reg = <0x00 0x8000000 0x0 0x100000>;
531 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
532 dma-coherent;
533
534 sec_jr0: jr@10000 {
535 compatible = "fsl,sec-v5.0-job-ring",
536 "fsl,sec-v4.0-job-ring";
537 reg = <0x10000 0x10000>;
538 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
539 };
540
541 sec_jr1: jr@20000 {
542 compatible = "fsl,sec-v5.0-job-ring",
543 "fsl,sec-v4.0-job-ring";
544 reg = <0x20000 0x10000>;
545 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
546 };
547
548 sec_jr2: jr@30000 {
549 compatible = "fsl,sec-v5.0-job-ring",
550 "fsl,sec-v4.0-job-ring";
551 reg = <0x30000 0x10000>;
552 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
553 };
554
555 sec_jr3: jr@40000 {
556 compatible = "fsl,sec-v5.0-job-ring",
557 "fsl,sec-v4.0-job-ring";
558 reg = <0x40000 0x10000>;
559 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
560 };
561 };
562
563 pcie1: pcie@3400000 {
564 compatible = "fsl,ls1088a-pcie";
565 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
566 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
567 reg-names = "regs", "config";
568 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
569 interrupt-names = "aer";
570 #address-cells = <3>;
571 #size-cells = <2>;
572 device_type = "pci";
573 dma-coherent;
574 num-viewport = <256>;
575 bus-range = <0x0 0xff>;
576 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
577 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
578 msi-parent = <&its>;
579 #interrupt-cells = <1>;
580 interrupt-map-mask = <0 0 0 7>;
581 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
582 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
585 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
586 status = "disabled";
587 };
588
589 pcie_ep1: pcie-ep@3400000 {
590 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
591 reg = <0x00 0x03400000 0x0 0x00100000>,
592 <0x20 0x00000000 0x8 0x00000000>;
593 reg-names = "regs", "addr_space";
594 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
595 interrupt-names = "pme";
596 num-ib-windows = <24>;
597 num-ob-windows = <256>;
598 max-functions = /bits/ 8 <2>;
599 status = "disabled";
600 };
601
602 pcie2: pcie@3500000 {
603 compatible = "fsl,ls1088a-pcie";
604 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
605 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
606 reg-names = "regs", "config";
607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
608 interrupt-names = "aer";
609 #address-cells = <3>;
610 #size-cells = <2>;
611 device_type = "pci";
612 dma-coherent;
613 num-viewport = <6>;
614 bus-range = <0x0 0xff>;
615 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
616 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
617 msi-parent = <&its>;
618 #interrupt-cells = <1>;
619 interrupt-map-mask = <0 0 0 7>;
620 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
621 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
624 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
625 status = "disabled";
626 };
627
628 pcie_ep2: pcie-ep@3500000 {
629 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
630 reg = <0x00 0x03500000 0x0 0x00100000>,
631 <0x28 0x00000000 0x8 0x00000000>;
632 reg-names = "regs", "addr_space";
633 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
634 interrupt-names = "pme";
635 num-ib-windows = <6>;
636 num-ob-windows = <6>;
637 status = "disabled";
638 };
639
640 pcie3: pcie@3600000 {
641 compatible = "fsl,ls1088a-pcie";
642 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
643 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
644 reg-names = "regs", "config";
645 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
646 interrupt-names = "aer";
647 #address-cells = <3>;
648 #size-cells = <2>;
649 device_type = "pci";
650 dma-coherent;
651 num-viewport = <6>;
652 bus-range = <0x0 0xff>;
653 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
654 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
655 msi-parent = <&its>;
656 #interrupt-cells = <1>;
657 interrupt-map-mask = <0 0 0 7>;
658 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
659 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
662 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
663 status = "disabled";
664 };
665
666 pcie_ep3: pcie-ep@3600000 {
667 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
668 reg = <0x00 0x03600000 0x0 0x00100000>,
669 <0x30 0x00000000 0x8 0x00000000>;
670 reg-names = "regs", "addr_space";
671 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
672 interrupt-names = "pme";
673 num-ib-windows = <6>;
674 num-ob-windows = <6>;
675 status = "disabled";
676 };
677
678 smmu: iommu@5000000 {
679 compatible = "arm,mmu-500";
680 reg = <0 0x5000000 0 0x800000>;
681 #iommu-cells = <1>;
682 stream-match-mask = <0x7C00>;
683 dma-coherent;
684 #global-interrupts = <12>;
685 // global secure fault
686 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
687 // combined secure
688 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
689 // global non-secure fault
690 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
691 // combined non-secure
692 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
693 // performance counter interrupts 0-7
694 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
702 // per context interrupt, 64 interrupts
703 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
767 };
768
769 console@8340020 {
770 compatible = "fsl,dpaa2-console";
771 reg = <0x00000000 0x08340020 0 0x2>;
772 };
773
774 ptp-timer@8b95000 {
775 compatible = "fsl,dpaa2-ptp";
776 reg = <0x0 0x8b95000 0x0 0x100>;
777 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
778 QORIQ_CLK_PLL_DIV(1)>;
779 little-endian;
780 fsl,extts-fifo;
781 };
782
783 emdio1: mdio@8b96000 {
784 compatible = "fsl,fman-memac-mdio";
785 reg = <0x0 0x8b96000 0x0 0x1000>;
786 little-endian;
787 #address-cells = <1>;
788 #size-cells = <0>;
789 clock-frequency = <2500000>;
790 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
791 QORIQ_CLK_PLL_DIV(1)>;
792 status = "disabled";
793 };
794
795 emdio2: mdio@8b97000 {
796 compatible = "fsl,fman-memac-mdio";
797 reg = <0x0 0x8b97000 0x0 0x1000>;
798 little-endian;
799 #address-cells = <1>;
800 #size-cells = <0>;
801 clock-frequency = <2500000>;
802 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
803 QORIQ_CLK_PLL_DIV(1)>;
804 status = "disabled";
805 };
806
807 pcs_mdio1: mdio@8c07000 {
808 compatible = "fsl,fman-memac-mdio";
809 reg = <0x0 0x8c07000 0x0 0x1000>;
810 little-endian;
811 #address-cells = <1>;
812 #size-cells = <0>;
813 status = "disabled";
814
815 pcs1: ethernet-phy@0 {
816 reg = <0>;
817 };
818 };
819
820 pcs_mdio2: mdio@8c0b000 {
821 compatible = "fsl,fman-memac-mdio";
822 reg = <0x0 0x8c0b000 0x0 0x1000>;
823 little-endian;
824 #address-cells = <1>;
825 #size-cells = <0>;
826 status = "disabled";
827
828 pcs2: ethernet-phy@0 {
829 reg = <0>;
830 };
831 };
832
833 pcs_mdio3: mdio@8c0f000 {
834 compatible = "fsl,fman-memac-mdio";
835 reg = <0x0 0x8c0f000 0x0 0x1000>;
836 little-endian;
837 #address-cells = <1>;
838 #size-cells = <0>;
839 status = "disabled";
840
841 pcs3_0: ethernet-phy@0 {
842 reg = <0>;
843 };
844
845 pcs3_1: ethernet-phy@1 {
846 reg = <1>;
847 };
848
849 pcs3_2: ethernet-phy@2 {
850 reg = <2>;
851 };
852
853 pcs3_3: ethernet-phy@3 {
854 reg = <3>;
855 };
856 };
857
858 pcs_mdio7: mdio@8c1f000 {
859 compatible = "fsl,fman-memac-mdio";
860 reg = <0x0 0x8c1f000 0x0 0x1000>;
861 little-endian;
862 #address-cells = <1>;
863 #size-cells = <0>;
864 status = "disabled";
865
866 pcs7_0: ethernet-phy@0 {
867 reg = <0>;
868 };
869
870 pcs7_1: ethernet-phy@1 {
871 reg = <1>;
872 };
873
874 pcs7_2: ethernet-phy@2 {
875 reg = <2>;
876 };
877
878 pcs7_3: ethernet-phy@3 {
879 reg = <3>;
880 };
881 };
882
883 cluster1_core0_watchdog: watchdog@c000000 {
884 compatible = "arm,sp805", "arm,primecell";
885 reg = <0x0 0xc000000 0x0 0x1000>;
886 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
887 QORIQ_CLK_PLL_DIV(16)>,
888 <&clockgen QORIQ_CLK_PLATFORM_PLL
889 QORIQ_CLK_PLL_DIV(16)>;
890 clock-names = "wdog_clk", "apb_pclk";
891 };
892
893 cluster1_core1_watchdog: watchdog@c010000 {
894 compatible = "arm,sp805", "arm,primecell";
895 reg = <0x0 0xc010000 0x0 0x1000>;
896 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
897 QORIQ_CLK_PLL_DIV(16)>,
898 <&clockgen QORIQ_CLK_PLATFORM_PLL
899 QORIQ_CLK_PLL_DIV(16)>;
900 clock-names = "wdog_clk", "apb_pclk";
901 };
902
903 cluster1_core2_watchdog: watchdog@c020000 {
904 compatible = "arm,sp805", "arm,primecell";
905 reg = <0x0 0xc020000 0x0 0x1000>;
906 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
907 QORIQ_CLK_PLL_DIV(16)>,
908 <&clockgen QORIQ_CLK_PLATFORM_PLL
909 QORIQ_CLK_PLL_DIV(16)>;
910 clock-names = "wdog_clk", "apb_pclk";
911 };
912
913 cluster1_core3_watchdog: watchdog@c030000 {
914 compatible = "arm,sp805", "arm,primecell";
915 reg = <0x0 0xc030000 0x0 0x1000>;
916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
917 QORIQ_CLK_PLL_DIV(16)>,
918 <&clockgen QORIQ_CLK_PLATFORM_PLL
919 QORIQ_CLK_PLL_DIV(16)>;
920 clock-names = "wdog_clk", "apb_pclk";
921 };
922
923 cluster2_core0_watchdog: watchdog@c100000 {
924 compatible = "arm,sp805", "arm,primecell";
925 reg = <0x0 0xc100000 0x0 0x1000>;
926 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
927 QORIQ_CLK_PLL_DIV(16)>,
928 <&clockgen QORIQ_CLK_PLATFORM_PLL
929 QORIQ_CLK_PLL_DIV(16)>;
930 clock-names = "wdog_clk", "apb_pclk";
931 };
932
933 cluster2_core1_watchdog: watchdog@c110000 {
934 compatible = "arm,sp805", "arm,primecell";
935 reg = <0x0 0xc110000 0x0 0x1000>;
936 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
937 QORIQ_CLK_PLL_DIV(16)>,
938 <&clockgen QORIQ_CLK_PLATFORM_PLL
939 QORIQ_CLK_PLL_DIV(16)>;
940 clock-names = "wdog_clk", "apb_pclk";
941 };
942
943 cluster2_core2_watchdog: watchdog@c120000 {
944 compatible = "arm,sp805", "arm,primecell";
945 reg = <0x0 0xc120000 0x0 0x1000>;
946 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
947 QORIQ_CLK_PLL_DIV(16)>,
948 <&clockgen QORIQ_CLK_PLATFORM_PLL
949 QORIQ_CLK_PLL_DIV(16)>;
950 clock-names = "wdog_clk", "apb_pclk";
951 };
952
953 cluster2_core3_watchdog: watchdog@c130000 {
954 compatible = "arm,sp805", "arm,primecell";
955 reg = <0x0 0xc130000 0x0 0x1000>;
956 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
957 QORIQ_CLK_PLL_DIV(16)>,
958 <&clockgen QORIQ_CLK_PLATFORM_PLL
959 QORIQ_CLK_PLL_DIV(16)>;
960 clock-names = "wdog_clk", "apb_pclk";
961 };
962
963 fsl_mc: fsl-mc@80c000000 {
964 compatible = "fsl,qoriq-mc";
965 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
966 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
967 msi-parent = <&its>;
968 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
969 dma-coherent;
970 #address-cells = <3>;
971 #size-cells = <1>;
972
973 /*
974 * Region type 0x0 - MC portals
975 * Region type 0x1 - QBMAN portals
976 */
977 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
978 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
979
980 dpmacs {
981 #address-cells = <1>;
982 #size-cells = <0>;
983
984 dpmac1: ethernet@1 {
985 compatible = "fsl,qoriq-mc-dpmac";
986 reg = <1>;
987 };
988
989 dpmac2: ethernet@2 {
990 compatible = "fsl,qoriq-mc-dpmac";
991 reg = <2>;
992 };
993
994 dpmac3: ethernet@3 {
995 compatible = "fsl,qoriq-mc-dpmac";
996 reg = <3>;
997 };
998
999 dpmac4: ethernet@4 {
1000 compatible = "fsl,qoriq-mc-dpmac";
1001 reg = <4>;
1002 };
1003
1004 dpmac5: ethernet@5 {
1005 compatible = "fsl,qoriq-mc-dpmac";
1006 reg = <5>;
1007 };
1008
1009 dpmac6: ethernet@6 {
1010 compatible = "fsl,qoriq-mc-dpmac";
1011 reg = <6>;
1012 };
1013
1014 dpmac7: ethernet@7 {
1015 compatible = "fsl,qoriq-mc-dpmac";
1016 reg = <7>;
1017 };
1018
1019 dpmac8: ethernet@8 {
1020 compatible = "fsl,qoriq-mc-dpmac";
1021 reg = <8>;
1022 };
1023
1024 dpmac9: ethernet@9 {
1025 compatible = "fsl,qoriq-mc-dpmac";
1026 reg = <9>;
1027 };
1028
1029 dpmac10: ethernet@a {
1030 compatible = "fsl,qoriq-mc-dpmac";
1031 reg = <0xa>;
1032 };
1033 };
1034 };
1035
1036 rcpm: power-controller@1e34040 {
1037 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1038 reg = <0x0 0x1e34040 0x0 0x18>;
1039 #fsl,rcpm-wakeup-cells = <6>;
1040 little-endian;
1041 };
1042
1043 ftm_alarm0: rtc@2800000 {
1044 compatible = "fsl,ls1088a-ftm-alarm";
1045 reg = <0x0 0x2800000 0x0 0x10000>;
1046 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1047 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1048 };
1049 };
1050
1051 firmware {
1052 optee {
1053 compatible = "linaro,optee-tz";
1054 method = "smc";
1055 };
1056 };
1057 };
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