1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2024 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9
10 cm41_ipg_clk: clock-cm41-ipg {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <132000000>;
14 clock-output-names = "cm41_ipg_clk";
15 };
16
17 cm41_subsys: bus@38000000 {
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0x38000000 0x0 0x38000000 0x4000000>;
22 interrupt-parent = <&cm41_intmux>;
23
24 cm41_i2c: i2c@3b230000 {
25 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
26 reg = <0x3b230000 0x1000>;
27 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
28 clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>,
29 <&cm41_i2c_lpcg IMX_LPCG_CLK_4>;
30 clock-names = "per", "ipg";
31 assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;
32 assigned-clock-rates = <24000000>;
33 power-domains = <&pd IMX_SC_R_M4_1_I2C>;
34 status = "disabled";
35 };
36
37 cm41_intmux: intmux@3b400000 {
38 compatible = "fsl,imx-intmux";
39 reg = <0x3b400000 0x1000>;
40 interrupt-parent = <&gic>;
41 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
49 interrupt-controller;
50 #interrupt-cells = <2>;
51 clocks = <&cm41_ipg_clk>;
52 clock-names = "ipg";
53 power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;
54 status = "disabled";
55 };
56
57 cm41_i2c_lpcg: clock-controller@3b630000 {
58 compatible = "fsl,imx8qxp-lpcg";
59 reg = <0x3b630000 0x1000>;
60 #clock-cells = <1>;
61 clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,
62 <&cm41_ipg_clk>;
63 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
64 clock-output-names = "cm41_lpcg_i2c_clk",
65 "cm41_lpcg_i2c_ipg_clk";
66 power-domains = <&pd IMX_SC_R_M4_1_I2C>;
67 };
68 };
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