1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com>
5 */
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
11 };
12
13 img_subsys: bus@58000000 {
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
18
19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
22 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
23 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
24 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
25 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
26 assigned-clock-rates = <200000000>, <200000000>;
27 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
28 <&pd IMX_SC_R_MJPEG_DEC_S0>;
29 slot = <0>;
30 };
31
32 jpegenc: jpegenc@58450000 {
33 reg = <0x58450000 0x00050000>;
34 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
36 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
37 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
38 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
39 assigned-clock-rates = <200000000>, <200000000>;
40 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
41 <&pd IMX_SC_R_MJPEG_ENC_S0>;
42 slot = <0>;
43 };
44
45 img_jpeg_dec_lpcg: clock-controller@585d0000 {
46 compatible = "fsl,imx8qxp-lpcg";
47 reg = <0x585d0000 0x10000>;
48 #clock-cells = <1>;
49 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
50 clock-indices = <IMX_LPCG_CLK_0>,
51 <IMX_LPCG_CLK_4>;
52 clock-output-names = "img_jpeg_dec_lpcg_clk",
53 "img_jpeg_dec_lpcg_ipg_clk";
54 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
55 };
56
57 img_jpeg_enc_lpcg: clock-controller@585f0000 {
58 compatible = "fsl,imx8qxp-lpcg";
59 reg = <0x585f0000 0x10000>;
60 #clock-cells = <1>;
61 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
62 clock-indices = <IMX_LPCG_CLK_0>,
63 <IMX_LPCG_CLK_4>;
64 clock-output-names = "img_jpeg_enc_lpcg_clk",
65 "img_jpeg_enc_lpcg_ipg_clk";
66 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
67 };
68 };
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