1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9
10 / {
11 aliases {
12 ethernet1 = ð1;
13 usb0 = &usbotg1;
14 usb1 = &usbotg2;
15 };
16
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
21
22 led-0 {
23 function = LED_FUNCTION_STATUS;
24 color = <LED_COLOR_ID_GREEN>;
25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26 default-state = "on";
27 linux,default-trigger = "heartbeat";
28 };
29
30 led-1 {
31 function = LED_FUNCTION_STATUS;
32 color = <LED_COLOR_ID_RED>;
33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
35 };
36 };
37
38 pcie0_refclk: pcie0-refclk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <100000000>;
42 };
43
44 pps {
45 compatible = "pps-gpio";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49 status = "okay";
50 };
51
52 reg_3p3v: regulator-3p3v {
53 compatible = "regulator-fixed";
54 regulator-name = "3P3V";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 regulator-always-on;
58 };
59
60 reg_usb_otg1_vbus: regulator-usb-otg1 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_reg_usb1_en>;
63 compatible = "regulator-fixed";
64 regulator-name = "usb_otg1_vbus";
65 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 };
70
71 reg_usb_otg2_vbus: regulator-usb-otg2 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_reg_usb2_en>;
74 compatible = "regulator-fixed";
75 regulator-name = "usb_otg2_vbus";
76 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 };
81 };
82
83 /* off-board header */
84 &ecspi2 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_spi2>;
87 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
88 <&gpio1 10 GPIO_ACTIVE_LOW>;
89 status = "okay";
90
91 tpm@1 {
92 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
93 reg = <0x1>;
94 spi-max-frequency = <36000000>;
95 };
96 };
97
98 &gpio1 {
99 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
100 "", "", "pci_usb_sel", "dio0",
101 "", "dio1", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "";
104 };
105
106 &gpio4 {
107 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
108 "mipi_gpio1", "", "", "pci_wdis#",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 "", "", "", "", "", "", "", "";
112 };
113
114 &i2c2 {
115 clock-frequency = <400000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c2>;
118 status = "okay";
119
120 accelerometer@19 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_accel>;
123 compatible = "st,lis2de12";
124 reg = <0x19>;
125 st,drdy-int-pin = <1>;
126 interrupt-parent = <&gpio4>;
127 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
128 };
129 };
130
131 /* off-board header */
132 &i2c3 {
133 clock-frequency = <400000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c3>;
136 status = "okay";
137 };
138
139 &pcie_phy {
140 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
141 fsl,clkreq-unsupported;
142 clocks = <&pcie0_refclk>;
143 clock-names = "ref";
144 status = "okay";
145 };
146
147 &pcie0 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_pcie0>;
150 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
151 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
152 <&clk IMX8MM_CLK_PCIE1_AUX>;
153 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
154 <&clk IMX8MM_CLK_PCIE1_CTRL>;
155 assigned-clock-rates = <10000000>, <250000000>;
156 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
157 <&clk IMX8MM_SYS_PLL2_250M>;
158 status = "okay";
159
160 pcie@0,0 {
161 reg = <0x0000 0 0 0 0>;
162 device_type = "pci";
163 #address-cells = <3>;
164 #size-cells = <2>;
165 ranges;
166
167 pcie@0,0 {
168 reg = <0x0000 0 0 0 0>;
169 device_type = "pci";
170 #address-cells = <3>;
171 #size-cells = <2>;
172 ranges;
173
174 pcie@3,0 {
175 reg = <0x1800 0 0 0 0>;
176 device_type = "pci";
177 #address-cells = <3>;
178 #size-cells = <2>;
179 ranges;
180
181 eth1: ethernet@0,0 {
182 reg = <0x0000 0 0 0 0>;
183 #address-cells = <3>;
184 #size-cells = <2>;
185 ranges;
186
187 local-mac-address = [00 00 00 00 00 00];
188 };
189 };
190 };
191 };
192 };
193
194 /* off-board header */
195 &sai3 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_sai3>;
198 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
199 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
200 assigned-clock-rates = <24576000>;
201 status = "okay";
202 };
203
204 /* GPS */
205 &uart1 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_uart1>;
208 status = "okay";
209 };
210
211 /* off-board header */
212 &uart3 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_uart3>;
215 status = "okay";
216 };
217
218 /* RS232 */
219 &uart4 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_uart4>;
222 status = "okay";
223 };
224
225 &usbotg1 {
226 dr_mode = "otg";
227 over-current-active-low;
228 vbus-supply = <®_usb_otg1_vbus>;
229 status = "okay";
230 };
231
232 &usbotg2 {
233 dr_mode = "host";
234 disable-over-current;
235 vbus-supply = <®_usb_otg2_vbus>;
236 status = "okay";
237 };
238
239 /* microSD */
240 &usdhc2 {
241 pinctrl-names = "default", "state_100mhz", "state_200mhz";
242 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
243 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
244 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
245 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
246 bus-width = <4>;
247 vmmc-supply = <®_3p3v>;
248 status = "okay";
249 };
250
251 &iomuxc {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_hog>;
254
255 pinctrl_hog: hoggrp {
256 fsl,pins = <
257 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
258 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
259 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
260 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
261 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
262 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
263 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
264 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
265 >;
266 };
267
268 pinctrl_accel: accelgrp {
269 fsl,pins = <
270 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
271 >;
272 };
273
274 pinctrl_gpio_leds: gpioledgrp {
275 fsl,pins = <
276 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
277 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
278 >;
279 };
280
281 pinctrl_i2c3: i2c3grp {
282 fsl,pins = <
283 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
284 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
285 >;
286 };
287
288 pinctrl_pcie0: pcie0grp {
289 fsl,pins = <
290 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
291 >;
292 };
293
294 pinctrl_pps: ppsgrp {
295 fsl,pins = <
296 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
297 >;
298 };
299
300 pinctrl_reg_usb1_en: regusb1grp {
301 fsl,pins = <
302 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
303 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
304 >;
305 };
306
307 pinctrl_reg_usb2_en: regusb2grp {
308 fsl,pins = <
309 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
310 >;
311 };
312
313 pinctrl_sai3: sai3grp {
314 fsl,pins = <
315 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
316 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
317 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
318 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
319 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
320 >;
321 };
322
323 pinctrl_spi2: spi2grp {
324 fsl,pins = <
325 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
326 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
327 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
328 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
329 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
330 >;
331 };
332
333 pinctrl_uart1: uart1grp {
334 fsl,pins = <
335 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
336 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
337 >;
338 };
339
340 pinctrl_uart3: uart3grp {
341 fsl,pins = <
342 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
343 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
344 >;
345 };
346
347 pinctrl_uart4: uart4grp {
348 fsl,pins = <
349 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
350 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
351 >;
352 };
353
354 pinctrl_usdhc1: usdhc1grp {
355 fsl,pins = <
356 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
357 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
358 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
359 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
360 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
361 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
362 >;
363 };
364
365 pinctrl_usdhc2: usdhc2grp {
366 fsl,pins = <
367 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
368 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
369 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
370 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
371 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
372 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
373 >;
374 };
375
376 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
377 fsl,pins = <
378 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
379 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
380 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
381 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
382 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
383 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
384 >;
385 };
386
387 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
388 fsl,pins = <
389 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
390 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
391 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
392 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
393 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
394 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
395 >;
396 };
397
398 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
399 fsl,pins = <
400 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
401 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
402 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
403 >;
404 };
405 };
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