1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Supports Symphony evaluation board versions >= 1.4a.
4 *
5 * Copyright 2019-2020 Variscite Ltd.
6 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/usb/pd.h>
12 #include "imx8mn-var-som.dtsi"
13
14 / {
15 model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
16 compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
17
18 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
22 regulator-name = "VSD_3V3";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
26 enable-active-high;
27 };
28
29 gpio-keys {
30 compatible = "gpio-keys";
31
32 key-back {
33 label = "Back";
34 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_BACK>;
36 };
37
38 key-home {
39 label = "Home";
40 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
41 linux,code = <KEY_HOME>;
42 };
43
44 key-menu {
45 label = "Menu";
46 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
47 linux,code = <KEY_MENU>;
48 };
49 };
50
51 leds {
52 compatible = "gpio-leds";
53
54 led {
55 label = "Heartbeat";
56 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
57 linux,default-trigger = "heartbeat";
58 };
59 };
60
61 /* Peripherals supply, enabled by Q2 after SOM_3V3 rises. */
62 reg_per_3v3: regulator-peripheral-3v3 {
63 compatible = "regulator-fixed";
64 regulator-name = "per_3v3";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 regulator-always-on;
68 };
69 };
70
71 ðphy {
72 reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
73 };
74
75 &i2c2 {
76 clock-frequency = <400000>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_i2c2>;
79 status = "okay";
80
81 pca9534: gpio@20 {
82 compatible = "nxp,pca9534";
83 reg = <0x20>;
84 gpio-controller;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_pca9534>;
87 interrupt-parent = <&gpio1>;
88 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
89 #gpio-cells = <2>;
90 wakeup-source;
91 vcc-supply = <®_per_3v3>;
92
93 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
94 usb3-sata-sel-hog {
95 gpio-hog;
96 gpios = <4 GPIO_ACTIVE_HIGH>;
97 output-low;
98 line-name = "usb3_sata_sel";
99 };
100
101 som-vselect-hog {
102 gpio-hog;
103 gpios = <6 GPIO_ACTIVE_HIGH>;
104 output-low;
105 line-name = "som_vselect";
106 };
107
108 enet-sel-hog {
109 gpio-hog;
110 gpios = <7 GPIO_ACTIVE_HIGH>;
111 output-low;
112 line-name = "enet_sel";
113 };
114 };
115
116 /*
117 * For Symphony board version <= 1.4, the PTN5150 IRQ pin is connected
118 * to GPIO1_IO11 on the SoM (R106 present, R132 absent). From Symphony
119 * board version >= 1.4a, the PTN5150 ID pin is connected to GPIO1_IO11
120 * on the SoM (R106 absent, R132 present).
121 */
122 extcon_usbotg1: typec@3d {
123 compatible = "nxp,ptn5150";
124 reg = <0x3d>;
125 interrupt-parent = <&gpio1>;
126 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_ptn5150>;
129
130 port {
131 typec1_dr_sw: endpoint {
132 remote-endpoint = <&usb1_drd_sw>;
133 };
134 };
135 };
136 };
137
138 &i2c3 {
139 /* Capacitive touch controller */
140 ft5x06_ts: touchscreen@38 {
141 compatible = "edt,edt-ft5406";
142 reg = <0x38>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_captouch>;
145 interrupt-parent = <&gpio5>;
146 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
147
148 touchscreen-size-x = <800>;
149 touchscreen-size-y = <480>;
150 touchscreen-inverted-x;
151 touchscreen-inverted-y;
152 };
153
154 rtc@68 {
155 compatible = "dallas,ds1337";
156 reg = <0x68>;
157 };
158 };
159
160 /* Header */
161 &uart1 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_uart1>;
164 status = "okay";
165 };
166
167 /* Header */
168 &uart3 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_uart3>;
171 status = "okay";
172 };
173
174 &usbotg1 {
175 dr_mode = "otg";
176 hnp-disable;
177 srp-disable;
178 adp-disable;
179 usb-role-switch;
180 disable-over-current;
181 samsung,picophy-pre-emp-curr-control = <3>;
182 samsung,picophy-dc-vol-level-adjust = <7>;
183 status = "okay";
184
185 port {
186 usb1_drd_sw: endpoint {
187 remote-endpoint = <&typec1_dr_sw>;
188 };
189 };
190 };
191
192 &iomuxc {
193 pinctrl_captouch: captouchgrp {
194 fsl,pins = <
195 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
196 >;
197 };
198
199 pinctrl_i2c2: i2c2grp {
200 fsl,pins = <
201 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
202 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
203 >;
204 };
205
206 pinctrl_pca9534: pca9534grp {
207 fsl,pins = <
208 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
209 >;
210 };
211
212 pinctrl_ptn5150: ptn5150grp {
213 fsl,pins = <
214 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
215 >;
216 };
217
218 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
219 fsl,pins = <
220 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
221 >;
222 };
223
224 pinctrl_uart1: uart1grp {
225 fsl,pins = <
226 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
227 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
228 >;
229 };
230
231 pinctrl_uart3: uart3grp {
232 fsl,pins = <
233 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
234 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
235 >;
236 };
237 };
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