1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include "imx8mp.dtsi"
10
11 / {
12 model = "NXP i.MX8MPlus EVK board";
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
14
15 chosen {
16 stdout-path = &uart2;
17 };
18
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
21 pwms = <&pwm2 0 100000 0>;
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
25 power-supply = <®_per_12v>;
26 status = "disabled";
27 };
28
29 hdmi-connector {
30 compatible = "hdmi-connector";
31 label = "hdmi";
32 type = "a";
33
34 port {
35 hdmi_connector_in: endpoint {
36 remote-endpoint = <&adv7535_out>;
37 };
38 };
39 };
40
41 gpio-leds {
42 compatible = "gpio-leds";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_gpio_led>;
45
46 status {
47 label = "yellow:status";
48 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
49 default-state = "on";
50 };
51 };
52
53 memory@40000000 {
54 device_type = "memory";
55 reg = <0x0 0x40000000 0 0xc0000000>,
56 <0x1 0x00000000 0 0xc0000000>;
57 };
58
59 pcie0_refclk: pcie0-refclk {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <100000000>;
63 };
64
65 reg_audio_pwr: regulator-audio-pwr {
66 compatible = "regulator-fixed";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_audio_pwr_reg>;
69 regulator-name = "audio-pwr";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
76 reg_can1_stby: regulator-can1-stby {
77 compatible = "regulator-fixed";
78 regulator-name = "can1-stby";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_flexcan1_reg>;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 reg_can2_stby: regulator-can2-stby {
88 compatible = "regulator-fixed";
89 regulator-name = "can2-stby";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_flexcan2_reg>;
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
95 enable-active-high;
96 };
97
98 reg_pcie0: regulator-pcie {
99 compatible = "regulator-fixed";
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_pcie0_reg>;
102 regulator-name = "MPCIE_3V3";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 };
108
109 reg_per_12v: regulator-per-12v {
110 compatible = "regulator-fixed";
111 regulator-name = "PER_12V";
112 regulator-min-microvolt = <12000000>;
113 regulator-max-microvolt = <12000000>;
114 gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
115 enable-active-high;
116 };
117
118 reg_usdhc2_vmmc: regulator-usdhc2 {
119 compatible = "regulator-fixed";
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
122 regulator-name = "VSD_3V3";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
126 enable-active-high;
127 };
128
129 reg_vext_3v3: regulator-vext-3v3 {
130 compatible = "regulator-fixed";
131 regulator-name = "VEXT_3V3";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 };
135
136 audio_codec_bt_sco: audio-codec-bt-sco {
137 compatible = "linux,bt-sco";
138 #sound-dai-cells = <1>;
139 };
140
141 sound {
142 compatible = "simple-audio-card";
143 simple-audio-card,name = "wm8960-audio";
144 simple-audio-card,format = "i2s";
145 simple-audio-card,frame-master = <&cpudai>;
146 simple-audio-card,bitclock-master = <&cpudai>;
147 simple-audio-card,widgets =
148 "Headphone", "Headphone Jack",
149 "Speaker", "External Speaker",
150 "Microphone", "Mic Jack";
151 simple-audio-card,routing =
152 "Headphone Jack", "HP_L",
153 "Headphone Jack", "HP_R",
154 "External Speaker", "SPK_LP",
155 "External Speaker", "SPK_LN",
156 "External Speaker", "SPK_RP",
157 "External Speaker", "SPK_RN",
158 "LINPUT1", "Mic Jack",
159 "LINPUT3", "Mic Jack",
160 "Mic Jack", "MICB";
161
162 cpudai: simple-audio-card,cpu {
163 sound-dai = <&sai3>;
164 };
165
166 simple-audio-card,codec {
167 sound-dai = <&wm8960>;
168 };
169
170 };
171
172 sound-bt-sco {
173 compatible = "simple-audio-card";
174 simple-audio-card,name = "bt-sco-audio";
175 simple-audio-card,format = "dsp_a";
176 simple-audio-card,bitclock-inversion;
177 simple-audio-card,frame-master = <&btcpu>;
178 simple-audio-card,bitclock-master = <&btcpu>;
179
180 btcpu: simple-audio-card,cpu {
181 sound-dai = <&sai2>;
182 dai-tdm-slot-num = <2>;
183 dai-tdm-slot-width = <16>;
184 };
185
186 simple-audio-card,codec {
187 sound-dai = <&audio_codec_bt_sco 1>;
188 };
189 };
190
191 sound-hdmi {
192 compatible = "fsl,imx-audio-hdmi";
193 model = "audio-hdmi";
194 audio-cpu = <&aud2htx>;
195 hdmi-out;
196 };
197
198 sound-micfil {
199 compatible = "fsl,imx-audio-card";
200 model = "micfil-audio";
201
202 pri-dai-link {
203 link-name = "micfil hifi";
204 format = "i2s";
205
206 cpu {
207 sound-dai = <&micfil>;
208 };
209 };
210 };
211
212 sound-xcvr {
213 compatible = "fsl,imx-audio-card";
214 model = "imx-audio-xcvr";
215
216 pri-dai-link {
217 link-name = "XCVR PCM";
218
219 cpu {
220 sound-dai = <&xcvr>;
221 };
222 };
223 };
224
225 reserved-memory {
226 #address-cells = <2>;
227 #size-cells = <2>;
228 ranges;
229
230 dsp_vdev0vring0: vdev0vring0@942f0000 {
231 reg = <0 0x942f0000 0 0x8000>;
232 no-map;
233 };
234
235 dsp_vdev0vring1: vdev0vring1@942f8000 {
236 reg = <0 0x942f8000 0 0x8000>;
237 no-map;
238 };
239
240 dsp_vdev0buffer: vdev0buffer@94300000 {
241 compatible = "shared-dma-pool";
242 reg = <0 0x94300000 0 0x100000>;
243 no-map;
244 };
245 };
246 };
247
248 &flexspi {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_flexspi0>;
251 status = "okay";
252
253 flash@0 {
254 compatible = "jedec,spi-nor";
255 reg = <0>;
256 spi-max-frequency = <80000000>;
257 spi-tx-bus-width = <1>;
258 spi-rx-bus-width = <4>;
259 };
260 };
261
262 &A53_0 {
263 cpu-supply = <®_arm>;
264 };
265
266 &A53_1 {
267 cpu-supply = <®_arm>;
268 };
269
270 &A53_2 {
271 cpu-supply = <®_arm>;
272 };
273
274 &A53_3 {
275 cpu-supply = <®_arm>;
276 };
277
278 &aud2htx {
279 status = "okay";
280 };
281
282 &eqos {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_eqos>;
285 phy-mode = "rgmii-id";
286 phy-handle = <ðphy0>;
287 snps,force_thresh_dma_mode;
288 snps,mtl-tx-config = <&mtl_tx_setup>;
289 snps,mtl-rx-config = <&mtl_rx_setup>;
290 status = "okay";
291
292 mdio {
293 compatible = "snps,dwmac-mdio";
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 ethphy0: ethernet-phy@1 {
298 compatible = "ethernet-phy-ieee802.3-c22";
299 reg = <1>;
300 eee-broken-1000t;
301 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
302 reset-assert-us = <10000>;
303 reset-deassert-us = <80000>;
304 realtek,clkout-disable;
305 };
306 };
307
308 mtl_tx_setup: tx-queues-config {
309 snps,tx-queues-to-use = <5>;
310
311 queue0 {
312 snps,dcb-algorithm;
313 snps,priority = <0x1>;
314 };
315
316 queue1 {
317 snps,dcb-algorithm;
318 snps,priority = <0x2>;
319 };
320
321 queue2 {
322 snps,dcb-algorithm;
323 snps,priority = <0x4>;
324 };
325
326 queue3 {
327 snps,dcb-algorithm;
328 snps,priority = <0x8>;
329 };
330
331 queue4 {
332 snps,dcb-algorithm;
333 snps,priority = <0xf0>;
334 };
335 };
336
337 mtl_rx_setup: rx-queues-config {
338 snps,rx-queues-to-use = <5>;
339 snps,rx-sched-sp;
340
341 queue0 {
342 snps,dcb-algorithm;
343 snps,priority = <0x1>;
344 snps,map-to-dma-channel = <0>;
345 };
346
347 queue1 {
348 snps,dcb-algorithm;
349 snps,priority = <0x2>;
350 snps,map-to-dma-channel = <1>;
351 };
352
353 queue2 {
354 snps,dcb-algorithm;
355 snps,priority = <0x4>;
356 snps,map-to-dma-channel = <2>;
357 };
358
359 queue3 {
360 snps,dcb-algorithm;
361 snps,priority = <0x8>;
362 snps,map-to-dma-channel = <3>;
363 };
364
365 queue4 {
366 snps,dcb-algorithm;
367 snps,priority = <0xf0>;
368 snps,map-to-dma-channel = <4>;
369 };
370 };
371 };
372
373 &fec {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_fec>;
376 phy-mode = "rgmii-id";
377 phy-handle = <ðphy1>;
378 fsl,magic-packet;
379 status = "okay";
380
381 mdio {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 ethphy1: ethernet-phy@1 {
386 compatible = "ethernet-phy-ieee802.3-c22";
387 reg = <1>;
388 eee-broken-1000t;
389 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
390 reset-assert-us = <10000>;
391 reset-deassert-us = <80000>;
392 realtek,clkout-disable;
393 };
394 };
395 };
396
397 &flexcan1 {
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_flexcan1>;
400 xceiver-supply = <®_can1_stby>;
401 status = "okay";
402 };
403
404 &flexcan2 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_flexcan2>;
407 xceiver-supply = <®_can2_stby>;
408 status = "disabled";/* can2 pin conflict with pdm */
409 };
410
411 &i2c1 {
412 clock-frequency = <400000>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_i2c1>;
415 status = "okay";
416
417 pmic@25 {
418 compatible = "nxp,pca9450c";
419 reg = <0x25>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_pmic>;
422 interrupt-parent = <&gpio1>;
423 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
424
425 regulators {
426 BUCK1 {
427 regulator-name = "BUCK1";
428 regulator-min-microvolt = <720000>;
429 regulator-max-microvolt = <1000000>;
430 regulator-boot-on;
431 regulator-always-on;
432 regulator-ramp-delay = <3125>;
433 };
434
435 reg_arm: BUCK2 {
436 regulator-name = "BUCK2";
437 regulator-min-microvolt = <720000>;
438 regulator-max-microvolt = <1025000>;
439 regulator-boot-on;
440 regulator-always-on;
441 regulator-ramp-delay = <3125>;
442 nxp,dvs-run-voltage = <950000>;
443 nxp,dvs-standby-voltage = <850000>;
444 };
445
446 BUCK4 {
447 regulator-name = "BUCK4";
448 regulator-min-microvolt = <3000000>;
449 regulator-max-microvolt = <3600000>;
450 regulator-boot-on;
451 regulator-always-on;
452 };
453
454 reg_buck5: BUCK5 {
455 regulator-name = "BUCK5";
456 regulator-min-microvolt = <1650000>;
457 regulator-max-microvolt = <1950000>;
458 regulator-boot-on;
459 regulator-always-on;
460 };
461
462 BUCK6 {
463 regulator-name = "BUCK6";
464 regulator-min-microvolt = <1045000>;
465 regulator-max-microvolt = <1155000>;
466 regulator-boot-on;
467 regulator-always-on;
468 };
469
470 LDO1 {
471 regulator-name = "LDO1";
472 regulator-min-microvolt = <1650000>;
473 regulator-max-microvolt = <1950000>;
474 regulator-boot-on;
475 regulator-always-on;
476 };
477
478 LDO3 {
479 regulator-name = "LDO3";
480 regulator-min-microvolt = <1710000>;
481 regulator-max-microvolt = <1890000>;
482 regulator-boot-on;
483 regulator-always-on;
484 };
485
486 LDO5 {
487 regulator-name = "LDO5";
488 regulator-min-microvolt = <1800000>;
489 regulator-max-microvolt = <3300000>;
490 regulator-boot-on;
491 regulator-always-on;
492 };
493 };
494 };
495 };
496
497 &i2c2 {
498 clock-frequency = <400000>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_i2c2>;
501 status = "okay";
502
503 hdmi@3d {
504 compatible = "adi,adv7535";
505 reg = <0x3d>;
506 interrupt-parent = <&gpio1>;
507 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
508 adi,dsi-lanes = <4>;
509 avdd-supply = <®_buck5>;
510 dvdd-supply = <®_buck5>;
511 pvdd-supply = <®_buck5>;
512 a2vdd-supply = <®_buck5>;
513 v3p3-supply = <®_vext_3v3>;
514 v1p2-supply = <®_buck5>;
515
516 ports {
517 #address-cells = <1>;
518 #size-cells = <0>;
519
520 port@0 {
521 reg = <0>;
522
523 adv7535_in: endpoint {
524 remote-endpoint = <&dsi_out>;
525 };
526 };
527
528 port@1 {
529 reg = <1>;
530
531 adv7535_out: endpoint {
532 remote-endpoint = <&hdmi_connector_in>;
533 };
534 };
535
536 };
537 };
538 };
539
540 &i2c3 {
541 clock-frequency = <400000>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_i2c3>;
544 status = "okay";
545
546 wm8960: codec@1a {
547 compatible = "wlf,wm8960";
548 reg = <0x1a>;
549 #sound-dai-cells = <0>;
550 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
551 clock-names = "mclk";
552 wlf,shared-lrclk;
553 wlf,hp-cfg = <3 2 3>;
554 wlf,gpio-cfg = <1 3>;
555 SPKVDD1-supply = <®_audio_pwr>;
556 };
557
558 pca6416: gpio@20 {
559 compatible = "ti,tca6416";
560 reg = <0x20>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_pca6416_int>;
567 interrupt-parent = <&gpio1>;
568 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
569 gpio-line-names = "EXT_PWREN1",
570 "EXT_PWREN2",
571 "CAN1/I2C5_SEL",
572 "PDM/CAN2_SEL",
573 "FAN_EN",
574 "PWR_MEAS_IO1",
575 "PWR_MEAS_IO2",
576 "EXP_P0_7",
577 "EXP_P1_0",
578 "EXP_P1_1",
579 "EXP_P1_2",
580 "EXP_P1_3",
581 "EXP_P1_4",
582 "EXP_P1_5",
583 "EXP_P1_6",
584 "EXP_P1_7";
585 };
586 };
587
588 /* I2C on expansion connector J22. */
589 &i2c5 {
590 clock-frequency = <100000>; /* Lower clock speed for external bus. */
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_i2c5>;
593 status = "disabled"; /* can1 pins conflict with i2c5 */
594
595 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
596 * LOW: CAN1 (default, pull-down)
597 * HIGH: I2C5
598 * You need to set it to high to enable I2C5 (for example, add gpio-hog
599 * in pca6416 node).
600 */
601 };
602
603 &lcdif1 {
604 status = "okay";
605 };
606
607 &micfil {
608 #sound-dai-cells = <0>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_pdm>;
611 assigned-clocks = <&clk IMX8MP_CLK_PDM>;
612 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
613 assigned-clock-rates = <196608000>;
614 status = "okay";
615 };
616
617 &mipi_dsi {
618 samsung,esc-clock-frequency = <10000000>;
619 status = "okay";
620
621 ports {
622 port@1 {
623 reg = <1>;
624
625 dsi_out: endpoint {
626 remote-endpoint = <&adv7535_in>;
627 data-lanes = <1 2 3 4>;
628 };
629 };
630 };
631 };
632
633 &pcie_phy {
634 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
635 clocks = <&pcie0_refclk>;
636 clock-names = "ref";
637 status = "okay";
638 };
639
640 &pcie {
641 pinctrl-names = "default";
642 pinctrl-0 = <&pinctrl_pcie0>;
643 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
644 vpcie-supply = <®_pcie0>;
645 status = "okay";
646 };
647
648 &pwm1 {
649 pinctrl-names = "default";
650 pinctrl-0 = <&pinctrl_pwm1>;
651 status = "okay";
652 };
653
654 &pwm2 {
655 pinctrl-names = "default";
656 pinctrl-0 = <&pinctrl_pwm2>;
657 status = "okay";
658 };
659
660 &pwm4 {
661 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_pwm4>;
663 status = "okay";
664 };
665
666 &sai2 {
667 #sound-dai-cells = <0>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_sai2>;
670 assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
671 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
672 assigned-clock-rates = <12288000>;
673 fsl,sai-mclk-direction-output;
674 status = "okay";
675 };
676
677 &sai3 {
678 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_sai3>;
680 assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
681 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
682 assigned-clock-rates = <12288000>;
683 fsl,sai-mclk-direction-output;
684 status = "okay";
685 };
686
687 &snvs_pwrkey {
688 status = "okay";
689 };
690
691 &uart1 { /* BT */
692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_uart1>;
694 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
695 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
696 uart-has-rtscts;
697 status = "okay";
698 };
699
700 &uart2 {
701 /* console */
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_uart2>;
704 status = "okay";
705 };
706
707 &usb3_phy1 {
708 status = "okay";
709 };
710
711 &usb3_1 {
712 status = "okay";
713 };
714
715 &usb_dwc3_1 {
716 pinctrl-names = "default";
717 pinctrl-0 = <&pinctrl_usb1_vbus>;
718 dr_mode = "host";
719 status = "okay";
720 };
721
722 &uart3 {
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_uart3>;
725 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
726 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
727 uart-has-rtscts;
728 status = "okay";
729 };
730
731 &usdhc2 {
732 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
733 assigned-clock-rates = <400000000>;
734 pinctrl-names = "default", "state_100mhz", "state_200mhz";
735 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
736 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
737 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
738 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
739 vmmc-supply = <®_usdhc2_vmmc>;
740 bus-width = <4>;
741 status = "okay";
742 };
743
744 &usdhc3 {
745 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
746 assigned-clock-rates = <400000000>;
747 pinctrl-names = "default", "state_100mhz", "state_200mhz";
748 pinctrl-0 = <&pinctrl_usdhc3>;
749 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
750 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
751 bus-width = <8>;
752 non-removable;
753 status = "okay";
754 };
755
756 &wdog1 {
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_wdog>;
759 fsl,ext-reset-output;
760 status = "okay";
761 };
762
763 &xcvr {
764 #sound-dai-cells = <0>;
765 status = "okay";
766 };
767
768 &iomuxc {
769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_hog>;
771
772 pinctrl_audio_pwr_reg: audiopwrreggrp {
773 fsl,pins = <
774 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
775 >;
776 };
777
778 pinctrl_eqos: eqosgrp {
779 fsl,pins = <
780 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
781 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
782 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
783 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
784 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
785 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
786 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
787 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
788 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
789 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
790 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
791 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
792 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
793 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
794 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
795 >;
796 };
797
798 pinctrl_fec: fecgrp {
799 fsl,pins = <
800 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
801 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
802 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
803 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
804 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
805 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
806 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
807 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
808 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
809 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
810 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
811 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
812 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
813 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
814 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
815 >;
816 };
817
818 pinctrl_flexcan1: flexcan1grp {
819 fsl,pins = <
820 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
821 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
822 >;
823 };
824
825 pinctrl_flexcan2: flexcan2grp {
826 fsl,pins = <
827 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
828 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
829 >;
830 };
831
832 pinctrl_flexcan1_reg: flexcan1reggrp {
833 fsl,pins = <
834 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
835 >;
836 };
837
838 pinctrl_flexcan2_reg: flexcan2reggrp {
839 fsl,pins = <
840 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
841 >;
842 };
843
844 pinctrl_flexspi0: flexspi0grp {
845 fsl,pins = <
846 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
847 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
848 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
849 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
850 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
851 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
852 >;
853 };
854
855 pinctrl_gpio_led: gpioledgrp {
856 fsl,pins = <
857 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
858 >;
859 };
860
861 pinctrl_hog: hoggrp {
862 fsl,pins = <
863 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
864 >;
865 };
866
867 pinctrl_i2c1: i2c1grp {
868 fsl,pins = <
869 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
870 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
871 >;
872 };
873
874 pinctrl_i2c2: i2c2grp {
875 fsl,pins = <
876 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
877 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
878 >;
879 };
880
881 pinctrl_i2c3: i2c3grp {
882 fsl,pins = <
883 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
884 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
885 >;
886 };
887
888 pinctrl_i2c5: i2c5grp {
889 fsl,pins = <
890 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
891 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
892 >;
893 };
894
895 pinctrl_pcie0: pcie0grp {
896 fsl,pins = <
897 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
898 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
899 >;
900 };
901
902 pinctrl_pcie0_reg: pcie0reggrp {
903 fsl,pins = <
904 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
905 >;
906 };
907
908 pinctrl_pdm: pdmgrp {
909 fsl,pins = <
910 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
911 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
912 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6
913 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6
914 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
915 >;
916 };
917
918 pinctrl_pmic: pmicgrp {
919 fsl,pins = <
920 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
921 >;
922 };
923
924 pinctrl_pca6416_int: pca6416_int_grp {
925 fsl,pins = <
926 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
927 >;
928 };
929
930 pinctrl_pwm1: pwm1grp {
931 fsl,pins = <
932 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
933 >;
934 };
935
936 pinctrl_pwm2: pwm2grp {
937 fsl,pins = <
938 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
939 >;
940 };
941
942 pinctrl_pwm4: pwm4grp {
943 fsl,pins = <
944 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
945 >;
946 };
947
948 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
949 fsl,pins = <
950 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
951 >;
952 };
953
954 pinctrl_uart1: uart1grp {
955 fsl,pins = <
956 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
957 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
958 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
959 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
960 >;
961 };
962
963 pinctrl_sai2: sai2grp {
964 fsl,pins = <
965 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
966 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
967 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
968 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
969 >;
970 };
971
972 pinctrl_sai3: sai3grp {
973 fsl,pins = <
974 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
975 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
976 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
977 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
978 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
979 >;
980 };
981
982 pinctrl_uart2: uart2grp {
983 fsl,pins = <
984 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
985 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
986 >;
987 };
988
989 pinctrl_usb1_vbus: usb1grp {
990 fsl,pins = <
991 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
992 >;
993 };
994
995 pinctrl_uart3: uart3grp {
996 fsl,pins = <
997 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
998 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
999 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
1000 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
1001 >;
1002 };
1003
1004 pinctrl_usdhc2: usdhc2grp {
1005 fsl,pins = <
1006 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
1007 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
1008 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
1009 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
1010 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
1011 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
1012 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1013 >;
1014 };
1015
1016 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1017 fsl,pins = <
1018 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
1019 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
1020 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
1021 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
1022 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
1023 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
1024 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1025 >;
1026 };
1027
1028 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1029 fsl,pins = <
1030 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
1031 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
1032 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
1033 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
1034 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
1035 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
1036 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
1037 >;
1038 };
1039
1040 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
1041 fsl,pins = <
1042 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
1043 >;
1044 };
1045
1046 pinctrl_usdhc3: usdhc3grp {
1047 fsl,pins = <
1048 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1049 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1050 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1051 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1052 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1053 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1054 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1055 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1056 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1057 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1058 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1059 >;
1060 };
1061
1062 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1063 fsl,pins = <
1064 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1065 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1066 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1067 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1068 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1069 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1070 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1071 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1072 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1073 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1074 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1075 >;
1076 };
1077
1078 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1079 fsl,pins = <
1080 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1081 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1082 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1083 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1084 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1085 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1086 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1087 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1088 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1089 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1090 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1091 >;
1092 };
1093
1094 pinctrl_wdog: wdoggrp {
1095 fsl,pins = <
1096 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1097 >;
1098 };
1099 };
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