1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13
14 #include "imx8mp.dtsi"
15
16 / {
17 model = "Gateworks Venice GW74xx i.MX8MP board";
18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
19
20 aliases {
21 ethernet0 = &eqos;
22 ethernet1 = &fec;
23 ethernet2 = &lan1;
24 ethernet3 = &lan2;
25 ethernet4 = &lan3;
26 ethernet5 = &lan4;
27 ethernet6 = &lan5;
28 };
29
30 chosen {
31 stdout-path = &uart2;
32 };
33
34 memory@40000000 {
35 device_type = "memory";
36 reg = <0x0 0x40000000 0 0x80000000>;
37 };
38
39 connector {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_usbcon1>;
42 compatible = "gpio-usb-b-connector", "usb-b-connector";
43 type = "micro";
44 label = "Type-C";
45 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
46
47 port {
48 usb_dr_connector: endpoint {
49 remote-endpoint = <&usb3_dwc>;
50 };
51 };
52 };
53
54 gpio-keys {
55 compatible = "gpio-keys";
56
57 key-0 {
58 label = "user_pb";
59 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
60 linux,code = <BTN_0>;
61 };
62
63 key-1 {
64 label = "user_pb1x";
65 linux,code = <BTN_1>;
66 interrupt-parent = <&gsc>;
67 interrupts = <0>;
68 };
69
70 key-2 {
71 label = "key_erased";
72 linux,code = <BTN_2>;
73 interrupt-parent = <&gsc>;
74 interrupts = <1>;
75 };
76
77 key-3 {
78 label = "eeprom_wp";
79 linux,code = <BTN_3>;
80 interrupt-parent = <&gsc>;
81 interrupts = <2>;
82 };
83
84 key-4 {
85 label = "tamper";
86 linux,code = <BTN_4>;
87 interrupt-parent = <&gsc>;
88 interrupts = <5>;
89 };
90
91 key-5 {
92 label = "switch_hold";
93 linux,code = <BTN_5>;
94 interrupt-parent = <&gsc>;
95 interrupts = <7>;
96 };
97 };
98
99 led-controller {
100 compatible = "gpio-leds";
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpio_leds>;
103
104 led-0 {
105 function = LED_FUNCTION_HEARTBEAT;
106 color = <LED_COLOR_ID_GREEN>;
107 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
108 default-state = "on";
109 linux,default-trigger = "heartbeat";
110 };
111
112 led-1 {
113 function = LED_FUNCTION_STATUS;
114 color = <LED_COLOR_ID_RED>;
115 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
116 default-state = "off";
117 };
118 };
119
120 pcie0_refclk: pcie0-refclk {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <100000000>;
124 };
125
126 pps {
127 compatible = "pps-gpio";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_pps>;
130 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
131 };
132
133 reg_usb2_vbus: regulator-usb2 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_reg_usb2>;
136 compatible = "regulator-fixed";
137 regulator-name = "usb_usb2_vbus";
138 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
139 enable-active-high;
140 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <5000000>;
142 };
143
144 reg_can1_stby: regulator-can1-stby {
145 compatible = "regulator-fixed";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_reg_can1>;
148 regulator-name = "can1_stby";
149 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 };
153
154 reg_can2_stby: regulator-can2-stby {
155 compatible = "regulator-fixed";
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_reg_can2>;
158 regulator-name = "can2_stby";
159 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
160 regulator-min-microvolt = <3300000>;
161 regulator-max-microvolt = <3300000>;
162 };
163
164 reg_wifi_en: regulator-wifi-en {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_reg_wifi>;
167 compatible = "regulator-fixed";
168 regulator-name = "wl";
169 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
170 startup-delay-us = <70000>;
171 enable-active-high;
172 regulator-min-microvolt = <3300000>;
173 regulator-max-microvolt = <3300000>;
174 };
175 };
176
177 &A53_0 {
178 cpu-supply = <®_arm>;
179 };
180
181 &A53_1 {
182 cpu-supply = <®_arm>;
183 };
184
185 &A53_2 {
186 cpu-supply = <®_arm>;
187 };
188
189 &A53_3 {
190 cpu-supply = <®_arm>;
191 };
192
193 &ecspi1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_spi1>;
196 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
197 status = "okay";
198
199 tpm@0 {
200 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
201 reg = <0x0>;
202 spi-max-frequency = <36000000>;
203 };
204 };
205
206 /* off-board header */
207 &ecspi2 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi2>;
210 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
211 status = "okay";
212 };
213
214 &eqos {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_eqos>;
217 phy-mode = "rgmii-id";
218 phy-handle = <ðphy0>;
219 status = "okay";
220
221 mdio {
222 compatible = "snps,dwmac-mdio";
223 #address-cells = <1>;
224 #size-cells = <0>;
225
226 ethphy0: ethernet-phy@0 {
227 compatible = "ethernet-phy-ieee802.3-c22";
228 reg = <0x0>;
229 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
230 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
231 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
232 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
233
234 leds {
235 #address-cells = <1>;
236 #size-cells = <0>;
237
238 led@1 {
239 reg = <1>;
240 color = <LED_COLOR_ID_AMBER>;
241 function = LED_FUNCTION_LAN;
242 default-state = "keep";
243 };
244
245 led@2 {
246 reg = <2>;
247 color = <LED_COLOR_ID_GREEN>;
248 function = LED_FUNCTION_LAN;
249 default-state = "keep";
250 };
251 };
252 };
253 };
254 };
255
256 &fec {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_fec>;
259 phy-mode = "rgmii-id";
260 local-mac-address = [00 00 00 00 00 00];
261 status = "okay";
262
263 fixed-link {
264 speed = <1000>;
265 full-duplex;
266 };
267 };
268
269 &flexcan1 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_flexcan1>;
272 xceiver-supply = <®_can1_stby>;
273 status = "okay";
274 };
275
276 &flexcan2 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_flexcan2>;
279 xceiver-supply = <®_can2_stby>;
280 status = "okay";
281 };
282
283 &gpio1 {
284 gpio-line-names =
285 "", "", "", "", "", "", "", "",
286 "", "dio0", "", "dio1", "", "", "", "",
287 "", "", "", "", "", "", "", "",
288 "", "", "", "", "", "", "", "";
289 };
290
291 &gpio2 {
292 gpio-line-names =
293 "", "", "", "", "", "", "m2_pin20", "",
294 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
295 "", "", "pcie2_wdis#", "", "", "", "", "",
296 "", "", "", "", "", "", "", "";
297 };
298
299 &gpio3 {
300 gpio-line-names =
301 "", "", "", "", "", "", "m2_rst", "",
302 "", "", "", "", "", "", "", "",
303 "", "", "", "", "", "", "", "",
304 "", "", "", "", "", "", "", "";
305 };
306
307 &gpio4 {
308 gpio-line-names =
309 "", "", "m2_off#", "", "", "", "", "",
310 "", "", "", "", "", "", "", "",
311 "", "", "m2_wdis#", "", "", "", "", "",
312 "", "", "", "", "", "", "", "rs485_en";
313 };
314
315 &gpio5 {
316 gpio-line-names =
317 "rs485_hd", "rs485_term", "", "", "", "", "", "",
318 "", "", "", "", "", "", "", "",
319 "", "", "", "", "", "", "", "",
320 "", "", "", "", "", "", "", "";
321 };
322
323 &i2c1 {
324 clock-frequency = <100000>;
325 pinctrl-names = "default", "gpio";
326 pinctrl-0 = <&pinctrl_i2c1>;
327 pinctrl-1 = <&pinctrl_i2c1_gpio>;
328 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
329 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
330 status = "okay";
331
332 gsc: gsc@20 {
333 compatible = "gw,gsc";
334 reg = <0x20>;
335 pinctrl-0 = <&pinctrl_gsc>;
336 interrupt-parent = <&gpio4>;
337 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
338 interrupt-controller;
339 #interrupt-cells = <1>;
340 #address-cells = <1>;
341 #size-cells = <0>;
342
343 adc {
344 compatible = "gw,gsc-adc";
345 #address-cells = <1>;
346 #size-cells = <0>;
347
348 channel@6 {
349 gw,mode = <0>;
350 reg = <0x06>;
351 label = "temp";
352 };
353
354 channel@8 {
355 gw,mode = <3>;
356 reg = <0x08>;
357 label = "vdd_bat";
358 };
359
360 channel@16 {
361 gw,mode = <4>;
362 reg = <0x16>;
363 label = "fan_tach";
364 };
365
366 channel@82 {
367 gw,mode = <2>;
368 reg = <0x82>;
369 label = "vdd_adc1";
370 gw,voltage-divider-ohms = <10000 10000>;
371 };
372
373 channel@84 {
374 gw,mode = <2>;
375 reg = <0x84>;
376 label = "vdd_adc2";
377 gw,voltage-divider-ohms = <10000 10000>;
378 };
379
380 channel@86 {
381 gw,mode = <2>;
382 reg = <0x86>;
383 label = "vdd_vin";
384 gw,voltage-divider-ohms = <22100 1000>;
385 };
386
387 channel@88 {
388 gw,mode = <2>;
389 reg = <0x88>;
390 label = "vdd_3p3";
391 gw,voltage-divider-ohms = <10000 10000>;
392 };
393
394 channel@8c {
395 gw,mode = <2>;
396 reg = <0x8c>;
397 label = "vdd_2p5";
398 gw,voltage-divider-ohms = <10000 10000>;
399 };
400
401 channel@90 {
402 gw,mode = <2>;
403 reg = <0x90>;
404 label = "vdd_soc";
405 };
406
407 channel@92 {
408 gw,mode = <2>;
409 reg = <0x92>;
410 label = "vdd_arm";
411 };
412
413 channel@98 {
414 gw,mode = <2>;
415 reg = <0x98>;
416 label = "vdd_1p8";
417 };
418
419 channel@9a {
420 gw,mode = <2>;
421 reg = <0x9a>;
422 label = "vdd_1p2";
423 };
424
425 channel@9c {
426 gw,mode = <2>;
427 reg = <0x9c>;
428 label = "vdd_dram";
429 };
430
431 channel@9e {
432 gw,mode = <2>;
433 reg = <0x9e>;
434 label = "vdd_1p0";
435 };
436
437 channel@a2 {
438 gw,mode = <2>;
439 reg = <0xa2>;
440 label = "vdd_gsc";
441 gw,voltage-divider-ohms = <10000 10000>;
442 };
443 };
444
445 fan-controller@a {
446 compatible = "gw,gsc-fan";
447 reg = <0x0a>;
448 };
449 };
450
451 gpio: gpio@23 {
452 compatible = "nxp,pca9555";
453 reg = <0x23>;
454 gpio-controller;
455 #gpio-cells = <2>;
456 interrupt-parent = <&gsc>;
457 interrupts = <4>;
458 };
459
460 eeprom@50 {
461 compatible = "atmel,24c02";
462 reg = <0x50>;
463 pagesize = <16>;
464 };
465
466 eeprom@51 {
467 compatible = "atmel,24c02";
468 reg = <0x51>;
469 pagesize = <16>;
470 };
471
472 eeprom@52 {
473 compatible = "atmel,24c02";
474 reg = <0x52>;
475 pagesize = <16>;
476 };
477
478 eeprom@53 {
479 compatible = "atmel,24c02";
480 reg = <0x53>;
481 pagesize = <16>;
482 };
483
484 rtc@68 {
485 compatible = "dallas,ds1672";
486 reg = <0x68>;
487 };
488 };
489
490 &i2c2 {
491 clock-frequency = <400000>;
492 pinctrl-names = "default", "gpio";
493 pinctrl-0 = <&pinctrl_i2c2>;
494 pinctrl-1 = <&pinctrl_i2c2_gpio>;
495 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
496 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
497 status = "okay";
498
499 accelerometer@19 {
500 compatible = "st,lis2de12";
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_accel>;
503 reg = <0x19>;
504 st,drdy-int-pin = <1>;
505 interrupt-parent = <&gpio1>;
506 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
507 };
508
509 switch: switch@5f {
510 compatible = "microchip,ksz9897";
511 reg = <0x5f>;
512 pinctrl-0 = <&pinctrl_ksz>;
513 interrupt-parent = <&gpio4>;
514 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
515
516 ports {
517 #address-cells = <1>;
518 #size-cells = <0>;
519
520 lan1: port@0 {
521 reg = <0>;
522 label = "lan1";
523 phy-mode = "internal";
524 local-mac-address = [00 00 00 00 00 00];
525 };
526
527 lan2: port@1 {
528 reg = <1>;
529 label = "lan2";
530 phy-mode = "internal";
531 local-mac-address = [00 00 00 00 00 00];
532 };
533
534 lan3: port@2 {
535 reg = <2>;
536 label = "lan3";
537 phy-mode = "internal";
538 local-mac-address = [00 00 00 00 00 00];
539 };
540
541 lan4: port@3 {
542 reg = <3>;
543 label = "lan4";
544 phy-mode = "internal";
545 local-mac-address = [00 00 00 00 00 00];
546 };
547
548 lan5: port@4 {
549 reg = <4>;
550 label = "lan5";
551 phy-mode = "internal";
552 local-mac-address = [00 00 00 00 00 00];
553 };
554
555 port@5 {
556 reg = <5>;
557 ethernet = <&fec>;
558 phy-mode = "rgmii-id";
559
560 fixed-link {
561 speed = <1000>;
562 full-duplex;
563 };
564 };
565 };
566 };
567 };
568
569 &i2c3 {
570 clock-frequency = <400000>;
571 pinctrl-names = "default", "gpio";
572 pinctrl-0 = <&pinctrl_i2c3>;
573 pinctrl-1 = <&pinctrl_i2c3_gpio>;
574 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
575 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 status = "okay";
577
578 pmic@25 {
579 compatible = "nxp,pca9450c";
580 reg = <0x25>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_pmic>;
583 interrupt-parent = <&gpio3>;
584 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
585
586 regulators {
587 BUCK1 {
588 regulator-name = "BUCK1";
589 regulator-min-microvolt = <720000>;
590 regulator-max-microvolt = <1000000>;
591 regulator-boot-on;
592 regulator-always-on;
593 regulator-ramp-delay = <3125>;
594 };
595
596 reg_arm: BUCK2 {
597 regulator-name = "BUCK2";
598 regulator-min-microvolt = <720000>;
599 regulator-max-microvolt = <1025000>;
600 regulator-boot-on;
601 regulator-always-on;
602 regulator-ramp-delay = <3125>;
603 nxp,dvs-run-voltage = <950000>;
604 nxp,dvs-standby-voltage = <850000>;
605 };
606
607 BUCK4 {
608 regulator-name = "BUCK4";
609 regulator-min-microvolt = <3000000>;
610 regulator-max-microvolt = <3600000>;
611 regulator-boot-on;
612 regulator-always-on;
613 };
614
615 BUCK5 {
616 regulator-name = "BUCK5";
617 regulator-min-microvolt = <1650000>;
618 regulator-max-microvolt = <1950000>;
619 regulator-boot-on;
620 regulator-always-on;
621 };
622
623 BUCK6 {
624 regulator-name = "BUCK6";
625 regulator-min-microvolt = <1045000>;
626 regulator-max-microvolt = <1155000>;
627 regulator-boot-on;
628 regulator-always-on;
629 };
630
631 LDO1 {
632 regulator-name = "LDO1";
633 regulator-min-microvolt = <1650000>;
634 regulator-max-microvolt = <1950000>;
635 regulator-boot-on;
636 regulator-always-on;
637 };
638
639 LDO3 {
640 regulator-name = "LDO3";
641 regulator-min-microvolt = <1710000>;
642 regulator-max-microvolt = <1890000>;
643 regulator-boot-on;
644 regulator-always-on;
645 };
646
647 LDO5 {
648 regulator-name = "LDO5";
649 regulator-min-microvolt = <1800000>;
650 regulator-max-microvolt = <3300000>;
651 regulator-boot-on;
652 regulator-always-on;
653 };
654 };
655 };
656 };
657
658 /* off-board header */
659 &i2c4 {
660 clock-frequency = <400000>;
661 pinctrl-names = "default", "gpio";
662 pinctrl-0 = <&pinctrl_i2c4>;
663 pinctrl-1 = <&pinctrl_i2c4_gpio>;
664 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
665 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
666 status = "okay";
667 };
668
669 &pcie_phy {
670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
671 fsl,clkreq-unsupported;
672 clocks = <&pcie0_refclk>;
673 clock-names = "ref";
674 status = "okay";
675 };
676
677 &pcie {
678 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_pcie0>;
680 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
681 status = "okay";
682 };
683
684 /* GPS / off-board header */
685 &uart1 {
686 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_uart1>;
688 status = "okay";
689 };
690
691 /* RS232 console */
692 &uart2 {
693 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_uart2>;
695 status = "okay";
696 };
697
698 /* bluetooth HCI */
699 &uart3 {
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
702 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
703 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
704 status = "okay";
705
706 bluetooth {
707 compatible = "brcm,bcm4330-bt";
708 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
709 };
710 };
711
712 &uart4 {
713 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_uart4>;
715 status = "okay";
716 };
717
718 /* USB1 - Type C front panel */
719 &usb3_0 {
720 pinctrl-names = "default";
721 pinctrl-0 = <&pinctrl_usb1>;
722 fsl,over-current-active-low;
723 status = "okay";
724 };
725
726 &usb3_phy0 {
727 status = "okay";
728 };
729
730 &usb_dwc3_0 {
731 /* dual role is implemented but not a full featured OTG */
732 adp-disable;
733 hnp-disable;
734 srp-disable;
735 dr_mode = "otg";
736 usb-role-switch;
737 role-switch-default-mode = "peripheral";
738 status = "okay";
739
740 port {
741 usb3_dwc: endpoint {
742 remote-endpoint = <&usb_dr_connector>;
743 };
744 };
745 };
746
747 /* USB2 - USB3.0 Hub */
748 &usb3_phy1 {
749 vbus-supply = <®_usb2_vbus>;
750 status = "okay";
751 };
752
753 &usb3_1 {
754 fsl,permanently-attached;
755 fsl,disable-port-power-control;
756 status = "okay";
757 };
758
759 &usb_dwc3_1 {
760 dr_mode = "host";
761 status = "okay";
762 };
763
764 /* SDIO WiFi */
765 &usdhc1 {
766 pinctrl-names = "default", "state_100mhz", "state_200mhz";
767 pinctrl-0 = <&pinctrl_usdhc1>;
768 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
769 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
770 bus-width = <4>;
771 non-removable;
772 vmmc-supply = <®_wifi_en>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 status = "okay";
776
777 wifi@0 {
778 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
779 reg = <0>;
780 };
781 };
782
783 /* eMMC */
784 &usdhc3 {
785 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
786 assigned-clock-rates = <400000000>;
787 pinctrl-names = "default", "state_100mhz", "state_200mhz";
788 pinctrl-0 = <&pinctrl_usdhc3>;
789 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
790 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
791 bus-width = <8>;
792 non-removable;
793 status = "okay";
794 };
795
796 &wdog1 {
797 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_wdog>;
799 fsl,ext-reset-output;
800 status = "okay";
801 };
802
803 &iomuxc {
804 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_hog>;
806
807 pinctrl_hog: hoggrp {
808 fsl,pins = <
809 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
810 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
811 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
812 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
813 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
814 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
815 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
816 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
817 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
818 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
819 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
820 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
821 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
822 >;
823 };
824
825 pinctrl_accel: accelgrp {
826 fsl,pins = <
827 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
828 >;
829 };
830
831 pinctrl_eqos: eqosgrp {
832 fsl,pins = <
833 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
834 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
835 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
836 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
837 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
838 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
839 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
840 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
841 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
842 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
843 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
844 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
845 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
846 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
847 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
848 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
849 >;
850 };
851
852 pinctrl_fec: fecgrp {
853 fsl,pins = <
854 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
855 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
856 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
857 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
858 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
859 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
860 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
861 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
862 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
863 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
864 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
865 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
866 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
867 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
868 >;
869 };
870
871 pinctrl_flexcan1: flexcan1grp {
872 fsl,pins = <
873 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
874 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
875 >;
876 };
877
878 pinctrl_flexcan2: flexcan2grp {
879 fsl,pins = <
880 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
881 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
882 >;
883 };
884
885 pinctrl_gsc: gscgrp {
886 fsl,pins = <
887 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
888 >;
889 };
890
891 pinctrl_i2c1: i2c1grp {
892 fsl,pins = <
893 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
894 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
895 >;
896 };
897
898 pinctrl_i2c1_gpio: i2c1gpiogrp {
899 fsl,pins = <
900 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
901 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
902 >;
903 };
904
905 pinctrl_i2c2: i2c2grp {
906 fsl,pins = <
907 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
908 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
909 >;
910 };
911
912 pinctrl_i2c2_gpio: i2c2gpiogrp {
913 fsl,pins = <
914 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
915 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
916 >;
917 };
918
919 pinctrl_i2c3: i2c3grp {
920 fsl,pins = <
921 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
922 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
923 >;
924 };
925
926 pinctrl_i2c3_gpio: i2c3gpiogrp {
927 fsl,pins = <
928 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
929 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
930 >;
931 };
932
933 pinctrl_i2c4: i2c4grp {
934 fsl,pins = <
935 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
936 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
937 >;
938 };
939
940 pinctrl_i2c4_gpio: i2c4gpiogrp {
941 fsl,pins = <
942 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
943 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
944 >;
945 };
946
947 pinctrl_ksz: kszgrp {
948 fsl,pins = <
949 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
950 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
951 >;
952 };
953
954 pinctrl_gpio_leds: ledgrp {
955 fsl,pins = <
956 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
957 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
958 >;
959 };
960
961 pinctrl_pcie0: pciegrp {
962 fsl,pins = <
963 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
964 >;
965 };
966
967 pinctrl_pmic: pmicgrp {
968 fsl,pins = <
969 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
970 >;
971 };
972
973 pinctrl_pps: ppsgrp {
974 fsl,pins = <
975 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
976 >;
977 };
978
979 pinctrl_reg_can1: regcan1grp {
980 fsl,pins = <
981 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
982 >;
983 };
984
985 pinctrl_reg_can2: regcan2grp {
986 fsl,pins = <
987 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
988 >;
989 };
990
991 pinctrl_reg_usb2: regusb2grp {
992 fsl,pins = <
993 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
994 >;
995 };
996
997 pinctrl_reg_wifi: regwifigrp {
998 fsl,pins = <
999 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
1000 >;
1001 };
1002
1003 pinctrl_spi1: spi1grp {
1004 fsl,pins = <
1005 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
1006 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
1007 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
1008 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
1009 >;
1010 };
1011
1012 pinctrl_spi2: spi2grp {
1013 fsl,pins = <
1014 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
1015 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
1016 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
1017 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
1018 >;
1019 };
1020
1021 pinctrl_uart1: uart1grp {
1022 fsl,pins = <
1023 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
1024 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
1025 >;
1026 };
1027
1028 pinctrl_uart2: uart2grp {
1029 fsl,pins = <
1030 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
1031 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
1032 >;
1033 };
1034
1035 pinctrl_uart3: uart3grp {
1036 fsl,pins = <
1037 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
1038 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
1039 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1040 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1041 >;
1042 };
1043
1044 pinctrl_uart3_gpio: uart3gpiogrp {
1045 fsl,pins = <
1046 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1047 >;
1048 };
1049
1050 pinctrl_uart4: uart4grp {
1051 fsl,pins = <
1052 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1053 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1054 >;
1055 };
1056
1057 pinctrl_usb1: usb1grp {
1058 fsl,pins = <
1059 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1060 >;
1061 };
1062
1063 pinctrl_usbcon1: usb1congrp {
1064 fsl,pins = <
1065 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
1066 >;
1067 };
1068
1069 pinctrl_usdhc1: usdhc1grp {
1070 fsl,pins = <
1071 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1072 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1073 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1074 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1075 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1076 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1077 >;
1078 };
1079
1080 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1081 fsl,pins = <
1082 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1083 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1084 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1085 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1086 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1087 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1088 >;
1089 };
1090
1091 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1092 fsl,pins = <
1093 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1094 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1095 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1096 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1097 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1098 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1099 >;
1100 };
1101
1102 pinctrl_usdhc3: usdhc3grp {
1103 fsl,pins = <
1104 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1105 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1106 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1107 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1108 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1109 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1110 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1111 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1112 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1113 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1114 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1115 >;
1116 };
1117
1118 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1119 fsl,pins = <
1120 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1121 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1122 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1123 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1124 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1125 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1126 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1127 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1128 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1129 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1130 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1131 >;
1132 };
1133
1134 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1135 fsl,pins = <
1136 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1137 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1138 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1139 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1140 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1141 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1142 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1143 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1144 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1145 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1146 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1147 >;
1148 };
1149
1150 pinctrl_wdog: wdoggrp {
1151 fsl,pins = <
1152 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1153 >;
1154 };
1155 };
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