1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7 /dts-v1/;
8
9 #include "imx8mq.dtsi"
10
11 / {
12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 0xc0000000>;
22 };
23
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
28 };
29
30 reg_pcie1: regulator-pcie {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_pcie1_reg>;
34 regulator-name = "MPCIE_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40
41 reg_usdhc2_vmmc: regulator-vsd-3v3 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_reg_usdhc2>;
44 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 off-on-delay-us = <20000>;
50 enable-active-high;
51 };
52
53 buck2_reg: regulator-buck2 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_buck2>;
56 compatible = "regulator-gpio";
57 regulator-name = "vdd_arm";
58 regulator-min-microvolt = <900000>;
59 regulator-max-microvolt = <1000000>;
60 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
61 states = <1000000 0x0
62 900000 0x1>;
63 regulator-boot-on;
64 regulator-always-on;
65 };
66
67 ir-receiver {
68 compatible = "gpio-ir-receiver";
69 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ir>;
72 linux,autosuspend-period = <125>;
73 };
74
75 audio_codec_bt_sco: audio-codec-bt-sco {
76 compatible = "linux,bt-sco";
77 #sound-dai-cells = <1>;
78 };
79
80 wm8524: audio-codec {
81 #sound-dai-cells = <0>;
82 compatible = "wlf,wm8524";
83 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
84 };
85
86 sound-bt-sco {
87 compatible = "simple-audio-card";
88 simple-audio-card,name = "bt-sco-audio";
89 simple-audio-card,format = "dsp_a";
90 simple-audio-card,bitclock-inversion;
91 simple-audio-card,frame-master = <&btcpu>;
92 simple-audio-card,bitclock-master = <&btcpu>;
93
94 btcpu: simple-audio-card,cpu {
95 sound-dai = <&sai3>;
96 dai-tdm-slot-num = <2>;
97 dai-tdm-slot-width = <16>;
98 };
99
100 simple-audio-card,codec {
101 sound-dai = <&audio_codec_bt_sco 1>;
102 };
103 };
104
105 sound-wm8524 {
106 compatible = "simple-audio-card";
107 simple-audio-card,name = "wm8524-audio";
108 simple-audio-card,format = "i2s";
109 simple-audio-card,frame-master = <&cpudai>;
110 simple-audio-card,bitclock-master = <&cpudai>;
111 simple-audio-card,widgets =
112 "Line", "Left Line Out Jack",
113 "Line", "Right Line Out Jack";
114 simple-audio-card,routing =
115 "Left Line Out Jack", "LINEVOUTL",
116 "Right Line Out Jack", "LINEVOUTR";
117
118 cpudai: simple-audio-card,cpu {
119 sound-dai = <&sai2>;
120 };
121
122 link_codec: simple-audio-card,codec {
123 sound-dai = <&wm8524>;
124 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
125 };
126 };
127
128 spdif_out: spdif-out {
129 compatible = "linux,spdif-dit";
130 #sound-dai-cells = <0>;
131 };
132
133 spdif_in: spdif-in {
134 compatible = "linux,spdif-dir";
135 #sound-dai-cells = <0>;
136 };
137
138 sound-spdif {
139 compatible = "fsl,imx-audio-spdif";
140 model = "imx-spdif";
141 audio-cpu = <&spdif1>;
142 audio-codec = <&spdif_out>, <&spdif_in>;
143 };
144
145 hdmi_arc_in: hdmi-arc-in {
146 compatible = "linux,spdif-dir";
147 #sound-dai-cells = <0>;
148 };
149
150 sound-hdmi-arc {
151 compatible = "fsl,imx-audio-spdif";
152 model = "imx-hdmi-arc";
153 audio-cpu = <&spdif2>;
154 audio-codec = <&hdmi_arc_in>;
155 };
156 };
157
158 &A53_0 {
159 cpu-supply = <&buck2_reg>;
160 };
161
162 &A53_1 {
163 cpu-supply = <&buck2_reg>;
164 };
165
166 &A53_2 {
167 cpu-supply = <&buck2_reg>;
168 };
169
170 &A53_3 {
171 cpu-supply = <&buck2_reg>;
172 };
173
174 &ddrc {
175 operating-points-v2 = <&ddrc_opp_table>;
176 status = "okay";
177
178 ddrc_opp_table: opp-table {
179 compatible = "operating-points-v2";
180
181 opp-25000000 {
182 opp-hz = /bits/ 64 <25000000>;
183 };
184
185 opp-100000000 {
186 opp-hz = /bits/ 64 <100000000>;
187 };
188
189 /*
190 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
191 */
192 opp-166000000 {
193 opp-hz = /bits/ 64 <166935483>;
194 };
195
196 opp-800000000 {
197 opp-hz = /bits/ 64 <800000000>;
198 };
199 };
200 };
201
202 &dphy {
203 status = "okay";
204 };
205
206 &fec1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_fec1>;
209 phy-mode = "rgmii-id";
210 phy-handle = <ðphy0>;
211 fsl,magic-packet;
212 status = "okay";
213
214 mdio {
215 #address-cells = <1>;
216 #size-cells = <0>;
217
218 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet-phy-ieee802.3-c22";
220 reg = <0>;
221 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
222 reset-assert-us = <10000>;
223 qca,disable-smarteee;
224 vddio-supply = <&vddh>;
225
226 vddh: vddh-regulator {
227 };
228 };
229 };
230 };
231
232 &gpio5 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_wifi_reset>;
235
236 wl-reg-on-hog {
237 gpio-hog;
238 gpios = <29 GPIO_ACTIVE_HIGH>;
239 output-high;
240 };
241 };
242
243 &i2c1 {
244 clock-frequency = <100000>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c1>;
247 status = "okay";
248
249 pmic@8 {
250 compatible = "fsl,pfuze100";
251 reg = <0x8>;
252
253 regulators {
254 sw1a_reg: sw1ab {
255 regulator-min-microvolt = <825000>;
256 regulator-max-microvolt = <1100000>;
257 };
258
259 sw1c_reg: sw1c {
260 regulator-min-microvolt = <825000>;
261 regulator-max-microvolt = <1100000>;
262 };
263
264 sw2_reg: sw2 {
265 regulator-min-microvolt = <1100000>;
266 regulator-max-microvolt = <1100000>;
267 regulator-always-on;
268 };
269
270 sw3a_reg: sw3ab {
271 regulator-min-microvolt = <825000>;
272 regulator-max-microvolt = <1100000>;
273 regulator-always-on;
274 };
275
276 sw4_reg: sw4 {
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <1800000>;
279 regulator-always-on;
280 };
281
282 swbst_reg: swbst {
283 regulator-min-microvolt = <5000000>;
284 regulator-max-microvolt = <5150000>;
285 };
286
287 snvs_reg: vsnvs {
288 regulator-min-microvolt = <1000000>;
289 regulator-max-microvolt = <3000000>;
290 regulator-always-on;
291 };
292
293 vref_reg: vrefddr {
294 regulator-always-on;
295 };
296
297 vgen1_reg: vgen1 {
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1550000>;
300 };
301
302 vgen2_reg: vgen2 {
303 regulator-min-microvolt = <850000>;
304 regulator-max-microvolt = <975000>;
305 regulator-always-on;
306 };
307
308 vgen3_reg: vgen3 {
309 regulator-min-microvolt = <1675000>;
310 regulator-max-microvolt = <1975000>;
311 regulator-always-on;
312 };
313
314 vgen4_reg: vgen4 {
315 regulator-min-microvolt = <1625000>;
316 regulator-max-microvolt = <1875000>;
317 regulator-always-on;
318 };
319
320 vgen5_reg: vgen5 {
321 regulator-min-microvolt = <3075000>;
322 regulator-max-microvolt = <3625000>;
323 regulator-always-on;
324 };
325
326 vgen6_reg: vgen6 {
327 regulator-min-microvolt = <1800000>;
328 regulator-max-microvolt = <3300000>;
329 };
330 };
331 };
332 };
333
334 &lcdif {
335 status = "okay";
336 };
337
338 &mipi_dsi {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "okay";
342
343 panel@0 {
344 pinctrl-0 = <&pinctrl_mipi_dsi>;
345 pinctrl-names = "default";
346 compatible = "raydium,rm67191";
347 reg = <0>;
348 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
349 dsi-lanes = <4>;
350
351 port {
352 panel_in: endpoint {
353 remote-endpoint = <&mipi_dsi_out>;
354 };
355 };
356 };
357
358 ports {
359 port@1 {
360 reg = <1>;
361 mipi_dsi_out: endpoint {
362 remote-endpoint = <&panel_in>;
363 };
364 };
365 };
366 };
367
368 &pcie0 {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_pcie0>;
371 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
372 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
373 <&pcie0_refclk>,
374 <&clk IMX8MQ_CLK_PCIE1_PHY>,
375 <&clk IMX8MQ_CLK_PCIE1_AUX>;
376 vph-supply = <&vgen5_reg>;
377 status = "okay";
378 };
379
380 &pcie1 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_pcie1>;
383 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
384 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
385 <&pcie0_refclk>,
386 <&clk IMX8MQ_CLK_PCIE2_PHY>,
387 <&clk IMX8MQ_CLK_PCIE2_AUX>;
388 vpcie-supply = <®_pcie1>;
389 vph-supply = <&vgen5_reg>;
390 status = "okay";
391 };
392
393 &pgc_gpu {
394 power-supply = <&sw1a_reg>;
395 };
396
397 &pgc_vpu {
398 power-supply = <&sw1c_reg>;
399 };
400
401 &qspi0 {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_qspi>;
404 status = "okay";
405
406 n25q256a: flash@0 {
407 reg = <0>;
408 #address-cells = <1>;
409 #size-cells = <1>;
410 compatible = "micron,n25q256a", "jedec,spi-nor";
411 spi-max-frequency = <29000000>;
412 spi-tx-bus-width = <1>;
413 spi-rx-bus-width = <4>;
414 };
415 };
416
417 &sai2 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_sai2>;
420 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
421 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
422 assigned-clock-rates = <0>, <24576000>;
423 status = "okay";
424 };
425
426 &sai3 {
427 #sound-dai-cells = <0>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_sai3>;
430 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
431 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
432 assigned-clock-rates = <24576000>;
433 status = "okay";
434 };
435
436 &snvs_pwrkey {
437 status = "okay";
438 };
439
440 &spdif1 {
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_spdif1>;
443 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
444 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
445 assigned-clock-rates = <24576000>;
446 status = "okay";
447 };
448
449 &spdif2 {
450 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
451 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
452 assigned-clock-rates = <24576000>;
453 status = "okay";
454 };
455
456 &uart1 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_uart1>;
459 status = "okay";
460 };
461
462 &usb3_phy1 {
463 status = "okay";
464 };
465
466 &usb_dwc3_1 {
467 dr_mode = "host";
468 status = "okay";
469 };
470
471 &usdhc1 {
472 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
473 assigned-clock-rates = <400000000>;
474 pinctrl-names = "default", "state_100mhz", "state_200mhz";
475 pinctrl-0 = <&pinctrl_usdhc1>;
476 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
477 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
478 vqmmc-supply = <&sw4_reg>;
479 bus-width = <8>;
480 non-removable;
481 no-sd;
482 no-sdio;
483 status = "okay";
484 };
485
486 &usdhc2 {
487 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
488 assigned-clock-rates = <200000000>;
489 pinctrl-names = "default", "state_100mhz", "state_200mhz";
490 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
491 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
492 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
493 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
494 vmmc-supply = <®_usdhc2_vmmc>;
495 status = "okay";
496 };
497
498 &wdog1 {
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_wdog>;
501 fsl,ext-reset-output;
502 status = "okay";
503 };
504
505 &iomuxc {
506 pinctrl_buck2: vddarmgrp {
507 fsl,pins = <
508 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
509 >;
510 };
511
512 pinctrl_fec1: fec1grp {
513 fsl,pins = <
514 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
516 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
517 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
518 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
519 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
520 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
521 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
522 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
523 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
524 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
525 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
526 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
527 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
529 >;
530 };
531
532 pinctrl_i2c1: i2c1grp {
533 fsl,pins = <
534 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
535 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
536 >;
537 };
538
539 pinctrl_ir: irgrp {
540 fsl,pins = <
541 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
542 >;
543 };
544
545 pinctrl_mipi_dsi: mipidsigrp {
546 fsl,pins = <
547 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
548 >;
549 };
550
551 pinctrl_pcie0: pcie0grp {
552 fsl,pins = <
553 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
554 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
555 >;
556 };
557
558 pinctrl_pcie1: pcie1grp {
559 fsl,pins = <
560 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
561 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
562 >;
563 };
564
565 pinctrl_pcie1_reg: pcie1reggrp {
566 fsl,pins = <
567 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
568 >;
569 };
570
571 pinctrl_qspi: qspigrp {
572 fsl,pins = <
573 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
574 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
575 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
576 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
577 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
578 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
579 >;
580 };
581
582 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
583 fsl,pins = <
584 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
585 >;
586 };
587
588 pinctrl_sai2: sai2grp {
589 fsl,pins = <
590 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
591 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
592 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
593 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
594 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
595 >;
596 };
597
598 pinctrl_sai3: sai3grp {
599 fsl,pins = <
600 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
601 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
602 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
603 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
604 >;
605 };
606
607 pinctrl_spdif1: spdif1grp {
608 fsl,pins = <
609 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
610 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
611 >;
612 };
613
614 pinctrl_uart1: uart1grp {
615 fsl,pins = <
616 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
617 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
618 >;
619 };
620
621 pinctrl_usdhc1: usdhc1grp {
622 fsl,pins = <
623 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
624 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
625 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
626 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
627 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
628 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
629 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
630 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
631 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
632 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
633 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
634 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
635 >;
636 };
637
638 pinctrl_usdhc1_100mhz: usdhc1-100grp {
639 fsl,pins = <
640 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
641 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
642 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
643 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
644 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
645 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
646 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
647 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
648 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
649 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
650 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
651 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
652 >;
653 };
654
655 pinctrl_usdhc1_200mhz: usdhc1-200grp {
656 fsl,pins = <
657 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
658 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
659 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
660 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
661 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
662 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
663 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
664 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
665 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
666 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
667 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
668 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
669 >;
670 };
671
672 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
673 fsl,pins = <
674 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
675 >;
676 };
677
678 pinctrl_usdhc2: usdhc2grp {
679 fsl,pins = <
680 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
681 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
682 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
683 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
684 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
685 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
686 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
687 >;
688 };
689
690 pinctrl_usdhc2_100mhz: usdhc2-100grp {
691 fsl,pins = <
692 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
693 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
694 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
695 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
696 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
697 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
698 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
699 >;
700 };
701
702 pinctrl_usdhc2_200mhz: usdhc2-200grp {
703 fsl,pins = <
704 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
705 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
706 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
707 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
708 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
709 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
710 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
711 >;
712 };
713
714 pinctrl_wdog: wdog1grp {
715 fsl,pins = <
716 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
717 >;
718 };
719
720 pinctrl_wifi_reset: wifiresetgrp {
721 fsl,pins = <
722 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
723 >;
724 };
725 };
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