1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6 #include "imx8mq.dtsi"
7
8 / {
9 aliases {
10 mdio-gpio0 = &mdio0;
11 rtc0 = &ds1341;
12 };
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 mdio0: mdio {
19 compatible = "virtual,mdio-gpio";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23 <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 phy0: ethernet-phy@0 {
28 reg = <0>;
29 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
30 };
31 };
32
33 pcie0_refclk: clock-pcie0-refclk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <100000000>;
37 };
38
39 pcie1_refclk: clock-pcie1-refclk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <100000000>;
43 };
44
45 reg_12p0_main: regulator-12p0-main {
46 compatible = "regulator-fixed";
47 regulator-name = "12V_MAIN";
48 regulator-min-microvolt = <12000000>;
49 regulator-max-microvolt = <12000000>;
50 regulator-always-on;
51 };
52
53 reg_5p0_main: regulator-5p0-main {
54 compatible = "regulator-fixed";
55 vin-supply = <®_12p0_main>;
56 regulator-name = "5V_MAIN";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 regulator-always-on;
60 };
61
62 reg_3p3_main: regulator-3p3-main {
63 compatible = "regulator-fixed";
64 vin-supply = <®_12p0_main>;
65 regulator-name = "3V3_MAIN";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 regulator-always-on;
69 };
70
71 reg_gen_3p3: regulator-gen-3p3 {
72 compatible = "regulator-fixed";
73 vin-supply = <®_3p3_main>;
74 regulator-name = "GEN_3V3";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
77 regulator-always-on;
78 };
79
80 reg_usdhc2_vmmc: regulator-vsd-3v3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_reg_usdhc2>;
83 compatible = "regulator-fixed";
84 vin-supply = <®_gen_3p3>;
85 regulator-name = "3V3_SD";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
89 enable-active-high;
90 };
91
92 reg_arm: regulator-arm {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_reg_arm>;
95 compatible = "regulator-gpio";
96 vin-supply = <®_12p0_main>;
97 regulator-name = "0V9_ARM";
98 regulator-min-microvolt = <900000>;
99 regulator-max-microvolt = <1000000>;
100 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
101 states = <1000000 0x1
102 900000 0x0>;
103 regulator-always-on;
104 };
105
106 cs2000_ref: cs2000-ref {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <24576000>;
110 };
111
112 cs2000_in_dummy: cs2000-in-dummy {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 };
117 };
118
119 &A53_0 {
120 cpu-supply = <®_arm>;
121 };
122
123 &A53_1 {
124 cpu-supply = <®_arm>;
125 };
126
127 &A53_2 {
128 cpu-supply = <®_arm>;
129 };
130
131 &A53_3 {
132 cpu-supply = <®_arm>;
133 };
134
135 &fec1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_fec1>;
138
139 phy-handle = <&phy0>;
140 phy-mode = "rmii";
141 status = "okay";
142
143 mdio {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 clock-frequency = <12500000>;
147 suppress-preamble;
148 status = "okay";
149
150 switch: switch@0 {
151 compatible = "marvell,mv88e6085";
152 pinctrl-0 = <&pinctrl_switch_irq>;
153 pinctrl-names = "default";
154 reg = <0>;
155 dsa,member = <0 0>;
156 eeprom-length = <512>;
157 interrupt-parent = <&gpio1>;
158 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
161
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 port@0 {
167 reg = <0>;
168 label = "gigabit_proc";
169 phy-handle = <&switchphy0>;
170 };
171
172 port@1 {
173 reg = <1>;
174 label = "netaux";
175 phy-handle = <&switchphy1>;
176 };
177
178 port@2 {
179 reg = <2>;
180 phy-mode = "rev-rmii";
181 ethernet = <&fec1>;
182
183 fixed-link {
184 speed = <100>;
185 full-duplex;
186 };
187 };
188
189 port@3 {
190 reg = <3>;
191 label = "netright";
192 phy-handle = <&switchphy3>;
193 };
194
195 port@4 {
196 reg = <4>;
197 label = "netleft";
198 phy-handle = <&switchphy4>;
199 };
200 };
201
202 mdio {
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 switchphy0: switchphy@0 {
207 reg = <0>;
208 interrupt-parent = <&switch>;
209 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
210 };
211
212 switchphy1: switchphy@1 {
213 reg = <1>;
214 interrupt-parent = <&switch>;
215 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
216 };
217
218 switchphy2: switchphy@2 {
219 reg = <2>;
220 interrupt-parent = <&switch>;
221 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
222 };
223
224 switchphy3: switchphy@3 {
225 reg = <3>;
226 interrupt-parent = <&switch>;
227 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
228 };
229
230 switchphy4: switchphy@4 {
231 reg = <4>;
232 interrupt-parent = <&switch>;
233 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
234 };
235 };
236 };
237 };
238 };
239
240 &gpio3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_gpio3_hog>;
243
244 usb-emulation-hog {
245 gpio-hog;
246 gpios = <10 GPIO_ACTIVE_HIGH>;
247 output-low;
248 line-name = "usb-emulation";
249 };
250
251 usb-mode1-hog {
252 gpio-hog;
253 gpios = <11 GPIO_ACTIVE_HIGH>;
254 output-high;
255 line-name = "usb-mode1";
256 };
257
258 usb-pwr-hog {
259 gpio-hog;
260 gpios = <12 GPIO_ACTIVE_LOW>;
261 output-high;
262 line-name = "usb-pwr-ctrl-en-n";
263 };
264
265 usb-mode2-hog {
266 gpio-hog;
267 gpios = <13 GPIO_ACTIVE_HIGH>;
268 output-high;
269 line-name = "usb-mode2";
270 };
271 };
272
273 &i2c1 {
274 clock-frequency = <400000>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_i2c1>;
277 status = "okay";
278
279 accelerometer@1c {
280 compatible = "fsl,mma8451";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_accel>;
283 reg = <0x1c>;
284 interrupt-parent = <&gpio3>;
285 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
286 interrupt-names = "INT2";
287 vdd-supply = <®_gen_3p3>;
288 vddio-supply = <®_gen_3p3>;
289 };
290
291 ucs1002: charger@32 {
292 compatible = "microchip,ucs1002";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_ucs1002>;
295 reg = <0x32>;
296 interrupt-parent = <&gpio3>;
297 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
298 <18 IRQ_TYPE_EDGE_FALLING>;
299 interrupt-names = "a_det", "alert";
300 };
301
302 hpa2: amp@60 {
303 compatible = "ti,tpa6130a2";
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_tpa2>;
306 reg = <0x60>;
307 power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
308 Vdd-supply = <®_5p0_main>;
309 sound-name-prefix = "HPA2";
310 };
311 };
312
313 &i2c2 {
314 clock-frequency = <400000>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c2>;
317 status = "okay";
318
319 pmic@8 {
320 compatible = "fsl,pfuze100";
321 reg = <0x8>;
322
323 regulators {
324 sw1a_reg: sw1ab {
325 regulator-min-microvolt = <825000>;
326 regulator-max-microvolt = <1100000>;
327 };
328
329 sw1c_reg: sw1c {
330 regulator-min-microvolt = <825000>;
331 regulator-max-microvolt = <1100000>;
332 };
333
334 sw2_reg: sw2 {
335 regulator-min-microvolt = <1100000>;
336 regulator-max-microvolt = <1100000>;
337 regulator-always-on;
338 };
339
340 sw3a_reg: sw3ab {
341 regulator-min-microvolt = <825000>;
342 regulator-max-microvolt = <1100000>;
343 regulator-always-on;
344 };
345
346 sw4_reg: sw4 {
347 regulator-min-microvolt = <1800000>;
348 regulator-max-microvolt = <1800000>;
349 regulator-always-on;
350 };
351
352 swbst_reg: swbst {
353 regulator-min-microvolt = <5000000>;
354 regulator-max-microvolt = <5150000>;
355 };
356
357 snvs_reg: vsnvs {
358 regulator-min-microvolt = <1000000>;
359 regulator-max-microvolt = <3000000>;
360 regulator-always-on;
361 };
362
363 vref_reg: vrefddr {
364 regulator-always-on;
365 };
366
367 vgen1_reg: vgen1 {
368 regulator-min-microvolt = <800000>;
369 regulator-max-microvolt = <1550000>;
370 };
371
372 vgen2_reg: vgen2 {
373 regulator-min-microvolt = <850000>;
374 regulator-max-microvolt = <975000>;
375 regulator-always-on;
376 };
377
378 vgen3_reg: vgen3 {
379 regulator-min-microvolt = <1675000>;
380 regulator-max-microvolt = <1975000>;
381 regulator-always-on;
382 };
383
384 vgen4_reg: vgen4 {
385 regulator-min-microvolt = <1625000>;
386 regulator-max-microvolt = <1875000>;
387 regulator-always-on;
388 };
389
390 vgen5_reg: vgen5 {
391 regulator-min-microvolt = <3075000>;
392 regulator-max-microvolt = <3625000>;
393 regulator-always-on;
394 };
395
396 vgen6_reg: vgen6 {
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <3300000>;
399 };
400 };
401 };
402
403 codec1: codec@18 {
404 compatible = "ti,tlv320dac3100";
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_codec1>;
407 reg = <0x18>;
408 #sound-dai-cells = <0>;
409 HPVDD-supply = <®_gen_3p3>;
410 SPRVDD-supply = <®_gen_3p3>;
411 SPLVDD-supply = <®_gen_3p3>;
412 AVDD-supply = <®_gen_3p3>;
413 IOVDD-supply = <®_gen_3p3>;
414 DVDD-supply = <&vgen4_reg>;
415 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
416 };
417
418 eeprom@54 {
419 compatible = "atmel,24c128";
420 reg = <0x54>;
421 };
422
423 hpa1: amp@60 {
424 compatible = "ti,tpa6130a2";
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_tpa1>;
427 reg = <0x60>;
428 power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
429 Vdd-supply = <®_5p0_main>;
430 sound-name-prefix = "HPA1";
431 };
432
433 ds1341: rtc@68 {
434 compatible = "dallas,ds1341";
435 reg = <0x68>;
436 };
437 };
438
439 &i2c3 {
440 clock-frequency = <100000>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_i2c3>;
443 status = "okay";
444
445 usbhub: usbhub@2c {
446 compatible = "microchip,usb2513b";
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_usbhub>;
449 reg = <0x2c>;
450 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
451 };
452
453 watchdog@38 {
454 compatible = "zii,rave-wdt";
455 reg = <0x38>;
456 };
457
458 cs2000: clkgen@4e {
459 compatible = "cirrus,cs2000-cp";
460 reg = <0x4e>;
461 #clock-cells = <0>;
462 clock-names = "clk_in", "ref_clk";
463 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
464 assigned-clocks = <&cs2000>;
465 assigned-clock-rates = <24000000>;
466 };
467 };
468
469 &i2c4 {
470 clock-frequency = <400000>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_i2c4>;
473 status = "okay";
474 };
475
476 &sai2 {
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_sai2>;
479 status = "okay";
480 };
481
482 &uart1 {
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_uart1>;
485 status = "okay";
486 };
487
488 &uart2 {
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_uart2>;
491 status = "okay";
492
493 mcu {
494 compatible = "zii,rave-sp-rdu2";
495 current-speed = <1000000>;
496 #address-cells = <1>;
497 #size-cells = <1>;
498
499 watchdog {
500 compatible = "zii,rave-sp-watchdog";
501 };
502
503 backlight {
504 compatible = "zii,rave-sp-backlight";
505 };
506
507 pwrbutton {
508 compatible = "zii,rave-sp-pwrbutton";
509 };
510
511 eeprom@a3 {
512 compatible = "zii,rave-sp-eeprom";
513 reg = <0xa3 0x4000>;
514 zii,eeprom-name = "dds-eeprom";
515 };
516
517 eeprom@a4 {
518 compatible = "zii,rave-sp-eeprom";
519 reg = <0xa4 0x4000>;
520 #address-cells = <1>;
521 #size-cells = <1>;
522 zii,eeprom-name = "main-eeprom";
523 };
524 };
525 };
526
527 &usb3_phy0 {
528 vbus-supply = <&ucs1002>;
529 status = "okay";
530 };
531
532 &usb_dwc3_0 {
533 dr_mode = "host";
534 maximum-speed = "high-speed";
535 status = "okay";
536 };
537
538 &usb3_phy1 {
539 vbus-supply = <®_5p0_main>;
540 status = "okay";
541 };
542
543 &usb_dwc3_1 {
544 dr_mode = "host";
545 maximum-speed = "high-speed";
546 status = "okay";
547 };
548
549 &pcie0 {
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_pcie0>;
552 reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
553 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
554 <&pcie0_refclk>,
555 <&clk IMX8MQ_CLK_PCIE1_PHY>,
556 <&clk IMX8MQ_CLK_PCIE1_AUX>;
557 vph-supply = <&vgen5_reg>;
558 status = "okay";
559 };
560
561 &pcie1 {
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_pcie1>;
564 reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
565 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
566 <&pcie1_refclk>,
567 <&clk IMX8MQ_CLK_PCIE2_PHY>,
568 <&clk IMX8MQ_CLK_PCIE2_AUX>;
569 vph-supply = <&vgen5_reg>;
570 status = "okay";
571 };
572
573 &pgc_gpu {
574 power-supply = <&sw1a_reg>;
575 };
576
577 &pgc_vpu {
578 power-supply = <&sw1c_reg>;
579 };
580
581 &usdhc1 {
582 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
583 assigned-clock-rates = <400000000>;
584 pinctrl-names = "default", "state_100mhz", "state_200mhz";
585 pinctrl-0 = <&pinctrl_usdhc1>;
586 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
587 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
588 vqmmc-supply = <&sw4_reg>;
589 bus-width = <8>;
590 non-removable;
591 no-sd;
592 no-sdio;
593 status = "okay";
594 };
595
596 &usdhc2 {
597 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
598 assigned-clock-rates = <200000000>;
599 pinctrl-names = "default", "state_100mhz", "state_200mhz";
600 pinctrl-0 = <&pinctrl_usdhc2>;
601 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
602 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
603 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
604 vmmc-supply = <®_usdhc2_vmmc>;
605 status = "okay";
606 };
607
608 &snvs_rtc {
609 status = "disabled";
610 };
611
612 &iomuxc {
613 pinctrl_accel: accelgrp {
614 fsl,pins = <
615 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
616 >;
617 };
618
619 pinctrl_codec1: dac1grp {
620 fsl,pins = <
621 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41
622 >;
623 };
624
625 pinctrl_fec1: fec1grp {
626 fsl,pins = <
627 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
628 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
629 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
630 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
631 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
632 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
633 MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
634 MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
635 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
636 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
637 >;
638 };
639
640 pinctrl_fec1_phy_reset: fec1phyresetgrp {
641 fsl,pins = <
642 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
643 >;
644 };
645
646 pinctrl_gpio3_hog: gpio3hoggrp {
647 fsl,pins = <
648 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
649 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
650 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
651 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
652 >;
653 };
654
655 pinctrl_i2c1: i2c1grp {
656 fsl,pins = <
657 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
658 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000a2
659 >;
660 };
661
662 pinctrl_i2c2: i2c2grp {
663 fsl,pins = <
664 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000022
665 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000a2
666 >;
667 };
668
669 pinctrl_i2c3: i2c3grp {
670 fsl,pins = <
671 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
672 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000a2
673 >;
674 };
675
676 pinctrl_i2c4: i2c4grp {
677 fsl,pins = <
678 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
679 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000a2
680 >;
681 };
682
683 pinctrl_mdio_bitbang: bitbangmdiogrp {
684 fsl,pins = <
685 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
686 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
687 >;
688 };
689
690 pinctrl_pcie0: pcie0grp {
691 fsl,pins = <
692 MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
693 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
694 >;
695 };
696
697 pinctrl_pcie1: pcie1grp {
698 fsl,pins = <
699 MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
700 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
701 >;
702 };
703
704 pinctrl_reg_arm: regarmgrp {
705 fsl,pins = <
706 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
707 >;
708 };
709
710 pinctrl_reg_usdhc2: regusdhc2grp {
711 fsl,pins = <
712 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
713 >;
714 };
715
716 pinctrl_sai2: sai2grp {
717 fsl,pins = <
718 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
719 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
720 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
721 >;
722 };
723
724 pinctrl_switch_irq: switchgrp {
725 fsl,pins = <
726 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
727 >;
728 };
729
730 pinctrl_tpa1: tpa6130-1grp {
731 fsl,pins = <
732 MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x41
733 >;
734 };
735
736 pinctrl_tpa2: tpa6130-2grp {
737 fsl,pins = <
738 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
739 >;
740 };
741
742 pinctrl_ts: tsgrp {
743 fsl,pins = <
744 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
745 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
746 >;
747 };
748
749 pinctrl_uart1: uart1grp {
750 fsl,pins = <
751 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
752 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
753 >;
754 };
755
756 pinctrl_uart2: uart2grp {
757 fsl,pins = <
758 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
759 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
760 >;
761 };
762
763 pinctrl_ucs1002: ucs1002grp {
764 fsl,pins = <
765 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41
766 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41
767 >;
768 };
769
770 pinctrl_usbhub: usbhubgrp {
771 fsl,pins = <
772 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
773 >;
774 };
775
776 pinctrl_usdhc1: usdhc1grp {
777 fsl,pins = <
778 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
779 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
780 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
781 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
782 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
783 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
784 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
785 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
786 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
787 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
788 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
789 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
790 >;
791 };
792
793 pinctrl_usdhc1_100mhz: usdhc1-100grp {
794 fsl,pins = <
795 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
796 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
797 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
798 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
799 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
800 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
801 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
802 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
803 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
804 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
805 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
806 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
807 >;
808 };
809
810 pinctrl_usdhc1_200mhz: usdhc1-200grp {
811 fsl,pins = <
812 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
813 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
814 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
815 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
816 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
817 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
818 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
819 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
820 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
821 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
822 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
823 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
824 >;
825 };
826
827 pinctrl_usdhc2: usdhc2grp {
828 fsl,pins = <
829 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
830 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
831 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
832 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
833 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
834 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
835 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
836 >;
837 };
838
839 pinctrl_usdhc2_100mhz: usdhc2-100grp {
840 fsl,pins = <
841 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
842 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
843 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
844 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
845 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
846 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
847 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
848 >;
849 };
850
851 pinctrl_usdhc2_200mhz: usdhc2-200grp {
852 fsl,pins = <
853 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
854 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
855 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
856 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
857 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
858 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
859 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
860 >;
861 };
862 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.