1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7 /dts-v1/;
8
9 #include "imx8qm.dtsi"
10
11 / {
12 model = "Freescale i.MX8QM MEK";
13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
14
15 chosen {
16 stdout-path = &lpuart0;
17 };
18
19 cpus {
20 /delete-node/ cpu-map;
21 /delete-node/ cpu@100;
22 /delete-node/ cpu@101;
23 };
24
25 thermal-zones {
26 /delete-node/ cpu1-thermal;
27 };
28
29 memory@80000000 {
30 device_type = "memory";
31 reg = <0x00000000 0x80000000 0 0x40000000>;
32 };
33
34 reg_usdhc2_vmmc: usdhc2-vmmc {
35 compatible = "regulator-fixed";
36 regulator-name = "SD1_SPWR";
37 regulator-min-microvolt = <3000000>;
38 regulator-max-microvolt = <3000000>;
39 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
40 enable-active-high;
41 };
42
43 reg_fec2_supply: regulator-fec2-nvcc {
44 compatible = "regulator-fixed";
45 regulator-name = "fec2_nvcc";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 };
51
52 reg_can01_en: regulator-can01-gen {
53 compatible = "regulator-fixed";
54 regulator-name = "can01-en";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
58 enable-active-high;
59 };
60
61 reg_can2_en: regulator-can2-gen {
62 compatible = "regulator-fixed";
63 regulator-name = "can2-en";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
67 enable-active-high;
68 };
69
70 reg_can01_stby: regulator-can01-stby {
71 compatible = "regulator-fixed";
72 regulator-name = "can01-stby";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
76 enable-active-high;
77 vin-supply = <®_can01_en>;
78 };
79
80 reg_can2_stby: regulator-can2-stby {
81 compatible = "regulator-fixed";
82 regulator-name = "can2-stby";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
86 enable-active-high;
87 vin-supply = <®_can2_en>;
88 };
89
90 reg_vref_1v8: regulator-adc-vref {
91 compatible = "regulator-fixed";
92 regulator-name = "vref_1v8";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 };
96
97 bt_sco_codec: audio-codec-bt {
98 compatible = "linux,bt-sco";
99 #sound-dai-cells = <1>;
100 };
101
102 sound-bt-sco {
103 compatible = "simple-audio-card";
104 simple-audio-card,name = "bt-sco-audio";
105 simple-audio-card,format = "dsp_a";
106 simple-audio-card,bitclock-inversion;
107 simple-audio-card,frame-master = <&btcpu>;
108 simple-audio-card,bitclock-master = <&btcpu>;
109
110 btcpu: simple-audio-card,cpu {
111 sound-dai = <&sai0>;
112 dai-tdm-slot-num = <2>;
113 dai-tdm-slot-width = <16>;
114 };
115
116 simple-audio-card,codec {
117 sound-dai = <&bt_sco_codec 1>;
118 };
119 };
120
121 sound-wm8960 {
122 compatible = "fsl,imx-audio-wm8960";
123 model = "wm8960-audio";
124 audio-cpu = <&sai1>;
125 audio-codec = <&wm8960>;
126 hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
127 audio-routing = "Headphone Jack", "HP_L",
128 "Headphone Jack", "HP_R",
129 "Ext Spk", "SPK_LP",
130 "Ext Spk", "SPK_LN",
131 "Ext Spk", "SPK_RP",
132 "Ext Spk", "SPK_RN",
133 "LINPUT1", "Mic Jack",
134 "Mic Jack", "MICB";
135 };
136 };
137
138 &adc0 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_adc0>;
141 vref-supply = <®_vref_1v8>;
142 status = "okay";
143 };
144
145 &amix {
146 status = "okay";
147 };
148
149 &asrc0 {
150 fsl,asrc-rate = <48000>;
151 status = "okay";
152 };
153
154 &cm41_i2c {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 clock-frequency = <100000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_cm41_i2c>;
160 status = "okay";
161
162 pca6416: gpio@20 {
163 compatible = "ti,tca6416";
164 reg = <0x20>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 };
168 };
169
170 &cm41_intmux {
171 status = "okay";
172 };
173
174 &i2c0 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 clock-frequency = <100000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c0>;
180 status = "okay";
181
182 accelerometer@19 {
183 compatible = "st,lsm303agr-accel";
184 reg = <0x19>;
185 };
186
187 gyrometer@20 {
188 compatible = "nxp,fxas21002c";
189 reg = <0x20>;
190 };
191
192 light-sensor@44 {
193 compatible = "isil,isl29023";
194 reg = <0x44>;
195 interrupt-parent = <&lsio_gpio4>;
196 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
197 };
198
199 pressure-sensor@60 {
200 compatible = "fsl,mpl3115";
201 reg = <0x60>;
202 };
203
204 max7322: gpio@68 {
205 compatible = "maxim,max7322";
206 reg = <0x68>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 };
210
211 gyrometer@69 {
212 compatible = "st,l3g4200d-gyro";
213 reg = <0x69>;
214 };
215 };
216
217 &i2c1 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 clock-frequency = <100000>;
221 pinctrl-names = "default", "gpio";
222 pinctrl-0 = <&pinctrl_i2c1>;
223 pinctrl-1 = <&pinctrl_i2c1_gpio>;
224 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
225 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
226 status = "okay";
227
228 wm8960: audio-codec@1a {
229 compatible = "wlf,wm8960";
230 reg = <0x1a>;
231 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
232 clock-names = "mclk";
233 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
234 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
235 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
236 <&mclkout0_lpcg IMX_LPCG_CLK_0>;
237 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
238 wlf,shared-lrclk;
239 wlf,hp-cfg = <2 2 3>;
240 wlf,gpio-cfg = <1 3>;
241 };
242 };
243
244 &flexcan1 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_flexcan1>;
247 xceiver-supply = <®_can01_stby>;
248 status = "okay";
249 };
250
251 &flexcan2 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_flexcan2>;
254 xceiver-supply = <®_can01_stby>;
255 status = "okay";
256 };
257
258 &flexcan3 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_flexcan3>;
261 xceiver-supply = <®_can2_stby>;
262 status = "okay";
263 };
264
265 &lpuart0 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_lpuart0>;
268 status = "okay";
269 };
270
271 &lpuart2 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_lpuart2>;
274 status = "okay";
275 };
276
277 &lpuart3 {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_lpuart3>;
280 status = "okay";
281 };
282
283 &lpspi2 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
288 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
289 status = "okay";
290
291 spidev0: spi@0 {
292 reg = <0>;
293 compatible = "rohm,dh2228fv";
294 spi-max-frequency = <30000000>;
295 };
296 };
297
298 &lsio_mu5 {
299 status = "okay";
300 };
301
302 &lsio_mu6 {
303 status = "okay";
304 };
305
306 &flexspi0 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_flexspi0>;
309 status = "okay";
310
311 flash0: flash@0 {
312 reg = <0>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "jedec,spi-nor";
316 spi-max-frequency = <133000000>;
317 spi-tx-bus-width = <8>;
318 spi-rx-bus-width = <8>;
319 };
320 };
321
322 &fec1 {
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_fec1>;
325 phy-mode = "rgmii-id";
326 phy-handle = <ðphy0>;
327 fsl,magic-packet;
328 status = "okay";
329
330 mdio {
331 #address-cells = <1>;
332 #size-cells = <0>;
333
334 ethphy0: ethernet-phy@0 {
335 compatible = "ethernet-phy-ieee802.3-c22";
336 reg = <0>;
337 };
338
339 ethphy1: ethernet-phy@1 {
340 compatible = "ethernet-phy-ieee802.3-c22";
341 reg = <1>;
342 };
343 };
344 };
345
346 &fec2 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_fec2>;
349 phy-mode = "rgmii-txid";
350 phy-handle = <ðphy1>;
351 phy-supply = <®_fec2_supply>;
352 nvmem-cells = <&fec_mac1>;
353 nvmem-cell-names = "mac-address";
354 rx-internal-delay-ps = <2000>;
355 fsl,magic-packet;
356 status = "okay";
357 };
358
359 &usdhc1 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_usdhc1>;
362 bus-width = <8>;
363 no-sd;
364 no-sdio;
365 non-removable;
366 status = "okay";
367 };
368
369 &usdhc2 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usdhc2>;
372 bus-width = <4>;
373 vmmc-supply = <®_usdhc2_vmmc>;
374 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
375 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
376 status = "okay";
377 };
378
379 &sai0 {
380 #sound-dai-cells = <0>;
381 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
382 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
383 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
384 <&sai0_lpcg IMX_LPCG_CLK_4>;
385 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_sai0>;
388 status = "okay";
389 };
390
391 &sai1 {
392 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
393 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
394 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
395 <&sai1_lpcg IMX_LPCG_CLK_4>;
396 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_sai1>;
399 status = "okay";
400 };
401
402 &sai6 {
403 assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
404 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
405 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
406 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
407 <&sai6_lpcg IMX_LPCG_CLK_4>;
408 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
409 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
410 fsl,sai-asynchronous;
411 status = "okay";
412 };
413
414 &sai7 {
415 assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
416 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
417 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
418 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
419 <&sai7_lpcg IMX_LPCG_CLK_4>;
420 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
421 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
422 fsl,sai-asynchronous;
423 status = "okay";
424 };
425
426 &iomuxc {
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_hog>;
429
430 pinctrl_hog: hoggrp {
431 fsl,pins = <
432 IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
433 IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
434 >;
435 };
436
437 pinctrl_i2c0: i2c0grp {
438 fsl,pins = <
439 IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
440 IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
441 >;
442 };
443
444 pinctrl_i2c1: i2c1grp {
445 fsl,pins = <
446 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
447 IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
448 >;
449 };
450
451 pinctrl_i2c1_gpio: i2c1gpio-grp {
452 fsl,pins = <
453 IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c
454 IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
455 >;
456 };
457
458 pinctrl_adc0: adc0grp {
459 fsl,pins = <
460 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060
461 >;
462 };
463
464 pinctrl_cm41_i2c: cm41i2cgrp {
465 fsl,pins = <
466 IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c
467 IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c
468 >;
469 };
470
471 pinctrl_fec1: fec1grp {
472 fsl,pins = <
473 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
474 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
475 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
476 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
477 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
478 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
479 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
480 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
481 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
482 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
483 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
484 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
485 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
486 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
487 >;
488 };
489
490 pinctrl_lpspi2: lpspi2grp {
491 fsl,pins = <
492 IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040
493 IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040
494 IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040
495 >;
496 };
497
498 pinctrl_lpspi2_cs: lpspi2csgrp {
499 fsl,pins = <
500 IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
501 >;
502 };
503
504 pinctrl_flexspi0: flexspi0grp {
505 fsl,pins = <
506 IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
507 IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
508 IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
509 IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
510 IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
511 IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
512 IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
513 IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
514 IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
515 IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
516 IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
517 IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
518 IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
519 IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
520 IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
521 IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
522 >;
523 };
524
525 pinctrl_fec2: fec2grp {
526 fsl,pins = <
527 IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
528 IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
529 IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
530 IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
531 IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
532 IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
533 IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
534 IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
535 IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
536 IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
537 IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
538 IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
539 IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
540 >;
541 };
542
543 pinctrl_flexcan1: flexcan0grp {
544 fsl,pins = <
545 IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21
546 IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21
547 >;
548 };
549
550 pinctrl_flexcan2: flexcan1grp {
551 fsl,pins = <
552 IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21
553 IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21
554 >;
555 };
556
557 pinctrl_flexcan3: flexcan3grp {
558 fsl,pins = <
559 IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21
560 IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21
561 >;
562 };
563
564 pinctrl_lpuart0: lpuart0grp {
565 fsl,pins = <
566 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
567 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
568 >;
569 };
570
571 pinctrl_lpuart2: lpuart2grp {
572 fsl,pins = <
573 IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
574 IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
575 >;
576 };
577
578 pinctrl_lpuart3: lpuart3grp {
579 fsl,pins = <
580 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
581 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
582 >;
583 };
584
585 pinctrl_sai0: sai0grp {
586 fsl,pins = <
587 IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c
588 IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c
589 IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c
590 IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c
591 >;
592 };
593
594 pinctrl_sai1: sai1grp {
595 fsl,pins = <
596 IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040
597 IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040
598 IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060
599 IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040
600 >;
601 };
602
603 pinctrl_usdhc1: usdhc1grp {
604 fsl,pins = <
605 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
606 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
607 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
608 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
609 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
610 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
611 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
612 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
613 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
614 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
615 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
616 >;
617 };
618
619 pinctrl_usdhc2: usdhc2grp {
620 fsl,pins = <
621 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
622 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
623 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
624 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
625 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
626 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
627 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
628 >;
629 };
630 };
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