1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
6 *
7 * Product homepage:
8 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
9 */
10
11 #include <dt-bindings/leds/common.h>
12
13 #include "imx93.dtsi"
14
15 /{
16 model = "PHYTEC phyCORE-i.MX93";
17 compatible = "phytec,imx93-phycore-som", "fsl,imx93";
18
19 reserved-memory {
20 ranges;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 linux,cma {
25 compatible = "shared-dma-pool";
26 reusable;
27 alloc-ranges = <0 0x80000000 0 0x40000000>;
28 size = <0 0x10000000>;
29 linux,cma-default;
30 };
31 };
32
33 leds {
34 compatible = "gpio-leds";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_leds>;
37
38 led-0 {
39 color = <LED_COLOR_ID_GREEN>;
40 function = LED_FUNCTION_HEARTBEAT;
41 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
42 linux,default-trigger = "heartbeat";
43 };
44 };
45 };
46
47 /* Ethernet */
48 &fec {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_fec>;
51 phy-mode = "rmii";
52 phy-handle = <ðphy1>;
53 fsl,magic-packet;
54 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
55 <&clk IMX93_CLK_ENET_REF>,
56 <&clk IMX93_CLK_ENET_REF_PHY>;
57 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
58 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
59 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
60 assigned-clock-rates = <100000000>, <50000000>, <50000000>;
61 status = "okay";
62
63 mdio: mdio {
64 clock-frequency = <5000000>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 ethphy1: ethernet-phy@1 {
69 compatible = "ethernet-phy-ieee802.3-c22";
70 reg = <1>;
71 };
72 };
73 };
74
75 /* eMMC */
76 &usdhc1 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usdhc1>;
79 bus-width = <8>;
80 non-removable;
81 status = "okay";
82 };
83
84 /* Watchdog */
85 &wdog3 {
86 status = "okay";
87 };
88
89 &iomuxc {
90 pinctrl_fec: fecgrp {
91 fsl,pins = <
92 MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
93 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
94 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
95 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
96 MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
97 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
98 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
99 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
100 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
101 MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
102 >;
103 };
104
105 pinctrl_leds: ledsgrp {
106 fsl,pins = <
107 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
108 >;
109 };
110
111 pinctrl_usdhc1: usdhc1grp {
112 fsl,pins = <
113 MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
114 MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
115 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
116 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
117 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
118 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
119 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
120 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
121 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
122 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
123 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
124 >;
125 };
126 };
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