1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8 /dts-v1/;
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
14
15 #include "imx93-tqma9352.dtsi"
16
17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";
19 compatible = "tq,imx93-tqma9352-mba93xxca",
20 "tq,imx93-tqma9352", "fsl,imx93";
21 chassis-type = "embedded";
22
23 chosen {
24 stdout-path = &lpuart1;
25 };
26
27 aliases {
28 eeprom0 = &eeprom0;
29 rtc0 = &pcf85063;
30 rtc1 = &bbnsm_rtc;
31 };
32
33 backlight_lvds: backlight {
34 compatible = "pwm-backlight";
35 pwms = <&tpm5 0 5000000 0>;
36 brightness-levels = <0 4 8 16 32 64 128 255>;
37 default-brightness-level = <7>;
38 power-supply = <®_12v0>;
39 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
40 status = "disabled";
41 };
42
43 fan0: pwm-fan {
44 compatible = "pwm-fan";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_pwmfan>;
47 fan-supply = <®_pwm_fan>;
48 #cooling-cells = <2>;
49 /* typical 25 kHz -> 40.000 nsec */
50 pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>;
51 cooling-levels = <0 32 64 128 196 240>;
52 pulses-per-revolution = <2>;
53 interrupt-parent = <&gpio2>;
54 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
55 status = "disabled";
56 };
57
58 gpio-keys {
59 compatible = "gpio-keys";
60 autorepeat;
61
62 switch-a {
63 label = "switcha";
64 linux,code = <BTN_0>;
65 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
66 wakeup-source;
67 };
68
69 switch-b {
70 label = "switchb";
71 linux,code = <BTN_1>;
72 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
73 wakeup-source;
74 };
75 };
76
77 gpio-leds {
78 compatible = "gpio-leds";
79
80 led-1 {
81 color = <LED_COLOR_ID_GREEN>;
82 function = LED_FUNCTION_STATUS;
83 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
84 linux,default-trigger = "default-on";
85 };
86
87 led-2 {
88 color = <LED_COLOR_ID_AMBER>;
89 function = LED_FUNCTION_HEARTBEAT;
90 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
91 linux,default-trigger = "heartbeat";
92 };
93 };
94
95 iio-hwmon {
96 compatible = "iio-hwmon";
97 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
98 };
99
100 reg_3v3: regulator-3v3 {
101 compatible = "regulator-fixed";
102 regulator-name = "V_3V3_MB";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 };
106
107 reg_5v0: regulator-5v0 {
108 compatible = "regulator-fixed";
109 regulator-name = "V_5V0_MB";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 };
113
114 reg_12v0: regulator-12v0 {
115 compatible = "regulator-fixed";
116 regulator-name = "V_12V";
117 regulator-min-microvolt = <12000000>;
118 regulator-max-microvolt = <12000000>;
119 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 };
122
123 reg_mpcie_1v5: regulator-mpcie-1v5 {
124 compatible = "regulator-fixed";
125 regulator-name = "V_1V5_MPCIE";
126 regulator-min-microvolt = <1500000>;
127 regulator-max-microvolt = <1500000>;
128 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
129 enable-active-high;
130 };
131
132 reg_mpcie_3v3: regulator-mpcie-3v3 {
133 compatible = "regulator-fixed";
134 regulator-name = "V_3V3_MPCIE";
135 regulator-min-microvolt = <3300000>;
136 regulator-max-microvolt = <3300000>;
137 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
138 enable-active-high;
139 };
140
141 reg_pwm_fan: regulator-pwm-fan {
142 compatible = "regulator-fixed";
143 regulator-name = "FAN_PWR";
144 regulator-min-microvolt = <12000000>;
145 regulator-max-microvolt = <12000000>;
146 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
147 enable-active-high;
148 vin-supply = <®_12v0>;
149 };
150
151 thermal-zones {
152 cpu-thermal {
153 trips {
154 cpu_active0: trip-active0 {
155 temperature = <40000>;
156 hysteresis = <5000>;
157 type = "active";
158 };
159
160 cpu_active1: trip-active1 {
161 temperature = <48000>;
162 hysteresis = <3000>;
163 type = "active";
164 };
165
166 cpu_active2: trip-active2 {
167 temperature = <60000>;
168 hysteresis = <10000>;
169 type = "active";
170 };
171 };
172
173 cooling-maps {
174 map1 {
175 trip = <&cpu_active0>;
176 cooling-device = <&fan0 1 1>;
177 };
178
179 map2 {
180 trip = <&cpu_active1>;
181 cooling-device = <&fan0 2 2>;
182 };
183
184 map3 {
185 trip = <&cpu_active2>;
186 cooling-device = <&fan0 3 3>;
187 };
188 };
189 };
190 };
191 };
192
193 &adc1 {
194 status = "okay";
195 };
196
197 &eqos {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_eqos>;
200 phy-mode = "rgmii-id";
201 phy-handle = <ðphy_eqos>;
202 status = "okay";
203
204 mdio {
205 compatible = "snps,dwmac-mdio";
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 ethphy_eqos: ethernet-phy@0 {
210 compatible = "ethernet-phy-ieee802.3-c22";
211 reg = <0>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_eqos_phy>;
214 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
215 reset-assert-us = <500000>;
216 reset-deassert-us = <50000>;
217 interrupt-parent = <&gpio3>;
218 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
219 enet-phy-lane-no-swap;
220 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
221 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
222 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
223 ti,dp83867-rxctrl-strap-quirk;
224 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
225 };
226 };
227 };
228
229 &fec {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_fec>;
232 phy-mode = "rgmii-id";
233 phy-handle = <ðphy_fec>;
234 fsl,magic-packet;
235 status = "okay";
236
237 mdio {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 clock-frequency = <5000000>;
241
242 ethphy_fec: ethernet-phy@0 {
243 compatible = "ethernet-phy-ieee802.3-c22";
244 reg = <0>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_fec_phy>;
247 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
248 reset-assert-us = <500000>;
249 reset-deassert-us = <50000>;
250 interrupt-parent = <&gpio3>;
251 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
252 enet-phy-lane-no-swap;
253 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
254 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
255 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
256 ti,dp83867-rxctrl-strap-quirk;
257 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
258 };
259 };
260 };
261
262 &flexcan1 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_flexcan1>;
265 xceiver-supply = <®_3v3>;
266 status = "okay";
267 };
268
269 &flexcan2 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_flexcan2>;
272 xceiver-supply = <®_3v3>;
273 status = "okay";
274 };
275
276 &gpio1 {
277 expander-irq-hog {
278 gpio-hog;
279 gpios = <12 GPIO_ACTIVE_LOW>;
280 input;
281 line-name = "PEX_INT#";
282 };
283
284 tcpc-irq-hog {
285 gpio-hog;
286 gpios = <2 GPIO_ACTIVE_LOW>;
287 input;
288 line-name = "USB_C_ALERT#";
289 };
290 };
291
292 &lpi2c3 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 clock-frequency = <400000>;
296 pinctrl-names = "default", "sleep";
297 pinctrl-0 = <&pinctrl_lpi2c3>;
298 pinctrl-1 = <&pinctrl_lpi2c3>;
299 status = "okay";
300
301 temperature-sensor@1c {
302 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
303 reg = <0x1c>;
304 };
305
306 ptn5110: usb-typec@50 {
307 compatible = "nxp,ptn5110", "tcpci";
308 reg = <0x50>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_typec>;
311 interrupt-parent = <&gpio1>;
312 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
313
314 connector {
315 compatible = "usb-c-connector";
316 label = "X17";
317 power-role = "dual";
318 data-role = "dual";
319 try-power-role = "sink";
320 typec-power-opmode = "default";
321 pd-disable;
322 self-powered;
323
324 port {
325 typec_con_hs: endpoint {
326 remote-endpoint = <&typec_hs>;
327 };
328 };
329 };
330 };
331
332 eeprom2: eeprom@54 {
333 compatible = "nxp,se97b", "atmel,24c02";
334 reg = <0x54>;
335 pagesize = <16>;
336 vcc-supply = <®_3v3>;
337 };
338
339 expander0: gpio@70 {
340 compatible = "nxp,pca9538";
341 reg = <0x70>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_pexp_irq>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 interrupt-parent = <&gpio1>;
349 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
350 vcc-supply = <®_3v3>;
351 gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",
352 "MPCIE_1V5_EN", "MPCIE_3V3_EN",
353 "MPCIE_PERST#", "MPCIE_WDISABLE#",
354 "BUTTON_A#", "BUTTON_B#";
355
356 mpcie-wake-hog {
357 gpio-hog;
358 gpios = <1 GPIO_ACTIVE_LOW>;
359 input;
360 line-name = "MPCIE_WAKE#";
361 };
362
363 /*
364 * Controls the mPCIE slot reset which is low active as
365 * reset signal. The output-low states, the signal is
366 * inactive, e.g. not in reset
367 */
368 mpcie_rst_hog: mpcie-rst-hog {
369 gpio-hog;
370 gpios = <4 GPIO_ACTIVE_LOW>;
371 output-low;
372 line-name = "MPCIE_PERST#";
373 };
374
375 /*
376 * Controls the mPCIE slot WDISABLE pin which is low active
377 * as disable signal. The output-low states, the signal is
378 * inactive, e.g. not disabled
379 */
380 mpcie_wdisable_hog: mpcie-wdisable-hog {
381 gpio-hog;
382 gpios = <5 GPIO_ACTIVE_LOW>;
383 output-low;
384 line-name = "MPCIE_WDISABLE#";
385 };
386 };
387
388 expander1: gpio@71 {
389 compatible = "nxp,pca9538";
390 reg = <0x71>;
391 gpio-controller;
392 #gpio-cells = <2>;
393 vcc-supply = <®_3v3>;
394 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
395 "USB_RESET#", "",
396 "WLAN_PD#", "WLAN_W_DISABLE#",
397 "WLAN_PERST#", "12V_EN";
398
399 /*
400 * Controls the WiFi card PD pin which is low active
401 * as power down signal. The output-high states, the signal
402 * is active, e.g. card is powered down
403 */
404 wlan-pd-hog {
405 gpio-hog;
406 gpios = <4 GPIO_ACTIVE_LOW>;
407 output-high;
408 line-name = "WLAN_PD#";
409 };
410
411 /*
412 * Controls the WiFi card disable pin which is low active
413 * as disable signal. The output-high states, the signal
414 * is active, e.g. card is disabled
415 */
416 wlan-wdisable-hog {
417 gpio-hog;
418 gpios = <5 GPIO_ACTIVE_LOW>;
419 output-high;
420 line-name = "WLAN_W_DISABLE#";
421 };
422
423 /*
424 * Controls the WiFi card reset pin which is low active
425 * as reset signal. The output-high states, the signal
426 * is active, e.g. card in reset
427 */
428 wlan-perst-hog {
429 gpio-hog;
430 gpios = <6 GPIO_ACTIVE_LOW>;
431 output-high;
432 line-name = "WLAN_PERST#";
433 };
434 };
435
436 expander2: gpio@72 {
437 compatible = "nxp,pca9538";
438 reg = <0x72>;
439 gpio-controller;
440 #gpio-cells = <2>;
441 vcc-supply = <®_3v3>;
442 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
443 "LCD_BLT_EN", "DP_EN",
444 "MIPI_CSI_EN", "MIPI_CSI_RST#",
445 "USER_LED1", "USER_LED2";
446 };
447 };
448
449 &lpi2c5 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 clock-frequency = <400000>;
453 pinctrl-names = "default", "sleep";
454 pinctrl-0 = <&pinctrl_lpi2c5>;
455 pinctrl-1 = <&pinctrl_lpi2c5>;
456 status = "okay";
457 };
458
459 &lpspi6 {
460 pinctrl-names = "default", "sleep";
461 pinctrl-0 = <&pinctrl_lpspi6>;
462 pinctrl-1 = <&pinctrl_lpspi6>;
463 status = "okay";
464 };
465
466 &lpuart1 {
467 pinctrl-names = "default";
468 pinctrl-0 = <&pinctrl_uart1>;
469 status = "okay";
470 };
471
472 &lpuart2 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_uart2>;
475 linux,rs485-enabled-at-boot-time;
476 status = "okay";
477 };
478
479 /* disabled per default, console for M33 */
480 &lpuart3 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_uart3>;
483 status = "disabled";
484 };
485
486 &lpuart6 {
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart6>;
489 status = "okay";
490 };
491
492 &lpuart8 {
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_uart8>;
495 status = "okay";
496 };
497
498 &tpm5 {
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_tpm5>;
501 };
502
503 &tpm6 {
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_tpm6>;
506 status = "okay";
507 };
508
509 &usbotg1 {
510 dr_mode = "otg";
511 hnp-disable;
512 srp-disable;
513 adp-disable;
514 usb-role-switch;
515 disable-over-current;
516 samsung,picophy-pre-emp-curr-control = <3>;
517 samsung,picophy-dc-vol-level-adjust = <7>;
518 status = "okay";
519
520 port {
521 typec_hs: endpoint {
522 remote-endpoint = <&typec_con_hs>;
523 };
524 };
525 };
526
527 &usbotg2 {
528 dr_mode = "host";
529 #address-cells = <1>;
530 #size-cells = <0>;
531 disable-over-current;
532 samsung,picophy-pre-emp-curr-control = <3>;
533 samsung,picophy-dc-vol-level-adjust = <7>;
534 status = "okay";
535
536 hub_2_0: hub@1 {
537 compatible = "usb424,2517";
538 reg = <1>;
539 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
540 vdd-supply = <®_3v3>;
541 };
542 };
543
544 &usdhc2 {
545 pinctrl-names = "default", "state_100mhz", "state_200mhz";
546 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
547 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
548 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
549 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
550 vmmc-supply = <®_usdhc2_vmmc>;
551 bus-width = <4>;
552 no-sdio;
553 no-mmc;
554 disable-wp;
555 status = "okay";
556 };
557
558 &iomuxc {
559 pinctrl_eqos: eqosgrp {
560 fsl,pins = <
561 /* PD | FSEL_2 | DSE X4 */
562 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
563 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
564 /* PD | FSEL_2 | DSE X6 */
565 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
566 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
567 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
568 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
569 /* PD | FSEL_3 | DSE X6 */
570 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
571 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
572 /* PD | FSEL_2 | DSE X4 */
573 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
574 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
575 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
576 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
577 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
578 /* PD | FSEL_3 | DSE X3 */
579 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
580 >;
581 };
582
583 pinctrl_eqos_phy: eqosphygrp {
584 fsl,pins = <
585 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
586 >;
587 };
588
589 pinctrl_fec: fecgrp {
590 fsl,pins = <
591 /* PD | FSEL_2 | DSE X4 */
592 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
593 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
594 /* PD | FSEL_2 | DSE X6 */
595 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
596 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
597 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
598 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
599 /* PD | FSEL_3 | DSE X6 */
600 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
601 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
602 /* PD | FSEL_2 | DSE X4 */
603 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
604 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
605 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
606 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
607 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
608 /* PD | FSEL_3 | DSE X3 */
609 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
610 >;
611 };
612
613 pinctrl_fec_phy: fecphygrp {
614 fsl,pins = <
615 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
616 >;
617 };
618
619 pinctrl_flexcan1: flexcan1grp {
620 fsl,pins = <
621 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
622 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
623 >;
624 };
625
626 pinctrl_flexcan2: flexcan2grp {
627 fsl,pins = <
628 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
629 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
630 >;
631 };
632
633 pinctrl_lpi2c3: lpi2c3grp {
634 fsl,pins = <
635 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
636 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
637 >;
638 };
639
640 pinctrl_lpi2c5: lpi2c5grp {
641 fsl,pins = <
642 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
643 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
644 >;
645 };
646
647 pinctrl_lpspi6: lpspi6grp {
648 fsl,pins = <
649 MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x3fe
650 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
651 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe
652 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe
653 >;
654 };
655
656 pinctrl_pexp_irq: pexpirqgrp {
657 fsl,pins = <
658 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
659 >;
660 };
661
662 pinctrl_pwmfan: pwmfangrp {
663 fsl,pins = <
664 MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1306
665 >;
666 };
667
668 pinctrl_tpm5: tpm5grp {
669 fsl,pins = <
670 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
671 >;
672 };
673
674 pinctrl_tpm6: tpm6grp {
675 fsl,pins = <
676 MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e
677 >;
678 };
679
680 pinctrl_typec: typecgrp {
681 fsl,pins = <
682 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
683 >;
684 };
685
686 pinctrl_uart1: uart1grp {
687 fsl,pins = <
688 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
689 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
690 >;
691 };
692
693 pinctrl_uart2: uart2grp {
694 fsl,pins = <
695 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
696 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
697 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
698 >;
699 };
700
701 pinctrl_uart3: uart3grp {
702 fsl,pins = <
703 MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
704 MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
705 >;
706 };
707
708 pinctrl_uart6: uart6grp {
709 fsl,pins = <
710 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
711 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
712 >;
713 };
714
715 pinctrl_uart8: uart8grp {
716 fsl,pins = <
717 MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
718 MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
719 >;
720 };
721
722 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
723 fsl,pins = <
724 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
725 >;
726 };
727
728 pinctrl_usdhc2_hs: usdhc2hsgrp {
729 fsl,pins = <
730 /* HYS | PD | PU | FSEL_3 | DSE X5 */
731 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
732 /* HYS | PD | PU | FSEL_3 | DSE X4 */
733 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
734 /* HYS | PD | PU | FSEL_3 | DSE X3 */
735 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
736 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
737 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
738 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
739 /* PD | PU | FSEL_2 | DSE X3 */
740 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
741 >;
742 };
743
744 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
745 fsl,pins = <
746 /* HYS | PD | PU | FSEL_3 | DSE X6 */
747 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
748 /* HYS | PD | PU | FSEL_3 | DSE X4 */
749 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
750 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
751 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
752 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
753 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
754 /* PD | PU | FSEL_2 | DSE X3 */
755 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
756 >;
757 };
758 };
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