1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8 /dts-v1/;
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "imx93-tqma9352.dtsi"
16
17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
19 compatible = "tq,imx93-tqma9352-mba93xxla",
20 "tq,imx93-tqma9352", "fsl,imx93";
21 chassis-type = "embedded";
22
23 chosen {
24 stdout-path = &lpuart1;
25 };
26
27 aliases {
28 eeprom0 = &eeprom0;
29 rtc0 = &pcf85063;
30 rtc1 = &bbnsm_rtc;
31 };
32
33 backlight_lvds: backlight {
34 compatible = "pwm-backlight";
35 pwms = <&tpm5 0 5000000 0>;
36 brightness-levels = <0 4 8 16 32 64 128 255>;
37 default-brightness-level = <7>;
38 power-supply = <®_12v0>;
39 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
40 status = "disabled";
41 };
42
43 clk_dp: clk-dp {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <26000000>;
47 };
48
49 gpio-keys {
50 compatible = "gpio-keys";
51 autorepeat;
52
53 switch-a {
54 label = "switcha";
55 linux,code = <BTN_0>;
56 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
57 wakeup-source;
58 };
59
60 switch-b {
61 label = "switchb";
62 linux,code = <BTN_1>;
63 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
64 wakeup-source;
65 };
66 };
67
68 gpio-leds {
69 compatible = "gpio-leds";
70
71 led-1 {
72 color = <LED_COLOR_ID_GREEN>;
73 function = LED_FUNCTION_STATUS;
74 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger = "default-on";
76 };
77
78 led-2 {
79 color = <LED_COLOR_ID_AMBER>;
80 function = LED_FUNCTION_HEARTBEAT;
81 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
82 linux,default-trigger = "heartbeat";
83 };
84 };
85
86 iio-hwmon {
87 compatible = "iio-hwmon";
88 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
89 };
90
91 reg_3v3: regulator-3v3 {
92 compatible = "regulator-fixed";
93 regulator-name = "V_3V3_MB";
94 regulator-min-microvolt = <3300000>;
95 regulator-max-microvolt = <3300000>;
96 };
97
98 reg_3v8: regulator-3v8 {
99 compatible = "regulator-fixed";
100 regulator-name = "V_3V8";
101 regulator-min-microvolt = <3800000>;
102 regulator-max-microvolt = <3800000>;
103 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 /* TODO: this is supply for IOT module */
106 regulator-always-on;
107 };
108
109 reg_5v0: regulator-5v0 {
110 compatible = "regulator-fixed";
111 regulator-name = "V_5V0_MB";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 };
115
116 reg_12v0: regulator-12v0 {
117 compatible = "regulator-fixed";
118 regulator-name = "V_12V";
119 regulator-min-microvolt = <12000000>;
120 regulator-max-microvolt = <12000000>;
121 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
122 enable-active-high;
123 };
124 };
125
126 &adc1 {
127 status = "okay";
128 };
129
130 &eqos {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_eqos>;
133 phy-mode = "rgmii-id";
134 phy-handle = <ðphy_eqos>;
135 status = "okay";
136
137 mdio {
138 compatible = "snps,dwmac-mdio";
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 ethphy_eqos: ethernet-phy@0 {
143 compatible = "ethernet-phy-ieee802.3-c22";
144 reg = <0>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_eqos_phy>;
147 interrupt-parent = <&gpio3>;
148 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
149 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
150 reset-assert-us = <500000>;
151 reset-deassert-us = <50000>;
152 enet-phy-lane-no-swap;
153 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
154 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
155 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
156 ti,dp83867-rxctrl-strap-quirk;
157 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
158 };
159 };
160 };
161
162 &fec {
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_fec>;
165 phy-mode = "rgmii-id";
166 phy-handle = <ðphy_fec>;
167 fsl,magic-packet;
168 status = "okay";
169
170 mdio {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 clock-frequency = <5000000>;
174
175 ethphy_fec: ethernet-phy@0 {
176 compatible = "ethernet-phy-ieee802.3-c22";
177 reg = <0>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_fec_phy>;
180 interrupt-parent = <&gpio3>;
181 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
182 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
183 reset-assert-us = <500000>;
184 reset-deassert-us = <50000>;
185 enet-phy-lane-no-swap;
186 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
187 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
188 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
189 ti,dp83867-rxctrl-strap-quirk;
190 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
191 };
192 };
193 };
194
195 &flexcan1 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_flexcan1>;
198 xceiver-supply = <®_3v3>;
199 status = "okay";
200 };
201
202 &flexcan2 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_flexcan2>;
205 xceiver-supply = <®_3v3>;
206 status = "okay";
207 };
208
209 &gpio1 {
210 expander-irq-hog {
211 gpio-hog;
212 gpios = <12 GPIO_ACTIVE_LOW>;
213 input;
214 line-name = "PEX_INT#";
215 };
216
217 rtc-irq-hog {
218 gpio-hog;
219 gpios = <14 GPIO_ACTIVE_LOW>;
220 input;
221 line-name = "RTC_EVENT#";
222 };
223 };
224
225 &gpio3 {
226 ethphy-eqos-irq-hog {
227 gpio-hog;
228 gpios = <26 GPIO_ACTIVE_LOW>;
229 input;
230 line-name = "ENET0_IRQ#";
231 };
232
233 ethphy-fec-irq-hog {
234 gpio-hog;
235 gpios = <27 GPIO_ACTIVE_LOW>;
236 input;
237 line-name = "ENET1_IRQ#";
238 };
239 };
240
241 &lpi2c3 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 clock-frequency = <400000>;
245 pinctrl-names = "default", "sleep";
246 pinctrl-0 = <&pinctrl_lpi2c3>;
247 pinctrl-1 = <&pinctrl_lpi2c3>;
248 status = "okay";
249
250 temperature-sensor@1c {
251 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
252 reg = <0x1c>;
253 };
254
255 ptn5110: usb-typec@50 {
256 compatible = "nxp,ptn5110", "tcpci";
257 reg = <0x50>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_typec>;
260 interrupt-parent = <&gpio1>;
261 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
262
263 connector {
264 compatible = "usb-c-connector";
265 label = "X17";
266 power-role = "dual";
267 data-role = "dual";
268 try-power-role = "sink";
269 typec-power-opmode = "default";
270 pd-disable;
271 self-powered;
272
273 port {
274 typec_con_hs: endpoint {
275 remote-endpoint = <&typec_hs>;
276 };
277 };
278 };
279 };
280
281 eeprom2: eeprom@54 {
282 compatible = "nxp,se97b", "atmel,24c02";
283 reg = <0x54>;
284 pagesize = <16>;
285 vcc-supply = <®_3v3>;
286 };
287
288 expander0: gpio@70 {
289 compatible = "nxp,pca9538";
290 reg = <0x70>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_pexp_irq>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 interrupt-parent = <&gpio1>;
298 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
299 vcc-supply = <®_3v3>;
300 gpio-line-names = "3V8_EN", "",
301 "", "IOT_PWRKEY",
302 "IOT_RESET", "IOT_W_DISABLE",
303 "BUTTON_A#", "BUTTON_B#";
304
305 /*
306 * Controls the IOT W_DISABLE pin which is low active
307 * as disable signal but inverted as seen from the CPU.
308 * The output-low states, the signal is
309 * inactive, e.g. not disabled
310 */
311 iot_wdisable_hog: iot-wdisable-hog {
312 gpio-hog;
313 gpios = <5 GPIO_ACTIVE_HIGH>;
314 output-low;
315 line-name = "IOT_W_DISABLE";
316 };
317 };
318
319 expander1: gpio@71 {
320 compatible = "nxp,pca9538";
321 reg = <0x71>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 vcc-supply = <®_3v3>;
325 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
326 "USB_RESET#", "",
327 "WLAN_PD#", "WLAN_W_DISABLE#",
328 "WLAN_PERST#", "12V_EN";
329
330 /*
331 * Controls the WiFi card PD pin which is low active
332 * as power down signal. The output-low states, the signal
333 * is inactive, e.g. not power down
334 */
335 wlan-pd-hog {
336 gpio-hog;
337 gpios = <4 GPIO_ACTIVE_LOW>;
338 output-low;
339 line-name = "WLAN_PD#";
340 };
341
342 /*
343 * Controls the WiFi card disable pin which is low active
344 * as disable signal. The output-low states, the signal
345 * is inactive, e.g. not disabled
346 */
347 wlan-wdisable-hog {
348 gpio-hog;
349 gpios = <5 GPIO_ACTIVE_LOW>;
350 output-low;
351 line-name = "WLAN_W_DISABLE#";
352 };
353
354 /*
355 * Controls the WiFi card reset pin which is low active
356 * as reset signal. The output-low states, the signal
357 * is inactive, e.g. not in reset
358 */
359 wlan-perst-hog {
360 gpio-hog;
361 gpios = <6 GPIO_ACTIVE_LOW>;
362 output-low;
363 line-name = "WLAN_PERST#";
364 };
365 };
366
367 expander2: gpio@72 {
368 compatible = "nxp,pca9538";
369 reg = <0x72>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 vcc-supply = <®_3v3>;
373 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
374 "LCD_BL_EN", "DP_EN",
375 "MIPI_CSI_EN", "MIPI_CSI_RST#",
376 "USER_LED1", "USER_LED2";
377 };
378 };
379
380 &lpi2c5 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 clock-frequency = <400000>;
384 pinctrl-names = "default", "sleep";
385 pinctrl-0 = <&pinctrl_lpi2c5>;
386 pinctrl-1 = <&pinctrl_lpi2c5>;
387 status = "okay";
388
389 dp_bridge: dp-bridge@f {
390 compatible = "toshiba,tc9595", "toshiba,tc358767";
391 reg = <0x0f>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_tc9595>;
394 clock-names = "ref";
395 clocks = <&clk_dp>;
396 reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
397 interrupt-parent = <&gpio4>;
398 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
399 toshiba,hpd-pin = <0>;
400 status = "disabled";
401
402 ports {
403 #address-cells = <1>;
404 #size-cells = <0>;
405
406 port@0 {
407 reg = <0>;
408
409 dp_dsi_in: endpoint {
410 data-lanes = <1 2 3 4>;
411 };
412 };
413 };
414 };
415 };
416
417 &lpuart1 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_uart1>;
420 status = "okay";
421 };
422
423 &lpuart2 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart2>;
426 linux,rs485-enabled-at-boot-time;
427 status = "okay";
428 };
429
430 /* disabled per default, console for M33 */
431 &lpuart3 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_uart3>;
434 status = "disabled";
435 };
436
437 &lpuart6 {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_uart6>;
440 status = "okay";
441 };
442
443 &lpuart8 {
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_uart8>;
446 status = "okay";
447 };
448
449 &pcf85063 {
450 /* RTC_EVENT# is connected on MBa93xxLA */
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_pcf85063>;
453 interrupt-parent = <&gpio1>;
454 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
455 };
456
457 &tpm5 {
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_tpm5>;
460 };
461
462 &usbotg1 {
463 dr_mode = "otg";
464 hnp-disable;
465 srp-disable;
466 adp-disable;
467 usb-role-switch;
468 disable-over-current;
469 samsung,picophy-pre-emp-curr-control = <3>;
470 samsung,picophy-dc-vol-level-adjust = <7>;
471 status = "okay";
472
473 port {
474 typec_hs: endpoint {
475 remote-endpoint = <&typec_con_hs>;
476 };
477 };
478 };
479
480 &usbotg2 {
481 dr_mode = "host";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 disable-over-current;
485 samsung,picophy-pre-emp-curr-control = <3>;
486 samsung,picophy-dc-vol-level-adjust = <7>;
487 status = "okay";
488
489 hub_2_0: hub@1 {
490 compatible = "usb424,2517";
491 reg = <1>;
492 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
493 vdd-supply = <®_3v3>;
494 };
495 };
496
497 &usdhc2 {
498 pinctrl-names = "default", "state_100mhz", "state_200mhz";
499 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
500 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
501 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
502 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
503 vmmc-supply = <®_usdhc2_vmmc>;
504 bus-width = <4>;
505 no-sdio;
506 no-mmc;
507 disable-wp;
508 status = "okay";
509 };
510
511 &iomuxc {
512 pinctrl_eqos: eqosgrp {
513 fsl,pins = <
514 /* PD | FSEL_2 | DSE X4 */
515 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
516 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
517 /* PD | FSEL_2 | DSE X6 */
518 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
519 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
520 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
521 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
522 /* PD | FSEL_3 | DSE X6 */
523 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
524 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
525 /* PD | FSEL_2 | DSE X4 */
526 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
527 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
528 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
529 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
530 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
531 /* PD | FSEL_3 | DSE X3 */
532 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
533 >;
534 };
535
536 pinctrl_eqos_phy: eqosphygrp {
537 fsl,pins = <
538 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
539 >;
540 };
541
542 pinctrl_fec: fecgrp {
543 fsl,pins = <
544 /* PD | FSEL_2 | DSE X4 */
545 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
546 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
547 /* PD | FSEL_2 | DSE X6 */
548 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
549 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
550 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
551 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
552 /* PD | FSEL_3 | DSE X6 */
553 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
554 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
555 /* PD | FSEL_2 | DSE X4 */
556 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
557 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
558 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
559 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
560 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
561 /* PD | FSEL_3 | DSE X3 */
562 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
563 >;
564 };
565
566 pinctrl_fec_phy: fecphygrp {
567 fsl,pins = <
568 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
569 >;
570 };
571
572 pinctrl_flexcan1: flexcan1grp {
573 fsl,pins = <
574 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
575 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
576 >;
577 };
578
579 pinctrl_flexcan2: flexcan2grp {
580 fsl,pins = <
581 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
582 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
583 >;
584 };
585
586 pinctrl_lpi2c3: lpi2c3grp {
587 fsl,pins = <
588 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
589 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
590 >;
591 };
592
593 pinctrl_lpi2c5: lpi2c5grp {
594 fsl,pins = <
595 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
596 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
597 >;
598 };
599
600 pinctrl_pcf85063: pcf85063grp {
601 fsl,pins = <
602 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306
603 >;
604 };
605
606 pinctrl_pexp_irq: pexpirqgrp {
607 fsl,pins = <
608 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
609 >;
610 };
611
612 pinctrl_tc9595: tc9595-grp {
613 fsl,pins = <
614 /* DP_IRQ */
615 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1306
616 >;
617 };
618
619 pinctrl_tpm5: tpm5grp {
620 fsl,pins = <
621 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
622 >;
623 };
624
625 pinctrl_typec: typecgrp {
626 fsl,pins = <
627 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
628 >;
629 };
630
631 pinctrl_uart1: uart1grp {
632 fsl,pins = <
633 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
634 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
635 >;
636 };
637
638 pinctrl_uart2: uart2grp {
639 fsl,pins = <
640 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
641 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
642 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
643 >;
644 };
645
646 pinctrl_uart3: uart3grp {
647 fsl,pins = <
648 MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
649 MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
650 >;
651 };
652
653 pinctrl_uart6: uart6grp {
654 fsl,pins = <
655 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
656 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
657 >;
658 };
659
660 pinctrl_uart8: uart8grp {
661 fsl,pins = <
662 MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
663 MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
664 >;
665 };
666
667 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
668 fsl,pins = <
669 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
670 >;
671 };
672
673 pinctrl_usdhc2_hs: usdhc2hsgrp {
674 fsl,pins = <
675 /* HYS | PD | PU | FSEL_3 | DSE X5 */
676 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
677 /* HYS | PD | PU | FSEL_3 | DSE X4 */
678 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
679 /* HYS | PD | PU | FSEL_3 | DSE X3 */
680 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
681 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
682 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
683 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
684 /* PD | PU | FSEL_2 | DSE X3 */
685 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
686 >;
687 };
688
689 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
690 fsl,pins = <
691 /* HYS | PD | PU | FSEL_3 | DSE X6 */
692 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
693 /* HYS | PD | PU | FSEL_3 | DSE X4 */
694 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
695 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
696 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
697 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
698 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
699 /* PD | PU | FSEL_2 | DSE X3 */
700 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
701 >;
702 };
703 };
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