1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2022 NXP
4 */
5
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/fsl,imx93-power.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 #include "imx93-pinfunc.h"
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 i2c0 = &lpi2c1;
27 i2c1 = &lpi2c2;
28 i2c2 = &lpi2c3;
29 i2c3 = &lpi2c4;
30 i2c4 = &lpi2c5;
31 i2c5 = &lpi2c6;
32 i2c6 = &lpi2c7;
33 i2c7 = &lpi2c8;
34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 serial0 = &lpuart1;
38 serial1 = &lpuart2;
39 serial2 = &lpuart3;
40 serial3 = &lpuart4;
41 serial4 = &lpuart5;
42 serial5 = &lpuart6;
43 serial6 = &lpuart7;
44 serial7 = &lpuart8;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 idle-states {
52 entry-method = "psci";
53
54 cpu_pd_wait: cpu-pd-wait {
55 compatible = "arm,idle-state";
56 arm,psci-suspend-param = <0x0010033>;
57 local-timer-stop;
58 entry-latency-us = <10000>;
59 exit-latency-us = <7000>;
60 min-residency-us = <27000>;
61 wakeup-latency-us = <15000>;
62 };
63 };
64
65 A55_0: cpu@0 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a55";
68 reg = <0x0>;
69 enable-method = "psci";
70 #cooling-cells = <2>;
71 cpu-idle-states = <&cpu_pd_wait>;
72 i-cache-size = <32768>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <128>;
75 d-cache-size = <32768>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&l2_cache_l0>;
79 };
80
81 A55_1: cpu@100 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a55";
84 reg = <0x100>;
85 enable-method = "psci";
86 #cooling-cells = <2>;
87 cpu-idle-states = <&cpu_pd_wait>;
88 i-cache-size = <32768>;
89 i-cache-line-size = <64>;
90 i-cache-sets = <128>;
91 d-cache-size = <32768>;
92 d-cache-line-size = <64>;
93 d-cache-sets = <128>;
94 next-level-cache = <&l2_cache_l1>;
95 };
96
97 l2_cache_l0: l2-cache-l0 {
98 compatible = "cache";
99 cache-size = <65536>;
100 cache-line-size = <64>;
101 cache-sets = <256>;
102 cache-level = <2>;
103 cache-unified;
104 next-level-cache = <&l3_cache>;
105 };
106
107 l2_cache_l1: l2-cache-l1 {
108 compatible = "cache";
109 cache-size = <65536>;
110 cache-line-size = <64>;
111 cache-sets = <256>;
112 cache-level = <2>;
113 cache-unified;
114 next-level-cache = <&l3_cache>;
115 };
116
117 l3_cache: l3-cache {
118 compatible = "cache";
119 cache-size = <262144>;
120 cache-line-size = <64>;
121 cache-sets = <256>;
122 cache-level = <3>;
123 cache-unified;
124 };
125 };
126
127 osc_32k: clock-osc-32k {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <32768>;
131 clock-output-names = "osc_32k";
132 };
133
134 osc_24m: clock-osc-24m {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <24000000>;
138 clock-output-names = "osc_24m";
139 };
140
141 clk_ext1: clock-ext1 {
142 compatible = "fixed-clock";
143 #clock-cells = <0>;
144 clock-frequency = <133000000>;
145 clock-output-names = "clk_ext1";
146 };
147
148 pmu {
149 compatible = "arm,cortex-a55-pmu";
150 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
151 };
152
153 psci {
154 compatible = "arm,psci-1.0";
155 method = "smc";
156 };
157
158 timer {
159 compatible = "arm,armv8-timer";
160 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
161 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
162 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
164 clock-frequency = <24000000>;
165 arm,no-tick-in-suspend;
166 interrupt-parent = <&gic>;
167 };
168
169 gic: interrupt-controller@48000000 {
170 compatible = "arm,gic-v3";
171 reg = <0 0x48000000 0 0x10000>,
172 <0 0x48040000 0 0xc0000>;
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-parent = <&gic>;
177 };
178
179 thermal-zones {
180 cpu-thermal {
181 polling-delay-passive = <250>;
182 polling-delay = <2000>;
183
184 thermal-sensors = <&tmu 0>;
185
186 trips {
187 cpu_alert: cpu-alert {
188 temperature = <80000>;
189 hysteresis = <2000>;
190 type = "passive";
191 };
192
193 cpu_crit: cpu-crit {
194 temperature = <90000>;
195 hysteresis = <2000>;
196 type = "critical";
197 };
198 };
199
200 cooling-maps {
201 map0 {
202 trip = <&cpu_alert>;
203 cooling-device =
204 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
205 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
206 };
207 };
208 };
209 };
210
211 cm33: remoteproc-cm33 {
212 compatible = "fsl,imx93-cm33";
213 clocks = <&clk IMX93_CLK_CM33_GATE>;
214 status = "disabled";
215 };
216
217 mqs1: mqs1 {
218 compatible = "fsl,imx93-mqs";
219 gpr = <&aonmix_ns_gpr>;
220 status = "disabled";
221 };
222
223 mqs2: mqs2 {
224 compatible = "fsl,imx93-mqs";
225 gpr = <&wakeupmix_gpr>;
226 status = "disabled";
227 };
228
229 usbphynop1: usbphynop1 {
230 compatible = "usb-nop-xceiv";
231 #phy-cells = <0>;
232 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
233 clock-names = "main_clk";
234 };
235
236 usbphynop2: usbphynop2 {
237 compatible = "usb-nop-xceiv";
238 #phy-cells = <0>;
239 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
240 clock-names = "main_clk";
241 };
242
243 soc@0 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x80000000>,
248 <0x28000000 0x0 0x28000000 0x10000000>;
249
250 aips1: bus@44000000 {
251 compatible = "fsl,aips-bus", "simple-bus";
252 reg = <0x44000000 0x800000>;
253 #address-cells = <1>;
254 #size-cells = <1>;
255 ranges;
256
257 edma1: dma-controller@44000000 {
258 compatible = "fsl,imx93-edma3";
259 reg = <0x44000000 0x200000>;
260 #dma-cells = <3>;
261 dma-channels = <31>;
262 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved
263 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1
264 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved
265 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0
266 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1
267 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus
268 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus
269 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX
270 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX
271 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX
272 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX
273 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX
274 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX
275 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX
276 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX
277 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1
278 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX
279 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX
280 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX
281 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX
282 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400
283 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX
284 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX
285 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2
286 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3
287 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow
288 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2
289 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3
290 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow
291 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM
292 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1
293 clocks = <&clk IMX93_CLK_EDMA1_GATE>;
294 clock-names = "dma";
295 };
296
297 aonmix_ns_gpr: syscon@44210000 {
298 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
299 reg = <0x44210000 0x1000>;
300 };
301
302 mu1: mailbox@44230000 {
303 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
304 reg = <0x44230000 0x10000>;
305 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clk IMX93_CLK_MU1_B_GATE>;
307 #mbox-cells = <2>;
308 status = "disabled";
309 };
310
311 system_counter: timer@44290000 {
312 compatible = "nxp,sysctr-timer";
313 reg = <0x44290000 0x30000>;
314 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&osc_24m>;
316 clock-names = "per";
317 nxp,no-divider;
318 };
319
320 wdog1: watchdog@442d0000 {
321 compatible = "fsl,imx93-wdt";
322 reg = <0x442d0000 0x10000>;
323 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clk IMX93_CLK_WDOG1_GATE>;
325 timeout-sec = <40>;
326 status = "disabled";
327 };
328
329 wdog2: watchdog@442e0000 {
330 compatible = "fsl,imx93-wdt";
331 reg = <0x442e0000 0x10000>;
332 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clk IMX93_CLK_WDOG2_GATE>;
334 timeout-sec = <40>;
335 status = "disabled";
336 };
337
338 tpm1: pwm@44310000 {
339 compatible = "fsl,imx7ulp-pwm";
340 reg = <0x44310000 0x1000>;
341 clocks = <&clk IMX93_CLK_TPM1_GATE>;
342 #pwm-cells = <3>;
343 status = "disabled";
344 };
345
346 tpm2: pwm@44320000 {
347 compatible = "fsl,imx7ulp-pwm";
348 reg = <0x44320000 0x10000>;
349 clocks = <&clk IMX93_CLK_TPM2_GATE>;
350 #pwm-cells = <3>;
351 status = "disabled";
352 };
353
354 i3c1: i3c@44330000 {
355 compatible = "silvaco,i3c-master-v1";
356 reg = <0x44330000 0x10000>;
357 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <3>;
359 #size-cells = <0>;
360 clocks = <&clk IMX93_CLK_BUS_AON>,
361 <&clk IMX93_CLK_I3C1_GATE>,
362 <&clk IMX93_CLK_I3C1_SLOW>;
363 clock-names = "pclk", "fast_clk", "slow_clk";
364 status = "disabled";
365 };
366
367 lpi2c1: i2c@44340000 {
368 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
369 reg = <0x44340000 0x10000>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
374 <&clk IMX93_CLK_BUS_AON>;
375 clock-names = "per", "ipg";
376 dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>;
377 dma-names = "tx", "rx";
378 status = "disabled";
379 };
380
381 lpi2c2: i2c@44350000 {
382 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
383 reg = <0x44350000 0x10000>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
388 <&clk IMX93_CLK_BUS_AON>;
389 clock-names = "per", "ipg";
390 dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>;
391 dma-names = "tx", "rx";
392 status = "disabled";
393 };
394
395 lpspi1: spi@44360000 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
399 reg = <0x44360000 0x10000>;
400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
402 <&clk IMX93_CLK_BUS_AON>;
403 clock-names = "per", "ipg";
404 dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>;
405 dma-names = "tx", "rx";
406 status = "disabled";
407 };
408
409 lpspi2: spi@44370000 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
413 reg = <0x44370000 0x10000>;
414 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
416 <&clk IMX93_CLK_BUS_AON>;
417 clock-names = "per", "ipg";
418 dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>;
419 dma-names = "tx", "rx";
420 status = "disabled";
421 };
422
423 lpuart1: serial@44380000 {
424 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
425 reg = <0x44380000 0x1000>;
426 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
428 clock-names = "ipg";
429 dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>;
430 dma-names = "rx", "tx";
431 status = "disabled";
432 };
433
434 lpuart2: serial@44390000 {
435 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
436 reg = <0x44390000 0x1000>;
437 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
439 clock-names = "ipg";
440 dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>;
441 dma-names = "rx", "tx";
442 status = "disabled";
443 };
444
445 flexcan1: can@443a0000 {
446 compatible = "fsl,imx93-flexcan";
447 reg = <0x443a0000 0x10000>;
448 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk IMX93_CLK_BUS_AON>,
450 <&clk IMX93_CLK_CAN1_GATE>;
451 clock-names = "ipg", "per";
452 assigned-clocks = <&clk IMX93_CLK_CAN1>;
453 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
454 assigned-clock-rates = <40000000>;
455 fsl,clk-source = /bits/ 8 <0>;
456 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
457 status = "disabled";
458 };
459
460 sai1: sai@443b0000 {
461 compatible = "fsl,imx93-sai";
462 reg = <0x443b0000 0x10000>;
463 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
465 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
466 <&clk IMX93_CLK_DUMMY>;
467 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
468 dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>;
469 dma-names = "rx", "tx";
470 #sound-dai-cells = <0>;
471 status = "disabled";
472 };
473
474 iomuxc: pinctrl@443c0000 {
475 compatible = "fsl,imx93-iomuxc";
476 reg = <0x443c0000 0x10000>;
477 status = "okay";
478 };
479
480 bbnsm: bbnsm@44440000 {
481 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
482 reg = <0x44440000 0x10000>;
483
484 bbnsm_rtc: rtc {
485 compatible = "nxp,imx93-bbnsm-rtc";
486 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 };
488
489 bbnsm_pwrkey: pwrkey {
490 compatible = "nxp,imx93-bbnsm-pwrkey";
491 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
492 linux,code = <KEY_POWER>;
493 };
494 };
495
496 clk: clock-controller@44450000 {
497 compatible = "fsl,imx93-ccm";
498 reg = <0x44450000 0x10000>;
499 #clock-cells = <1>;
500 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
501 clock-names = "osc_32k", "osc_24m", "clk_ext1";
502 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
503 assigned-clock-rates = <393216000>;
504 status = "okay";
505 };
506
507 src: system-controller@44460000 {
508 compatible = "fsl,imx93-src", "syscon";
509 reg = <0x44460000 0x10000>;
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges;
513
514 mlmix: power-domain@44461800 {
515 compatible = "fsl,imx93-src-slice";
516 reg = <0x44461800 0x400>, <0x44464800 0x400>;
517 #power-domain-cells = <0>;
518 clocks = <&clk IMX93_CLK_ML_APB>,
519 <&clk IMX93_CLK_ML>;
520 };
521
522 mediamix: power-domain@44462400 {
523 compatible = "fsl,imx93-src-slice";
524 reg = <0x44462400 0x400>, <0x44465800 0x400>;
525 #power-domain-cells = <0>;
526 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>,
527 <&clk IMX93_CLK_MEDIA_APB>;
528 };
529 };
530
531 clock-controller@44480000 {
532 compatible = "fsl,imx93-anatop";
533 reg = <0x44480000 0x2000>;
534 #clock-cells = <1>;
535 };
536
537 tmu: tmu@44482000 {
538 compatible = "fsl,qoriq-tmu";
539 reg = <0x44482000 0x1000>;
540 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clk IMX93_CLK_TMC_GATE>;
542 little-endian;
543 fsl,tmu-range = <0x800000da 0x800000e9
544 0x80000102 0x8000012a
545 0x80000166 0x800001a7
546 0x800001b6>;
547 fsl,tmu-calibration = <0x00000000 0x0000000e
548 0x00000001 0x00000029
549 0x00000002 0x00000056
550 0x00000003 0x000000a2
551 0x00000004 0x00000116
552 0x00000005 0x00000195
553 0x00000006 0x000001b2>;
554 #thermal-sensor-cells = <1>;
555 };
556
557 micfil: micfil@44520000 {
558 compatible = "fsl,imx93-micfil";
559 reg = <0x44520000 0x10000>;
560 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clk IMX93_CLK_PDM_IPG>,
565 <&clk IMX93_CLK_PDM_GATE>,
566 <&clk IMX93_CLK_AUDIO_PLL>;
567 clock-names = "ipg_clk", "ipg_clk_app", "pll8k";
568 dmas = <&edma1 29 0 5>;
569 dma-names = "rx";
570 #sound-dai-cells = <0>;
571 status = "disabled";
572 };
573
574 adc1: adc@44530000 {
575 compatible = "nxp,imx93-adc";
576 reg = <0x44530000 0x10000>;
577 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&clk IMX93_CLK_ADC1_GATE>;
581 clock-names = "ipg";
582 #io-channel-cells = <1>;
583 status = "disabled";
584 };
585 };
586
587 aips2: bus@42000000 {
588 compatible = "fsl,aips-bus", "simple-bus";
589 reg = <0x42000000 0x800000>;
590 #address-cells = <1>;
591 #size-cells = <1>;
592 ranges;
593
594 edma2: dma-controller@42000000 {
595 compatible = "fsl,imx93-edma4";
596 reg = <0x42000000 0x210000>;
597 #dma-cells = <3>;
598 dma-channels = <64>;
599 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clk IMX93_CLK_EDMA2_GATE>;
664 clock-names = "dma";
665 };
666
667 wakeupmix_gpr: syscon@42420000 {
668 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
669 reg = <0x42420000 0x1000>;
670 };
671
672 mu2: mailbox@42440000 {
673 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
674 reg = <0x42440000 0x10000>;
675 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clk IMX93_CLK_MU2_B_GATE>;
677 #mbox-cells = <2>;
678 status = "disabled";
679 };
680
681 wdog3: watchdog@42490000 {
682 compatible = "fsl,imx93-wdt";
683 reg = <0x42490000 0x10000>;
684 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clk IMX93_CLK_WDOG3_GATE>;
686 timeout-sec = <40>;
687 status = "disabled";
688 };
689
690 wdog4: watchdog@424a0000 {
691 compatible = "fsl,imx93-wdt";
692 reg = <0x424a0000 0x10000>;
693 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clk IMX93_CLK_WDOG4_GATE>;
695 timeout-sec = <40>;
696 status = "disabled";
697 };
698
699 wdog5: watchdog@424b0000 {
700 compatible = "fsl,imx93-wdt";
701 reg = <0x424b0000 0x10000>;
702 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clk IMX93_CLK_WDOG5_GATE>;
704 timeout-sec = <40>;
705 status = "disabled";
706 };
707
708 tpm3: pwm@424e0000 {
709 compatible = "fsl,imx7ulp-pwm";
710 reg = <0x424e0000 0x1000>;
711 clocks = <&clk IMX93_CLK_TPM3_GATE>;
712 #pwm-cells = <3>;
713 status = "disabled";
714 };
715
716 tpm4: pwm@424f0000 {
717 compatible = "fsl,imx7ulp-pwm";
718 reg = <0x424f0000 0x10000>;
719 clocks = <&clk IMX93_CLK_TPM4_GATE>;
720 #pwm-cells = <3>;
721 status = "disabled";
722 };
723
724 tpm5: pwm@42500000 {
725 compatible = "fsl,imx7ulp-pwm";
726 reg = <0x42500000 0x10000>;
727 clocks = <&clk IMX93_CLK_TPM5_GATE>;
728 #pwm-cells = <3>;
729 status = "disabled";
730 };
731
732 tpm6: pwm@42510000 {
733 compatible = "fsl,imx7ulp-pwm";
734 reg = <0x42510000 0x10000>;
735 clocks = <&clk IMX93_CLK_TPM6_GATE>;
736 #pwm-cells = <3>;
737 status = "disabled";
738 };
739
740 i3c2: i3c@42520000 {
741 compatible = "silvaco,i3c-master-v1";
742 reg = <0x42520000 0x10000>;
743 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
744 #address-cells = <3>;
745 #size-cells = <0>;
746 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
747 <&clk IMX93_CLK_I3C2_GATE>,
748 <&clk IMX93_CLK_I3C2_SLOW>;
749 clock-names = "pclk", "fast_clk", "slow_clk";
750 status = "disabled";
751 };
752
753 lpi2c3: i2c@42530000 {
754 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
755 reg = <0x42530000 0x10000>;
756 #address-cells = <1>;
757 #size-cells = <0>;
758 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
760 <&clk IMX93_CLK_BUS_WAKEUP>;
761 clock-names = "per", "ipg";
762 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
763 dma-names = "tx", "rx";
764 status = "disabled";
765 };
766
767 lpi2c4: i2c@42540000 {
768 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
769 reg = <0x42540000 0x10000>;
770 #address-cells = <1>;
771 #size-cells = <0>;
772 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
774 <&clk IMX93_CLK_BUS_WAKEUP>;
775 clock-names = "per", "ipg";
776 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
777 dma-names = "tx", "rx";
778 status = "disabled";
779 };
780
781 lpspi3: spi@42550000 {
782 #address-cells = <1>;
783 #size-cells = <0>;
784 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
785 reg = <0x42550000 0x10000>;
786 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
788 <&clk IMX93_CLK_BUS_WAKEUP>;
789 clock-names = "per", "ipg";
790 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
791 dma-names = "tx", "rx";
792 status = "disabled";
793 };
794
795 lpspi4: spi@42560000 {
796 #address-cells = <1>;
797 #size-cells = <0>;
798 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
799 reg = <0x42560000 0x10000>;
800 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
802 <&clk IMX93_CLK_BUS_WAKEUP>;
803 clock-names = "per", "ipg";
804 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
805 dma-names = "tx", "rx";
806 status = "disabled";
807 };
808
809 lpuart3: serial@42570000 {
810 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
811 reg = <0x42570000 0x1000>;
812 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
814 clock-names = "ipg";
815 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
816 dma-names = "rx", "tx";
817 status = "disabled";
818 };
819
820 lpuart4: serial@42580000 {
821 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
822 reg = <0x42580000 0x1000>;
823 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
825 clock-names = "ipg";
826 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
827 dma-names = "rx", "tx";
828 status = "disabled";
829 };
830
831 lpuart5: serial@42590000 {
832 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
833 reg = <0x42590000 0x1000>;
834 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
836 clock-names = "ipg";
837 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
838 dma-names = "rx", "tx";
839 status = "disabled";
840 };
841
842 lpuart6: serial@425a0000 {
843 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
844 reg = <0x425a0000 0x1000>;
845 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
847 clock-names = "ipg";
848 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
849 dma-names = "rx", "tx";
850 status = "disabled";
851 };
852
853 flexcan2: can@425b0000 {
854 compatible = "fsl,imx93-flexcan";
855 reg = <0x425b0000 0x10000>;
856 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
858 <&clk IMX93_CLK_CAN2_GATE>;
859 clock-names = "ipg", "per";
860 assigned-clocks = <&clk IMX93_CLK_CAN2>;
861 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
862 assigned-clock-rates = <40000000>;
863 fsl,clk-source = /bits/ 8 <0>;
864 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
865 status = "disabled";
866 };
867
868 flexspi1: spi@425e0000 {
869 compatible = "nxp,imx8mm-fspi";
870 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
871 reg-names = "fspi_base", "fspi_mmap";
872 #address-cells = <1>;
873 #size-cells = <0>;
874 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
876 <&clk IMX93_CLK_FLEXSPI1_GATE>;
877 clock-names = "fspi_en", "fspi";
878 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
879 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
880 status = "disabled";
881 };
882
883 sai2: sai@42650000 {
884 compatible = "fsl,imx93-sai";
885 reg = <0x42650000 0x10000>;
886 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>,
888 <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>,
889 <&clk IMX93_CLK_DUMMY>;
890 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
891 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>;
892 dma-names = "rx", "tx";
893 #sound-dai-cells = <0>;
894 status = "disabled";
895 };
896
897 sai3: sai@42660000 {
898 compatible = "fsl,imx93-sai";
899 reg = <0x42660000 0x10000>;
900 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>,
902 <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>,
903 <&clk IMX93_CLK_DUMMY>;
904 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
905 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>;
906 dma-names = "rx", "tx";
907 #sound-dai-cells = <0>;
908 status = "disabled";
909 };
910
911 xcvr: xcvr@42680000 {
912 compatible = "fsl,imx93-xcvr";
913 reg = <0x42680000 0x800>,
914 <0x42680800 0x400>,
915 <0x42680c00 0x080>,
916 <0x42680e00 0x080>;
917 reg-names = "ram", "regs", "rxfifo", "txfifo";
918 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
921 <&clk IMX93_CLK_SPDIF_GATE>,
922 <&clk IMX93_CLK_DUMMY>,
923 <&clk IMX93_CLK_AUD_XCVR_GATE>;
924 clock-names = "ipg", "phy", "spba", "pll_ipg";
925 dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>;
926 dma-names = "rx", "tx";
927 #sound-dai-cells = <0>;
928 status = "disabled";
929 };
930
931 lpuart7: serial@42690000 {
932 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
933 reg = <0x42690000 0x1000>;
934 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
936 clock-names = "ipg";
937 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>;
938 dma-names = "rx", "tx";
939 status = "disabled";
940 };
941
942 lpuart8: serial@426a0000 {
943 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
944 reg = <0x426a0000 0x1000>;
945 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
947 clock-names = "ipg";
948 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>;
949 dma-names = "rx", "tx";
950 status = "disabled";
951 };
952
953 lpi2c5: i2c@426b0000 {
954 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
955 reg = <0x426b0000 0x10000>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
960 <&clk IMX93_CLK_BUS_WAKEUP>;
961 clock-names = "per", "ipg";
962 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
963 dma-names = "tx", "rx";
964 status = "disabled";
965 };
966
967 lpi2c6: i2c@426c0000 {
968 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
969 reg = <0x426c0000 0x10000>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
974 <&clk IMX93_CLK_BUS_WAKEUP>;
975 clock-names = "per", "ipg";
976 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
977 dma-names = "tx", "rx";
978 status = "disabled";
979 };
980
981 lpi2c7: i2c@426d0000 {
982 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
983 reg = <0x426d0000 0x10000>;
984 #address-cells = <1>;
985 #size-cells = <0>;
986 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
988 <&clk IMX93_CLK_BUS_WAKEUP>;
989 clock-names = "per", "ipg";
990 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
991 dma-names = "tx", "rx";
992 status = "disabled";
993 };
994
995 lpi2c8: i2c@426e0000 {
996 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
997 reg = <0x426e0000 0x10000>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1000 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
1002 <&clk IMX93_CLK_BUS_WAKEUP>;
1003 clock-names = "per", "ipg";
1004 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
1005 dma-names = "tx", "rx";
1006 status = "disabled";
1007 };
1008
1009 lpspi5: spi@426f0000 {
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
1013 reg = <0x426f0000 0x10000>;
1014 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
1016 <&clk IMX93_CLK_BUS_WAKEUP>;
1017 clock-names = "per", "ipg";
1018 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
1019 dma-names = "tx", "rx";
1020 status = "disabled";
1021 };
1022
1023 lpspi6: spi@42700000 {
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
1027 reg = <0x42700000 0x10000>;
1028 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
1030 <&clk IMX93_CLK_BUS_WAKEUP>;
1031 clock-names = "per", "ipg";
1032 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
1033 dma-names = "tx", "rx";
1034 status = "disabled";
1035 };
1036
1037 lpspi7: spi@42710000 {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
1041 reg = <0x42710000 0x10000>;
1042 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
1044 <&clk IMX93_CLK_BUS_WAKEUP>;
1045 clock-names = "per", "ipg";
1046 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
1047 dma-names = "tx", "rx";
1048 status = "disabled";
1049 };
1050
1051 lpspi8: spi@42720000 {
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
1055 reg = <0x42720000 0x10000>;
1056 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
1058 <&clk IMX93_CLK_BUS_WAKEUP>;
1059 clock-names = "per", "ipg";
1060 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
1061 dma-names = "tx", "rx";
1062 status = "disabled";
1063 };
1064
1065 };
1066
1067 aips3: bus@42800000 {
1068 compatible = "fsl,aips-bus", "simple-bus";
1069 reg = <0x42800000 0x800000>;
1070 #address-cells = <1>;
1071 #size-cells = <1>;
1072 ranges;
1073
1074 usdhc1: mmc@42850000 {
1075 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
1076 reg = <0x42850000 0x10000>;
1077 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
1079 <&clk IMX93_CLK_WAKEUP_AXI>,
1080 <&clk IMX93_CLK_USDHC1_GATE>;
1081 clock-names = "ipg", "ahb", "per";
1082 assigned-clocks = <&clk IMX93_CLK_USDHC1>;
1083 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
1084 assigned-clock-rates = <400000000>;
1085 bus-width = <8>;
1086 fsl,tuning-start-tap = <1>;
1087 fsl,tuning-step = <2>;
1088 status = "disabled";
1089 };
1090
1091 usdhc2: mmc@42860000 {
1092 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
1093 reg = <0x42860000 0x10000>;
1094 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
1096 <&clk IMX93_CLK_WAKEUP_AXI>,
1097 <&clk IMX93_CLK_USDHC2_GATE>;
1098 clock-names = "ipg", "ahb", "per";
1099 assigned-clocks = <&clk IMX93_CLK_USDHC2>;
1100 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
1101 assigned-clock-rates = <400000000>;
1102 bus-width = <4>;
1103 fsl,tuning-start-tap = <1>;
1104 fsl,tuning-step = <2>;
1105 status = "disabled";
1106 };
1107
1108 fec: ethernet@42890000 {
1109 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1110 reg = <0x42890000 0x10000>;
1111 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&clk IMX93_CLK_ENET1_GATE>,
1116 <&clk IMX93_CLK_ENET1_GATE>,
1117 <&clk IMX93_CLK_ENET_TIMER1>,
1118 <&clk IMX93_CLK_ENET_REF>,
1119 <&clk IMX93_CLK_ENET_REF_PHY>;
1120 clock-names = "ipg", "ahb", "ptp",
1121 "enet_clk_ref", "enet_out";
1122 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
1123 <&clk IMX93_CLK_ENET_REF>,
1124 <&clk IMX93_CLK_ENET_REF_PHY>;
1125 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
1126 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
1127 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
1128 assigned-clock-rates = <100000000>, <250000000>, <50000000>;
1129 fsl,num-tx-queues = <3>;
1130 fsl,num-rx-queues = <3>;
1131 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
1132 nvmem-cells = <ð_mac1>;
1133 nvmem-cell-names = "mac-address";
1134 status = "disabled";
1135 };
1136
1137 eqos: ethernet@428a0000 {
1138 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
1139 reg = <0x428a0000 0x10000>;
1140 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1142 interrupt-names = "macirq", "eth_wake_irq";
1143 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
1144 <&clk IMX93_CLK_ENET_QOS_GATE>,
1145 <&clk IMX93_CLK_ENET_TIMER2>,
1146 <&clk IMX93_CLK_ENET>,
1147 <&clk IMX93_CLK_ENET_QOS_GATE>;
1148 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
1149 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
1150 <&clk IMX93_CLK_ENET>;
1151 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
1152 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
1153 assigned-clock-rates = <100000000>, <250000000>;
1154 intf_mode = <&wakeupmix_gpr 0x28>;
1155 snps,clk-csr = <6>;
1156 nvmem-cells = <ð_mac2>;
1157 nvmem-cell-names = "mac-address";
1158 status = "disabled";
1159 };
1160
1161 usdhc3: mmc@428b0000 {
1162 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
1163 reg = <0x428b0000 0x10000>;
1164 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
1166 <&clk IMX93_CLK_WAKEUP_AXI>,
1167 <&clk IMX93_CLK_USDHC3_GATE>;
1168 clock-names = "ipg", "ahb", "per";
1169 assigned-clocks = <&clk IMX93_CLK_USDHC3>;
1170 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
1171 assigned-clock-rates = <400000000>;
1172 bus-width = <4>;
1173 fsl,tuning-start-tap = <1>;
1174 fsl,tuning-step = <2>;
1175 status = "disabled";
1176 };
1177 };
1178
1179 gpio2: gpio@43810000 {
1180 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1181 reg = <0x43810000 0x1000>;
1182 gpio-controller;
1183 #gpio-cells = <2>;
1184 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1186 interrupt-controller;
1187 #interrupt-cells = <2>;
1188 clocks = <&clk IMX93_CLK_GPIO2_GATE>,
1189 <&clk IMX93_CLK_GPIO2_GATE>;
1190 clock-names = "gpio", "port";
1191 gpio-ranges = <&iomuxc 0 4 30>;
1192 };
1193
1194 gpio3: gpio@43820000 {
1195 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1196 reg = <0x43820000 0x1000>;
1197 gpio-controller;
1198 #gpio-cells = <2>;
1199 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1201 interrupt-controller;
1202 #interrupt-cells = <2>;
1203 clocks = <&clk IMX93_CLK_GPIO3_GATE>,
1204 <&clk IMX93_CLK_GPIO3_GATE>;
1205 clock-names = "gpio", "port";
1206 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
1207 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
1208 };
1209
1210 gpio4: gpio@43830000 {
1211 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1212 reg = <0x43830000 0x1000>;
1213 gpio-controller;
1214 #gpio-cells = <2>;
1215 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1217 interrupt-controller;
1218 #interrupt-cells = <2>;
1219 clocks = <&clk IMX93_CLK_GPIO4_GATE>,
1220 <&clk IMX93_CLK_GPIO4_GATE>;
1221 clock-names = "gpio", "port";
1222 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
1223 };
1224
1225 gpio1: gpio@47400000 {
1226 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1227 reg = <0x47400000 0x1000>;
1228 gpio-controller;
1229 #gpio-cells = <2>;
1230 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1232 interrupt-controller;
1233 #interrupt-cells = <2>;
1234 clocks = <&clk IMX93_CLK_GPIO1_GATE>,
1235 <&clk IMX93_CLK_GPIO1_GATE>;
1236 clock-names = "gpio", "port";
1237 gpio-ranges = <&iomuxc 0 92 16>;
1238 };
1239
1240 ocotp: efuse@47510000 {
1241 compatible = "fsl,imx93-ocotp", "syscon";
1242 reg = <0x47510000 0x10000>;
1243 #address-cells = <1>;
1244 #size-cells = <1>;
1245
1246 eth_mac1: mac-address@4ec {
1247 reg = <0x4ec 0x6>;
1248 };
1249
1250 eth_mac2: mac-address@4f2 {
1251 reg = <0x4f2 0x6>;
1252 };
1253
1254 };
1255
1256 s4muap: mailbox@47520000 {
1257 compatible = "fsl,imx93-mu-s4";
1258 reg = <0x47520000 0x10000>;
1259 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1261 interrupt-names = "tx", "rx";
1262 #mbox-cells = <2>;
1263 };
1264
1265 media_blk_ctrl: system-controller@4ac10000 {
1266 compatible = "fsl,imx93-media-blk-ctrl", "syscon";
1267 reg = <0x4ac10000 0x10000>;
1268 power-domains = <&mediamix>;
1269 clocks = <&clk IMX93_CLK_MEDIA_APB>,
1270 <&clk IMX93_CLK_MEDIA_AXI>,
1271 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
1272 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
1273 <&clk IMX93_CLK_CAM_PIX>,
1274 <&clk IMX93_CLK_PXP_GATE>,
1275 <&clk IMX93_CLK_LCDIF_GATE>,
1276 <&clk IMX93_CLK_ISI_GATE>,
1277 <&clk IMX93_CLK_MIPI_CSI_GATE>,
1278 <&clk IMX93_CLK_MIPI_DSI_GATE>;
1279 clock-names = "apb", "axi", "nic", "disp", "cam",
1280 "pxp", "lcdif", "isi", "csi", "dsi";
1281 #power-domain-cells = <1>;
1282 status = "disabled";
1283 };
1284
1285 usbotg1: usb@4c100000 {
1286 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1287 reg = <0x4c100000 0x200>;
1288 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
1290 <&clk IMX93_CLK_HSIO_32K_GATE>;
1291 clock-names = "usb_ctrl_root", "usb_wakeup";
1292 assigned-clocks = <&clk IMX93_CLK_HSIO>;
1293 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
1294 assigned-clock-rates = <133000000>;
1295 phys = <&usbphynop1>;
1296 fsl,usbmisc = <&usbmisc1 0>;
1297 status = "disabled";
1298 };
1299
1300 usbmisc1: usbmisc@4c100200 {
1301 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1302 "fsl,imx6q-usbmisc";
1303 reg = <0x4c100200 0x200>;
1304 #index-cells = <1>;
1305 };
1306
1307 usbotg2: usb@4c200000 {
1308 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1309 reg = <0x4c200000 0x200>;
1310 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
1312 <&clk IMX93_CLK_HSIO_32K_GATE>;
1313 clock-names = "usb_ctrl_root", "usb_wakeup";
1314 assigned-clocks = <&clk IMX93_CLK_HSIO>;
1315 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
1316 assigned-clock-rates = <133000000>;
1317 phys = <&usbphynop2>;
1318 fsl,usbmisc = <&usbmisc2 0>;
1319 status = "disabled";
1320 };
1321
1322 usbmisc2: usbmisc@4c200200 {
1323 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1324 "fsl,imx6q-usbmisc";
1325 reg = <0x4c200200 0x200>;
1326 #index-cells = <1>;
1327 };
1328
1329 ddr-pmu@4e300dc0 {
1330 compatible = "fsl,imx93-ddr-pmu";
1331 reg = <0x4e300dc0 0x200>;
1332 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1333 };
1334 };
1335 };
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