1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright 2021-2023 NXP
4 *
5 * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
6 * Ciprian Costea <ciprianmarian.costea@nxp.com>
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
8 */
9
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
12 / {
13 compatible = "nxp,s32g3";
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu-map {
23 cluster0 {
24 core0 {
25 cpu = <&cpu0>;
26 };
27
28 core1 {
29 cpu = <&cpu1>;
30 };
31
32 core2 {
33 cpu = <&cpu2>;
34 };
35
36 core3 {
37 cpu = <&cpu3>;
38 };
39 };
40
41 cluster1 {
42 core0 {
43 cpu = <&cpu4>;
44 };
45
46 core1 {
47 cpu = <&cpu5>;
48 };
49
50 core2 {
51 cpu = <&cpu6>;
52 };
53
54 core3 {
55 cpu = <&cpu7>;
56 };
57 };
58 };
59
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a53";
63 reg = <0x0>;
64 enable-method = "psci";
65 clocks = <&dfs 0>;
66 };
67
68 cpu1: cpu@1 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a53";
71 reg = <0x1>;
72 enable-method = "psci";
73 clocks = <&dfs 0>;
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53";
79 reg = <0x2>;
80 enable-method = "psci";
81 clocks = <&dfs 0>;
82 };
83
84 cpu3: cpu@3 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a53";
87 reg = <0x3>;
88 enable-method = "psci";
89 clocks = <&dfs 0>;
90 };
91
92 cpu4: cpu@100 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a53";
95 reg = <0x100>;
96 enable-method = "psci";
97 clocks = <&dfs 0>;
98 };
99
100 cpu5: cpu@101 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x101>;
104 enable-method = "psci";
105 clocks = <&dfs 0>;
106 };
107
108 cpu6: cpu@102 {
109 device_type = "cpu";
110 compatible = "arm,cortex-a53";
111 reg = <0x102>;
112 enable-method = "psci";
113 clocks = <&dfs 0>;
114 };
115
116 cpu7: cpu@103 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a53";
119 reg = <0x103>;
120 enable-method = "psci";
121 clocks = <&dfs 0>;
122 };
123 };
124
125 firmware {
126 scmi: scmi {
127 compatible = "arm,scmi-smc";
128 shmem = <&scmi_shmem>;
129 arm,smc-id = <0xc20000fe>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132
133 dfs: protocol@13 {
134 reg = <0x13>;
135 #clock-cells = <1>;
136 };
137
138 clks: protocol@14 {
139 reg = <0x14>;
140 #clock-cells = <1>;
141 };
142 };
143
144 psci: psci {
145 compatible = "arm,psci-1.0";
146 method = "smc";
147 };
148 };
149
150
151 pmu {
152 compatible = "arm,cortex-a53-pmu";
153 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
154 };
155
156 reserved-memory {
157 #address-cells = <2>;
158 #size-cells = <2>;
159 ranges;
160
161 scmi_shmem: shm@d0000000 {
162 compatible = "arm,scmi-shmem";
163 reg = <0x0 0xd0000000 0x0 0x80>;
164 no-map;
165 };
166 };
167
168 soc@0 {
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0 0 0x80000000>;
173
174 uart0: serial@401c8000 {
175 compatible = "nxp,s32g3-linflexuart",
176 "fsl,s32v234-linflexuart";
177 reg = <0x401c8000 0x3000>;
178 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
179 status = "disabled";
180 };
181
182 uart1: serial@401cc000 {
183 compatible = "nxp,s32g3-linflexuart",
184 "fsl,s32v234-linflexuart";
185 reg = <0x401cc000 0x3000>;
186 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
187 status = "disabled";
188 };
189
190 uart2: serial@402bc000 {
191 compatible = "nxp,s32g3-linflexuart",
192 "fsl,s32v234-linflexuart";
193 reg = <0x402bc000 0x3000>;
194 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
195 status = "disabled";
196 };
197
198 usdhc0: mmc@402f0000 {
199 compatible = "nxp,s32g3-usdhc",
200 "nxp,s32g2-usdhc";
201 reg = <0x402f0000 0x1000>;
202 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clks 32>,
204 <&clks 31>,
205 <&clks 33>;
206 clock-names = "ipg", "ahb", "per";
207 status = "disabled";
208 };
209
210 gic: interrupt-controller@50800000 {
211 compatible = "arm,gic-v3";
212 #interrupt-cells = <3>;
213 interrupt-controller;
214 reg = <0x50800000 0x10000>,
215 <0x50900000 0x200000>,
216 <0x50400000 0x2000>,
217 <0x50410000 0x2000>,
218 <0x50420000 0x2000>;
219 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
220 };
221 };
222
223 timer {
224 compatible = "arm,armv8-timer";
225 interrupt-parent = <&gic>;
226 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
227 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
228 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
229 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
230 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
231 arm,no-tick-in-suspend;
232 };
233 };
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