1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * DTS File for HiSilicon Hi3798cv200 SoC.
4 *
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 */
7
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
13
14 / {
15 compatible = "hisilicon,hi3798cv200";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <2>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "arm,cortex-a53";
31 device_type = "cpu";
32 reg = <0x0 0x0>;
33 enable-method = "psci";
34 d-cache-size = <0x8000>; /* 32 KiB */
35 d-cache-line-size = <64>;
36 d-cache-sets = <128>;
37 i-cache-size = <0x8000>; /* 32 KiB */
38 i-cache-line-size = <64>;
39 i-cache-sets = <256>;
40 next-level-cache = <&L2>;
41 };
42
43 cpu@1 {
44 compatible = "arm,cortex-a53";
45 device_type = "cpu";
46 reg = <0x0 0x1>;
47 enable-method = "psci";
48 d-cache-size = <0x8000>; /* 32 KiB */
49 d-cache-line-size = <64>;
50 d-cache-sets = <128>;
51 i-cache-size = <0x8000>; /* 32 KiB */
52 i-cache-line-size = <64>;
53 i-cache-sets = <256>;
54 next-level-cache = <&L2>;
55 };
56
57 cpu@2 {
58 compatible = "arm,cortex-a53";
59 device_type = "cpu";
60 reg = <0x0 0x2>;
61 enable-method = "psci";
62 d-cache-size = <0x8000>; /* 32 KiB */
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 i-cache-size = <0x8000>; /* 32 KiB */
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
68 next-level-cache = <&L2>;
69 };
70
71 cpu@3 {
72 compatible = "arm,cortex-a53";
73 device_type = "cpu";
74 reg = <0x0 0x3>;
75 enable-method = "psci";
76 d-cache-size = <0x8000>; /* 32 KiB */
77 d-cache-line-size = <64>;
78 d-cache-sets = <128>;
79 i-cache-size = <0x8000>; /* 32 KiB */
80 i-cache-line-size = <64>;
81 i-cache-sets = <256>;
82 next-level-cache = <&L2>;
83 };
84 };
85
86 L2: l2-cache {
87 compatible = "cache";
88 cache-unified;
89 cache-size = <0x80000>; /* 512 KiB */
90 cache-line-size = <64>;
91 cache-sets = <512>;
92 cache-level = <2>;
93 };
94
95 gic: interrupt-controller@f1001000 {
96 compatible = "arm,gic-400";
97 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
98 <0x0 0xf1002000 0x0 0x2000>, /* GICC */
99 <0x0 0xf1004000 0x0 0x2000>, /* GICH */
100 <0x0 0xf1006000 0x0 0x2000>; /* GICV */
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
102 IRQ_TYPE_LEVEL_HIGH)>;
103 #address-cells = <0>;
104 #interrupt-cells = <3>;
105 interrupt-controller;
106 };
107
108 timer {
109 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
111 IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
113 IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
115 IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
117 IRQ_TYPE_LEVEL_LOW)>;
118 };
119
120 soc: soc@f0000000 {
121 compatible = "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0x0 0x0 0xf0000000 0x10000000>;
125
126 crg: clock-reset-controller@8a22000 {
127 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
128 reg = <0x8a22000 0x1000>;
129 #clock-cells = <1>;
130 #reset-cells = <2>;
131
132 gmacphyrst: reset-controller {
133 compatible = "ti,syscon-reset";
134 #reset-cells = <1>;
135 ti,reset-bits = <
136 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
137 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
138 >;
139 };
140 };
141
142 sysctrl: system-controller@8000000 {
143 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
144 reg = <0x8000000 0x1000>;
145 #clock-cells = <1>;
146 #reset-cells = <2>;
147 };
148
149 perictrl: peripheral-controller@8a20000 {
150 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
151 "simple-mfd";
152 reg = <0x8a20000 0x1000>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges = <0x0 0x8a20000 0x1000>;
156
157 usb2_phy1: usb2_phy@120 {
158 compatible = "hisilicon,hi3798cv200-usb2-phy";
159 reg = <0x120 0x4>;
160 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
161 resets = <&crg 0xbc 4>;
162 #address-cells = <1>;
163 #size-cells = <0>;
164
165 usb2_phy1_port0: phy@0 {
166 reg = <0>;
167 #phy-cells = <0>;
168 resets = <&crg 0xbc 8>;
169 };
170
171 usb2_phy1_port1: phy@1 {
172 reg = <1>;
173 #phy-cells = <0>;
174 resets = <&crg 0xbc 9>;
175 };
176 };
177
178 usb2_phy2: usb2_phy@124 {
179 compatible = "hisilicon,hi3798cv200-usb2-phy";
180 reg = <0x124 0x4>;
181 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
182 resets = <&crg 0xbc 6>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185
186 usb2_phy2_port0: phy@0 {
187 reg = <0>;
188 #phy-cells = <0>;
189 resets = <&crg 0xbc 10>;
190 };
191 };
192
193 combphy0: phy@850 {
194 compatible = "hisilicon,hi3798cv200-combphy";
195 reg = <0x850 0x8>;
196 #phy-cells = <1>;
197 clocks = <&crg HISTB_COMBPHY0_CLK>;
198 resets = <&crg 0x188 4>;
199 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
200 assigned-clock-rates = <100000000>;
201 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
202 };
203
204 combphy1: phy@858 {
205 compatible = "hisilicon,hi3798cv200-combphy";
206 reg = <0x858 0x8>;
207 #phy-cells = <1>;
208 clocks = <&crg HISTB_COMBPHY1_CLK>;
209 resets = <&crg 0x188 12>;
210 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
211 assigned-clock-rates = <100000000>;
212 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
213 };
214 };
215
216 pmx0: pinconf@8a21000 {
217 compatible = "pinconf-single";
218 reg = <0x8a21000 0x180>;
219 pinctrl-single,register-width = <32>;
220 pinctrl-single,function-mask = <7>;
221 pinctrl-single,gpio-range = <
222 &range 0 8 2 /* GPIO 0 */
223 &range 8 1 0 /* GPIO 1 */
224 &range 9 4 2
225 &range 13 1 0
226 &range 14 1 1
227 &range 15 1 0
228 &range 16 5 0 /* GPIO 2 */
229 &range 21 3 1
230 &range 24 4 1 /* GPIO 3 */
231 &range 28 2 2
232 &range 86 1 1
233 &range 87 1 0
234 &range 30 4 2 /* GPIO 4 */
235 &range 34 3 0
236 &range 37 1 2
237 &range 38 3 2 /* GPIO 6 */
238 &range 41 5 0
239 &range 46 8 1 /* GPIO 7 */
240 &range 54 8 1 /* GPIO 8 */
241 &range 64 7 1 /* GPIO 9 */
242 &range 71 1 0
243 &range 72 6 1 /* GPIO 10 */
244 &range 78 1 0
245 &range 79 1 1
246 &range 80 6 1 /* GPIO 11 */
247 &range 70 2 1
248 &range 88 8 0 /* GPIO 12 */
249 >;
250
251 range: gpio-range {
252 #pinctrl-single,gpio-range-cells = <3>;
253 };
254 };
255
256 uart0: serial@8b00000 {
257 compatible = "arm,pl011", "arm,primecell";
258 reg = <0x8b00000 0x1000>;
259 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>;
261 clock-names = "uartclk", "apb_pclk";
262 status = "disabled";
263 };
264
265 uart2: serial@8b02000 {
266 compatible = "arm,pl011", "arm,primecell";
267 reg = <0x8b02000 0x1000>;
268 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
270 clock-names = "uartclk", "apb_pclk";
271 status = "disabled";
272 };
273
274 i2c0: i2c@8b10000 {
275 compatible = "hisilicon,hix5hd2-i2c";
276 reg = <0x8b10000 0x1000>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
280 clock-frequency = <400000>;
281 clocks = <&crg HISTB_I2C0_CLK>;
282 status = "disabled";
283 };
284
285 i2c1: i2c@8b11000 {
286 compatible = "hisilicon,hix5hd2-i2c";
287 reg = <0x8b11000 0x1000>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
291 clock-frequency = <400000>;
292 clocks = <&crg HISTB_I2C1_CLK>;
293 status = "disabled";
294 };
295
296 i2c2: i2c@8b12000 {
297 compatible = "hisilicon,hix5hd2-i2c";
298 reg = <0x8b12000 0x1000>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
302 clock-frequency = <400000>;
303 clocks = <&crg HISTB_I2C2_CLK>;
304 status = "disabled";
305 };
306
307 i2c3: i2c@8b13000 {
308 compatible = "hisilicon,hix5hd2-i2c";
309 reg = <0x8b13000 0x1000>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
313 clock-frequency = <400000>;
314 clocks = <&crg HISTB_I2C3_CLK>;
315 status = "disabled";
316 };
317
318 i2c4: i2c@8b14000 {
319 compatible = "hisilicon,hix5hd2-i2c";
320 reg = <0x8b14000 0x1000>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
324 clock-frequency = <400000>;
325 clocks = <&crg HISTB_I2C4_CLK>;
326 status = "disabled";
327 };
328
329 spi0: spi@8b1a000 {
330 compatible = "arm,pl022", "arm,primecell";
331 reg = <0x8b1a000 0x1000>;
332 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
333 num-cs = <1>;
334 cs-gpios = <&gpio7 1 0>;
335 clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
336 clock-names = "sspclk", "apb_pclk";
337 #address-cells = <1>;
338 #size-cells = <0>;
339 status = "disabled";
340 };
341
342 sd0: mmc@9820000 {
343 compatible = "snps,dw-mshc";
344 reg = <0x9820000 0x10000>;
345 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&crg HISTB_SDIO0_BIU_CLK>,
347 <&crg HISTB_SDIO0_CIU_CLK>;
348 clock-names = "biu", "ciu";
349 resets = <&crg 0x9c 4>;
350 reset-names = "reset";
351 status = "disabled";
352 };
353
354 emmc: mmc@9830000 {
355 compatible = "hisilicon,hi3798cv200-dw-mshc";
356 reg = <0x9830000 0x10000>;
357 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&crg HISTB_MMC_CIU_CLK>,
359 <&crg HISTB_MMC_BIU_CLK>,
360 <&crg HISTB_MMC_SAMPLE_CLK>,
361 <&crg HISTB_MMC_DRV_CLK>;
362 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
363 resets = <&crg 0xa0 4>;
364 reset-names = "reset";
365 status = "disabled";
366 };
367
368 gpio0: gpio@8b20000 {
369 compatible = "arm,pl061", "arm,primecell";
370 reg = <0x8b20000 0x1000>;
371 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 gpio-ranges = <&pmx0 0 0 8>;
377 clocks = <&crg HISTB_APB_CLK>;
378 clock-names = "apb_pclk";
379 status = "disabled";
380 };
381
382 gpio1: gpio@8b21000 {
383 compatible = "arm,pl061", "arm,primecell";
384 reg = <0x8b21000 0x1000>;
385 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 gpio-ranges = <
391 &pmx0 0 8 1
392 &pmx0 1 9 4
393 &pmx0 5 13 1
394 &pmx0 6 14 1
395 &pmx0 7 15 1
396 >;
397 clocks = <&crg HISTB_APB_CLK>;
398 clock-names = "apb_pclk";
399 status = "disabled";
400 };
401
402 gpio2: gpio@8b22000 {
403 compatible = "arm,pl061", "arm,primecell";
404 reg = <0x8b22000 0x1000>;
405 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
411 clocks = <&crg HISTB_APB_CLK>;
412 clock-names = "apb_pclk";
413 status = "disabled";
414 };
415
416 gpio3: gpio@8b23000 {
417 compatible = "arm,pl061", "arm,primecell";
418 reg = <0x8b23000 0x1000>;
419 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <
425 &pmx0 0 24 4
426 &pmx0 4 28 2
427 &pmx0 6 86 1
428 &pmx0 7 87 1
429 >;
430 clocks = <&crg HISTB_APB_CLK>;
431 clock-names = "apb_pclk";
432 status = "disabled";
433 };
434
435 gpio4: gpio@8b24000 {
436 compatible = "arm,pl061", "arm,primecell";
437 reg = <0x8b24000 0x1000>;
438 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
439 gpio-controller;
440 #gpio-cells = <2>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
444 clocks = <&crg HISTB_APB_CLK>;
445 clock-names = "apb_pclk";
446 status = "disabled";
447 };
448
449 gpio5: gpio@8004000 {
450 compatible = "arm,pl061", "arm,primecell";
451 reg = <0x8004000 0x1000>;
452 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 clocks = <&crg HISTB_APB_CLK>;
458 clock-names = "apb_pclk";
459 status = "disabled";
460 };
461
462 gpio6: gpio@8b26000 {
463 compatible = "arm,pl061", "arm,primecell";
464 reg = <0x8b26000 0x1000>;
465 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
471 clocks = <&crg HISTB_APB_CLK>;
472 clock-names = "apb_pclk";
473 status = "disabled";
474 };
475
476 gpio7: gpio@8b27000 {
477 compatible = "arm,pl061", "arm,primecell";
478 reg = <0x8b27000 0x1000>;
479 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 gpio-ranges = <&pmx0 0 46 8>;
485 clocks = <&crg HISTB_APB_CLK>;
486 clock-names = "apb_pclk";
487 status = "disabled";
488 };
489
490 gpio8: gpio@8b28000 {
491 compatible = "arm,pl061", "arm,primecell";
492 reg = <0x8b28000 0x1000>;
493 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
494 gpio-controller;
495 #gpio-cells = <2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 gpio-ranges = <&pmx0 0 54 8>;
499 clocks = <&crg HISTB_APB_CLK>;
500 clock-names = "apb_pclk";
501 status = "disabled";
502 };
503
504 gpio9: gpio@8b29000 {
505 compatible = "arm,pl061", "arm,primecell";
506 reg = <0x8b29000 0x1000>;
507 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
508 gpio-controller;
509 #gpio-cells = <2>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
512 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
513 clocks = <&crg HISTB_APB_CLK>;
514 clock-names = "apb_pclk";
515 status = "disabled";
516 };
517
518 gpio10: gpio@8b2a000 {
519 compatible = "arm,pl061", "arm,primecell";
520 reg = <0x8b2a000 0x1000>;
521 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
527 clocks = <&crg HISTB_APB_CLK>;
528 clock-names = "apb_pclk";
529 status = "disabled";
530 };
531
532 gpio11: gpio@8b2b000 {
533 compatible = "arm,pl061", "arm,primecell";
534 reg = <0x8b2b000 0x1000>;
535 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
541 clocks = <&crg HISTB_APB_CLK>;
542 clock-names = "apb_pclk";
543 status = "disabled";
544 };
545
546 gpio12: gpio@8b2c000 {
547 compatible = "arm,pl061", "arm,primecell";
548 reg = <0x8b2c000 0x1000>;
549 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&pmx0 0 88 8>;
555 clocks = <&crg HISTB_APB_CLK>;
556 clock-names = "apb_pclk";
557 status = "disabled";
558 };
559
560 gmac0: ethernet@9840000 {
561 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
562 reg = <0x9840000 0x1000>,
563 <0x984300c 0x4>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&crg HISTB_ETH0_MAC_CLK>,
566 <&crg HISTB_ETH0_MACIF_CLK>;
567 clock-names = "mac_core", "mac_ifc";
568 resets = <&crg 0xcc 8>,
569 <&crg 0xcc 10>,
570 <&gmacphyrst 0>;
571 reset-names = "mac_core", "mac_ifc", "phy";
572 status = "disabled";
573 };
574
575 gmac1: ethernet@9841000 {
576 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
577 reg = <0x9841000 0x1000>,
578 <0x9843010 0x4>;
579 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&crg HISTB_ETH1_MAC_CLK>,
581 <&crg HISTB_ETH1_MACIF_CLK>;
582 clock-names = "mac_core", "mac_ifc";
583 resets = <&crg 0xcc 9>,
584 <&crg 0xcc 11>,
585 <&gmacphyrst 1>;
586 reset-names = "mac_core", "mac_ifc", "phy";
587 status = "disabled";
588 };
589
590 ir: ir@8001000 {
591 compatible = "hisilicon,hix5hd2-ir";
592 reg = <0x8001000 0x1000>;
593 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&sysctrl HISTB_IR_CLK>;
595 status = "disabled";
596 };
597
598 pcie: pcie@9860000 {
599 compatible = "hisilicon,hi3798cv200-pcie";
600 reg = <0x9860000 0x1000>,
601 <0x0 0x2000>,
602 <0x2000000 0x01000000>;
603 reg-names = "control", "rc-dbi", "config";
604 #address-cells = <3>;
605 #size-cells = <2>;
606 device_type = "pci";
607 bus-range = <0x00 0xff>;
608 num-lanes = <1>;
609 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>,
610 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
611 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
612 interrupt-names = "msi";
613 #interrupt-cells = <1>;
614 interrupt-map-mask = <0 0 0 0>;
615 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&crg HISTB_PCIE_AUX_CLK>,
617 <&crg HISTB_PCIE_PIPE_CLK>,
618 <&crg HISTB_PCIE_SYS_CLK>,
619 <&crg HISTB_PCIE_BUS_CLK>;
620 clock-names = "aux", "pipe", "sys", "bus";
621 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
622 reset-names = "soft", "sys", "bus";
623 phys = <&combphy1 PHY_TYPE_PCIE>;
624 phy-names = "phy";
625 status = "disabled";
626 };
627
628 ohci: usb@9880000 {
629 compatible = "generic-ohci";
630 reg = <0x9880000 0x10000>;
631 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&crg HISTB_USB2_BUS_CLK>,
633 <&crg HISTB_USB2_12M_CLK>,
634 <&crg HISTB_USB2_48M_CLK>;
635 clock-names = "bus", "clk12", "clk48";
636 resets = <&crg 0xb8 12>;
637 reset-names = "bus";
638 phys = <&usb2_phy1_port0>;
639 phy-names = "usb";
640 status = "disabled";
641 };
642
643 ehci: usb@9890000 {
644 compatible = "generic-ehci";
645 reg = <0x9890000 0x10000>;
646 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&crg HISTB_USB2_BUS_CLK>,
648 <&crg HISTB_USB2_PHY_CLK>,
649 <&crg HISTB_USB2_UTMI_CLK>;
650 clock-names = "bus", "phy", "utmi";
651 resets = <&crg 0xb8 12>,
652 <&crg 0xb8 16>,
653 <&crg 0xb8 13>;
654 reset-names = "bus", "phy", "utmi";
655 phys = <&usb2_phy1_port0>;
656 phy-names = "usb";
657 status = "disabled";
658 };
659 };
660 };
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