1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dts file for Hisilicon Hi6220 SoC
4 *
5 * Copyright (C) 2015, HiSilicon Ltd.
6 */
7
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <2>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu = <&cpu0>;
33 };
34 core1 {
35 cpu = <&cpu1>;
36 };
37 core2 {
38 cpu = <&cpu2>;
39 };
40 core3 {
41 cpu = <&cpu3>;
42 };
43 };
44 cluster1 {
45 core0 {
46 cpu = <&cpu4>;
47 };
48 core1 {
49 cpu = <&cpu5>;
50 };
51 core2 {
52 cpu = <&cpu6>;
53 };
54 core3 {
55 cpu = <&cpu7>;
56 };
57 };
58 };
59
60 idle-states {
61 entry-method = "psci";
62
63 CPU_SLEEP: cpu-sleep {
64 compatible = "arm,idle-state";
65 local-timer-stop;
66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency-us = <700>;
68 exit-latency-us = <250>;
69 min-residency-us = <1000>;
70 };
71
72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = "arm,idle-state";
74 local-timer-stop;
75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency-us = <1000>;
77 exit-latency-us = <700>;
78 min-residency-us = <2700>;
79 wakeup-latency-us = <1500>;
80 };
81 };
82
83 cpu0: cpu@0 {
84 compatible = "arm,cortex-a53";
85 device_type = "cpu";
86 reg = <0x0 0x0>;
87 enable-method = "psci";
88 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 0>;
90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coefficient = <311>;
94 };
95
96 cpu1: cpu@1 {
97 compatible = "arm,cortex-a53";
98 device_type = "cpu";
99 reg = <0x0 0x1>;
100 enable-method = "psci";
101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock 0>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <311>;
107 };
108
109 cpu2: cpu@2 {
110 compatible = "arm,cortex-a53";
111 device_type = "cpu";
112 reg = <0x0 0x2>;
113 enable-method = "psci";
114 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock 0>;
116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <311>;
120 };
121
122 cpu3: cpu@3 {
123 compatible = "arm,cortex-a53";
124 device_type = "cpu";
125 reg = <0x0 0x3>;
126 enable-method = "psci";
127 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock 0>;
129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coefficient = <311>;
133 };
134
135 cpu4: cpu@100 {
136 compatible = "arm,cortex-a53";
137 device_type = "cpu";
138 reg = <0x0 0x100>;
139 enable-method = "psci";
140 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock 0>;
142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coefficient = <311>;
146 };
147
148 cpu5: cpu@101 {
149 compatible = "arm,cortex-a53";
150 device_type = "cpu";
151 reg = <0x0 0x101>;
152 enable-method = "psci";
153 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock 0>;
155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coefficient = <311>;
159 };
160
161 cpu6: cpu@102 {
162 compatible = "arm,cortex-a53";
163 device_type = "cpu";
164 reg = <0x0 0x102>;
165 enable-method = "psci";
166 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock 0>;
168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coefficient = <311>;
172 };
173
174 cpu7: cpu@103 {
175 compatible = "arm,cortex-a53";
176 device_type = "cpu";
177 reg = <0x0 0x103>;
178 enable-method = "psci";
179 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock 0>;
181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coefficient = <311>;
185 };
186
187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache";
189 cache-level = <2>;
190 cache-unified;
191 };
192
193 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache";
195 cache-level = <2>;
196 cache-unified;
197 };
198 };
199
200 cpu_opp_table: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
203
204 opp00 {
205 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <1040000>;
207 clock-latency-ns = <500000>;
208 };
209 opp01 {
210 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <1040000>;
212 clock-latency-ns = <500000>;
213 };
214 opp02 {
215 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <1090000>;
217 clock-latency-ns = <500000>;
218 };
219 opp03 {
220 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <1180000>;
222 clock-latency-ns = <500000>;
223 };
224 opp04 {
225 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <1330000>;
227 clock-latency-ns = <500000>;
228 };
229 };
230
231 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>;
238 #interrupt-cells = <3>;
239 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 };
242
243 timer {
244 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 };
251
252 soc {
253 compatible = "simple-bus";
254 #address-cells = <2>;
255 #size-cells = <2>;
256 ranges;
257
258 sram: sram@fff80000 {
259 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 0x0 0x12000>;
261 };
262
263 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>;
267 #reset-cells = <1>;
268 };
269
270 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>;
274 #reset-cells = <1>;
275 };
276
277 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 };
283
284 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>;
288 };
289
290 acpu_sctrl: acpu_sctrl@f6504000 {
291 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
292 reg = <0x0 0xf6504000 0x0 0x1000>;
293 #clock-cells = <1>;
294 };
295
296 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon";
298 reg = <0x0 0xf4520000 0x0 0x4000>;
299 };
300
301 stub_clock: stub_clock {
302 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>;
305 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 11>;
307 };
308
309 uart0: serial@f8015000 { /* console */
310 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk", "apb_pclk";
316 };
317
318 uart1: serial@f7111000 {
319 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 9>;
328 dma-names = "rx", "tx";
329 status = "disabled";
330 };
331
332 uart2: serial@f7112000 {
333 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled";
342 };
343
344 uart3: serial@f7113000 {
345 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled";
354 };
355
356 uart4: serial@f7114000 {
357 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled";
366 };
367
368 dma0: dma@f7370000 {
369 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>;
372 dma-channels = <15>;
373 dma-requests = <32>;
374 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci;
377 dma-type = "hi6220_dma";
378 status = "okay";
379 };
380
381 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1", "timer2", "apb_pclk";
390 };
391
392 rtc0: rtc@f8003000 {
393 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pclk";
398 };
399
400 rtc1: rtc@f8004000 {
401 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pclk";
406 };
407
408 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3>;
415 pinctrl-single,register-width = <32>;
416 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-range = <
418 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >;
442 range: gpio-range {
443 #pinctrl-single,gpio-range-cells = <3>;
444 };
445 };
446
447 pmx1: pinmux@f7010800 {
448 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>;
451 #size-cells = <0>;
452 #pinctrl-cells = <1>;
453 pinctrl-single,register-width = <32>;
454 };
455
456 pmx2: pinmux@f8001800 {
457 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 #pinctrl-cells = <1>;
462 pinctrl-single,register-width = <32>;
463 };
464
465 gpio0: gpio@f8011000 {
466 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pclk";
475 };
476
477 gpio1: gpio@f8012000 {
478 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4>;
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pclk";
487 };
488
489 gpio2: gpio@f8013000 {
490 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4>;
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pclk";
499 };
500
501 gpio3: gpio@f8014000 {
502 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4>;
505 gpio-controller;
506 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pclk";
512 };
513
514 gpio4: gpio@f7020000 {
515 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4>;
518 gpio-controller;
519 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pclk";
525 };
526
527 gpio5: gpio@f7021000 {
528 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller;
535 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pclk";
538 };
539
540 gpio6: gpio@f7022000 {
541 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4>;
544 gpio-controller;
545 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pclk";
551 };
552
553 gpio7: gpio@f7023000 {
554 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4>;
557 gpio-controller;
558 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pclk";
564 };
565
566 gpio8: gpio@f7024000 {
567 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4>;
570 gpio-controller;
571 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pclk";
577 };
578
579 gpio9: gpio@f7025000 {
580 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pclk";
590 };
591
592 gpio10: gpio@f7026000 {
593 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4>;
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pclk";
603 };
604
605 gpio11: gpio@f7027000 {
606 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4>;
609 gpio-controller;
610 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pclk";
616 };
617
618 gpio12: gpio@f7028000 {
619 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pclk";
629 };
630
631 gpio13: gpio@f7029000 {
632 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4>;
635 gpio-controller;
636 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pclk";
642 };
643
644 gpio14: gpio@f702a000 {
645 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4>;
648 gpio-controller;
649 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pclk";
655 };
656
657 gpio15: gpio@f702b000 {
658 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4>;
661 gpio-controller;
662 #gpio-cells = <2>;
663 gpio-ranges = <
664 &pmx0 0 74 6
665 &pmx0 6 122 1
666 &pmx0 7 126 1
667 >;
668 interrupt-controller;
669 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pclk";
672 };
673
674 gpio16: gpio@f702c000 {
675 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4>;
678 gpio-controller;
679 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pclk";
685 };
686
687 gpio17: gpio@f702d000 {
688 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4>;
691 gpio-controller;
692 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller;
695 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pclk";
698 };
699
700 gpio18: gpio@f702e000 {
701 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4>;
704 gpio-controller;
705 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller;
708 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pclk";
711 };
712
713 gpio19: gpio@f702f000 {
714 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4>;
717 gpio-controller;
718 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller;
721 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pclk";
724 };
725
726 spi0: spi@f7106000 {
727 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>;
730 bus-id = <0>;
731 enable-dma = <0>;
732 clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk", "apb_pclk";
734 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0>;
738 status = "disabled";
739 };
740
741 i2c0: i2c@f7100000 {
742 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled";
750 };
751
752 i2c1: i2c@f7101000 {
753 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled";
761 };
762
763 i2c2: i2c@f7102000 {
764 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled";
772 };
773
774 usb_phy: usbphy {
775 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>;
777 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 };
780
781 usb: usb@f72c0000 {
782 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>;
785 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg";
788 dr_mode = "otg";
789 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 16 16 16 16 16 16 16>;
793 interrupts = <0 77 0x4>;
794 };
795
796 mailbox: mailbox@f7510000 {
797 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>;
802 };
803
804 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset";
812 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg_func &emmc_rst_cfg_func>;
815 };
816
817 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1>;
823 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset";
828 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 };
832
833 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset";
841 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 };
845
846 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp805", "arm,primecell";
848 reg = <0x0 0xf8005000 0x0 0x1000>;
849 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
851 <&ao_ctrl HI6220_WDT0_PCLK>;
852 clock-names = "wdog_clk", "apb_pclk";
853 };
854
855 tsensor: tsensor@f7030700 {
856 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal_clk";
861 #thermal-sensor-cells = <1>;
862 };
863
864 i2s0: i2s@f7118000 {
865 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx";
873 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1>;
875 };
876
877 thermal-zones {
878
879 cls0: cls0-thermal {
880 polling-delay = <1000>;
881 polling-delay-passive = <100>;
882 sustainable-power = <3326>;
883
884 /* sensor ID */
885 thermal-sensors = <&tsensor 2>;
886
887 trips {
888 threshold: trip-point0 {
889 temperature = <65000>;
890 hysteresis = <0>;
891 type = "passive";
892 };
893
894 target: trip-point1 {
895 temperature = <75000>;
896 hysteresis = <0>;
897 type = "passive";
898 };
899 };
900
901 cooling-maps {
902 map0 {
903 trip = <&target>;
904 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
906 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
907 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
908 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
909 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
910 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
911 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
912 };
913 };
914 };
915 };
916
917 ade: ade@f4100000 {
918 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base";
921 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4>; /* ldi interrupt */
924
925 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/
929 clock-names = "clk_ade_core",
930 "clk_codec_jpeg",
931 "clk_ade_pix";
932
933 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent;
937 status = "disabled";
938
939 port {
940 ade_out: endpoint {
941 remote-endpoint = <&dsi_in>;
942 };
943 };
944 };
945
946 dsi: dsi@f4107800 {
947 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk";
951 status = "disabled";
952
953 ports {
954 #address-cells = <1>;
955 #size-cells = <0>;
956
957 /* 0 for input port */
958 port@0 {
959 reg = <0>;
960 dsi_in: endpoint {
961 remote-endpoint = <&ade_out>;
962 };
963 };
964 };
965 };
966
967 debug@f6590000 {
968 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pclk";
972 cpu = <&cpu0>;
973 };
974
975 debug@f6592000 {
976 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pclk";
980 cpu = <&cpu1>;
981 };
982
983 debug@f6594000 {
984 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pclk";
988 cpu = <&cpu2>;
989 };
990
991 debug@f6596000 {
992 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pclk";
996 cpu = <&cpu3>;
997 };
998
999 debug@f65d0000 {
1000 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pclk";
1004 cpu = <&cpu4>;
1005 };
1006
1007 debug@f65d2000 {
1008 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pclk";
1012 cpu = <&cpu5>;
1013 };
1014
1015 debug@f65d4000 {
1016 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pclk";
1020 cpu = <&cpu6>;
1021 };
1022
1023 debug@f65d6000 {
1024 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pclk";
1028 cpu = <&cpu7>;
1029 };
1030
1031 mali: gpu@f4080000 {
1032 compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1033 reg = <0x0 0xf4080000 0x0 0x00040000>;
1034 interrupt-parent = <&gic>;
1035 interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
1046
1047 interrupt-names = "gp",
1048 "gpmmu",
1049 "pp",
1050 "pp0",
1051 "ppmmu0",
1052 "pp1",
1053 "ppmmu1",
1054 "pp2",
1055 "ppmmu2",
1056 "pp3",
1057 "ppmmu3";
1058 clocks = <&media_ctrl HI6220_G3D_CLK>,
1059 <&media_ctrl HI6220_G3D_PCLK>;
1060 clock-names = "bus", "core";
1061 assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1062 <&media_ctrl HI6220_G3D_PCLK>;
1063 assigned-clock-rates = <500000000>, <144000000>;
1064 reset-names = "ao_g3d", "media_g3d";
1065 resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
1066 };
1067 };
1068 };
1069
1070 #include "hi6220-coresight.dtsi"
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