1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree For AC5.
4 *
5 * Copyright (C) 2021 Marvell
6 * Copyright (C) 2022 Allied Telesis Labs
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
12 / {
13 model = "Marvell AC5 SoC";
14 compatible = "marvell,ac5";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <2>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;
27 };
28 core1 {
29 cpu = <&cpu1>;
30 };
31 };
32 };
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a55";
37 reg = <0x0 0x0>;
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a55";
45 reg = <0x0 0x100>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 };
49
50 l2: l2-cache {
51 compatible = "cache";
52 cache-level = <2>;
53 cache-unified;
54 };
55 };
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 timer {
63 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68 };
69
70 pmu {
71 compatible = "arm,cortex-a55-pmu";
72 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
73 };
74
75 soc {
76 compatible = "simple-bus";
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 internal-regs@7f000000 {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-bus";
85 /* 16M internal register @ 0x7f00_0000 */
86 ranges = <0x0 0x0 0x7f000000 0x1000000>;
87 dma-coherent;
88
89 uart0: serial@12000 {
90 compatible = "snps,dw-apb-uart";
91 reg = <0x12000 0x100>;
92 reg-shift = <2>;
93 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
94 reg-io-width = <1>;
95 clocks = <&cnm_clock>;
96 status = "okay";
97 };
98
99 uart1: serial@12100 {
100 compatible = "snps,dw-apb-uart";
101 reg = <0x12100 0x100>;
102 reg-shift = <2>;
103 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
104 reg-io-width = <1>;
105 clocks = <&cnm_clock>;
106 status = "disabled";
107 };
108
109 uart2: serial@12200 {
110 compatible = "snps,dw-apb-uart";
111 reg = <0x12200 0x100>;
112 reg-shift = <2>;
113 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
114 reg-io-width = <1>;
115 clocks = <&cnm_clock>;
116 status = "disabled";
117 };
118
119 uart3: serial@12300 {
120 compatible = "snps,dw-apb-uart";
121 reg = <0x12300 0x100>;
122 reg-shift = <2>;
123 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
124 reg-io-width = <1>;
125 clocks = <&cnm_clock>;
126 status = "disabled";
127 };
128
129 mdio: mdio@22004 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "marvell,orion-mdio";
133 reg = <0x22004 0x4>;
134 clocks = <&cnm_clock>;
135 };
136
137 i2c0: i2c@11000 {
138 compatible = "marvell,mv78230-i2c";
139 reg = <0x11000 0x20>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142
143 clocks = <&cnm_clock>;
144 clock-names = "core";
145 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
146 clock-frequency = <100000>;
147
148 pinctrl-names = "default", "gpio";
149 pinctrl-0 = <&i2c0_pins>;
150 pinctrl-1 = <&i2c0_gpio>;
151 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
152 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153 status = "disabled";
154 };
155
156 i2c1: i2c@11100 {
157 compatible = "marvell,mv78230-i2c";
158 reg = <0x11100 0x20>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161
162 clocks = <&cnm_clock>;
163 clock-names = "core";
164 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
165 clock-frequency = <100000>;
166
167 pinctrl-names = "default", "gpio";
168 pinctrl-0 = <&i2c1_pins>;
169 pinctrl-1 = <&i2c1_gpio>;
170 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
171 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
172 status = "disabled";
173 };
174
175 gpio0: gpio@18100 {
176 compatible = "marvell,orion-gpio";
177 reg = <0x18100 0x40>;
178 ngpios = <32>;
179 gpio-controller;
180 #gpio-cells = <2>;
181 gpio-ranges = <&pinctrl0 0 0 32>;
182 marvell,pwm-offset = <0x1f0>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
189 };
190
191 gpio1: gpio@18140 {
192 reg = <0x18140 0x40>;
193 compatible = "marvell,orion-gpio";
194 ngpios = <14>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 gpio-ranges = <&pinctrl0 0 32 14>;
198 marvell,pwm-offset = <0x1f0>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
201 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
203 };
204 };
205
206 mmc_dma: bus@80500000 {
207 compatible = "simple-bus";
208 ranges;
209 #address-cells = <0x2>;
210 #size-cells = <0x2>;
211 reg = <0x0 0x80500000 0x0 0x100000>;
212 dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
213 dma-coherent;
214
215 sdhci: mmc@805c0000 {
216 compatible = "marvell,ac5-sdhci",
217 "marvell,armada-ap806-sdhci";
218 reg = <0x0 0x805c0000 0x0 0x1000>;
219 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&emmc_clock>, <&cnm_clock>;
221 clock-names = "core", "axi";
222 bus-width = <8>;
223 non-removable;
224 mmc-ddr-1_8v;
225 mmc-hs200-1_8v;
226 mmc-hs400-1_8v;
227 };
228 };
229
230 /*
231 * Dedicated section for devices behind 32bit controllers so we
232 * can configure specific DMA mapping for them
233 */
234 behind-32bit-controller@7f000000 {
235 compatible = "simple-bus";
236 #address-cells = <0x2>;
237 #size-cells = <0x2>;
238 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
239 /* Host phy ram starts at 0x200M */
240 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
241 dma-coherent;
242
243 eth0: ethernet@20000 {
244 compatible = "marvell,armada-ac5-neta";
245 reg = <0x0 0x20000 0x0 0x4000>;
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cnm_clock>;
248 phy-mode = "sgmii";
249 status = "disabled";
250 };
251
252 eth1: ethernet@24000 {
253 compatible = "marvell,armada-ac5-neta";
254 reg = <0x0 0x24000 0x0 0x4000>;
255 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cnm_clock>;
257 phy-mode = "sgmii";
258 status = "disabled";
259 };
260
261 usb0: usb@80000 {
262 compatible = "marvell,orion-ehci";
263 reg = <0x0 0x80000 0x0 0x500>;
264 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
265 status = "disabled";
266 };
267
268 usb1: usb@a0000 {
269 compatible = "marvell,orion-ehci";
270 reg = <0x0 0xa0000 0x0 0x500>;
271 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
272 status = "disabled";
273 };
274 };
275
276 pinctrl0: pinctrl@80020100 {
277 compatible = "marvell,ac5-pinctrl";
278 reg = <0 0x80020100 0 0x20>;
279
280 i2c0_pins: i2c0-pins {
281 marvell,pins = "mpp26", "mpp27";
282 marvell,function = "i2c0";
283 };
284
285 i2c0_gpio: i2c0-gpio-pins {
286 marvell,pins = "mpp26", "mpp27";
287 marvell,function = "gpio";
288 };
289
290 i2c1_pins: i2c1-pins {
291 marvell,pins = "mpp20", "mpp21";
292 marvell,function = "i2c1";
293 };
294
295 i2c1_gpio: i2c1-gpio-pins {
296 marvell,pins = "mpp20", "mpp21";
297 marvell,function = "i2c1";
298 };
299 };
300
301 spi0: spi@805a0000 {
302 compatible = "marvell,armada-3700-spi";
303 reg = <0x0 0x805a0000 0x0 0x50>;
304 #address-cells = <0x1>;
305 #size-cells = <0x0>;
306 clocks = <&spi_clock>;
307 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
308 num-cs = <1>;
309 status = "disabled";
310 };
311
312 spi1: spi@805a8000 {
313 compatible = "marvell,armada-3700-spi";
314 reg = <0x0 0x805a8000 0x0 0x50>;
315 #address-cells = <0x1>;
316 #size-cells = <0x0>;
317 clocks = <&spi_clock>;
318 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
319 num-cs = <1>;
320 status = "disabled";
321 };
322
323 nand: nand-controller@805b0000 {
324 compatible = "marvell,ac5-nand-controller";
325 reg = <0x0 0x805b0000 0x0 0x00000054>;
326 #address-cells = <0x1>;
327 #size-cells = <0x0>;
328 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&nand_clock>;
330 status = "disabled";
331 };
332
333 gic: interrupt-controller@80600000 {
334 compatible = "arm,gic-v3";
335 #interrupt-cells = <3>;
336 interrupt-controller;
337 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
338 <0x0 0x80660000 0x0 0x40000>; /* GICR */
339 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
340 };
341 };
342
343 clocks {
344 cnm_clock: cnm-clock {
345 compatible = "fixed-clock";
346 #clock-cells = <0>;
347 clock-frequency = <328000000>;
348 };
349
350 spi_clock: spi-clock {
351 compatible = "fixed-clock";
352 #clock-cells = <0>;
353 clock-frequency = <200000000>;
354 };
355
356 nand_clock: nand-clock {
357 compatible = "fixed-clock";
358 #clock-cells = <0>;
359 clock-frequency = <400000000>;
360 };
361
362 emmc_clock: emmc-clock {
363 compatible = "fixed-clock";
364 #clock-cells = <0>;
365 clock-frequency = <400000000>;
366 };
367 };
368 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.