1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
4 *
5 * DTS for SolidRun CN9130 Clearfog Base.
6 *
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13
14 #include "cn9130.dtsi"
15 #include "cn9130-sr-som.dtsi"
16
17 /*
18 * Instantiate the external CP115
19 */
20
21 #define CP11X_NAME cp1
22 #define CP11X_BASE f4000000
23 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
24 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
25 #define CP11X_PCIE0_BASE f4600000
26 #define CP11X_PCIE1_BASE f4620000
27 #define CP11X_PCIE2_BASE f4640000
28
29 #include "armada-cp115.dtsi"
30
31 #undef CP11X_NAME
32 #undef CP11X_BASE
33 #undef CP11X_PCIEx_MEM_BASE
34 #undef CP11X_PCIEx_MEM_SIZE
35 #undef CP11X_PCIE0_BASE
36 #undef CP11X_PCIE1_BASE
37 #undef CP11X_PCIE2_BASE
38
39 / {
40 model = "SolidRun CN9131 SolidWAN";
41 compatible = "solidrun,cn9131-solidwan",
42 "solidrun,cn9130-sr-som", "marvell,cn9130";
43
44 aliases {
45 ethernet0 = &cp1_eth1;
46 ethernet1 = &cp1_eth2;
47 ethernet2 = &cp0_eth1;
48 ethernet3 = &cp0_eth2;
49 ethernet4 = &cp0_eth0;
50 ethernet5 = &cp1_eth0;
51 gpio0 = &ap_gpio;
52 gpio1 = &cp0_gpio1;
53 gpio2 = &cp0_gpio2;
54 gpio3 = &cp1_gpio1;
55 gpio4 = &cp1_gpio2;
56 gpio5 = &expander0;
57 i2c0 = &cp0_i2c0;
58 i2c1 = &cp0_i2c1;
59 i2c2 = &cp1_i2c1;
60 mmc0 = &ap_sdhci0;
61 mmc1 = &cp0_sdhci0;
62 rtc0 = &cp0_rtc;
63 rtc1 = &carrier_rtc;
64 };
65
66 leds {
67 compatible = "gpio-leds";
68 pinctrl-names = "default";
69 pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
70
71 /* for sfp-1 (J42) */
72 led-sfp1-activity {
73 label = "sfp1:green";
74 gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
75 };
76
77 /* for sfp-1 (J42) */
78 led-sfp1-link {
79 label = "sfp1:yellow";
80 gpios = <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>;
81 };
82
83 /* (J28) */
84 led-sfp0-activity {
85 label = "sfp0:green";
86 gpios = <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>;
87 };
88
89 /* (J28) */
90 led-sfp0-link {
91 label = "sfp0:yellow";
92 gpios = <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>;
93 };
94 };
95
96 /* Type-A port on J53 */
97 reg_usb_a_vbus0: regulator-usb-a-vbus0 {
98 compatible = "regulator-fixed";
99 pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
100 pinctrl-names = "default";
101 regulator-name = "vbus0";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 gpios = <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>;
105 enable-active-high;
106 regulator-always-on;
107 };
108
109 reg_usb_a_vbus1: regulator-usb-a-vbus1 {
110 compatible = "regulator-fixed";
111 pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
112 pinctrl-names = "default";
113 regulator-name = "vbus1";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
116 gpios = <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>;
117 enable-active-high;
118 regulator-always-on;
119 };
120
121 sfp0: sfp-0 {
122 compatible = "sff,sfp";
123 pinctrl-0 = <&cp0_sfp0_pins>;
124 pinctrl-names = "default";
125 i2c-bus = <&cp0_i2c1>;
126 los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
127 mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
128 tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
129 tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;
130 maximum-power-milliwatt = <2000>;
131 };
132
133 sfp1: sfp-1 {
134 compatible = "sff,sfp";
135 pinctrl-0 = <&cp1_sfp1_pins>;
136 pinctrl-names = "default";
137 i2c-bus = <&cp1_i2c1>;
138 los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>;
139 mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
140 tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>;
141 tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>;
142 maximum-power-milliwatt = <2000>;
143 };
144 };
145
146 &cp0_ethernet {
147 status = "okay";
148 };
149
150 /* SRDS #2 - SFP+ 10GE */
151 &cp0_eth0 {
152 managed = "in-band-status";
153 phy-mode = "10gbase-r";
154 phys = <&cp0_comphy2 0>;
155 sfp = <&sfp0>;
156 status = "okay";
157 };
158
159 /* SRDS #3 - SGMII 1GE */
160 &cp0_eth1 {
161 managed = "in-band-status";
162 phy-mode = "sgmii";
163 /* Without mdio phy access rely on sgmii auto-negotiation. */
164 phys = <&cp0_comphy3 1>;
165 status = "okay";
166 };
167
168 /* SRDS #1 - SGMII */
169 &cp0_eth2 {
170 /delete-property/ pinctrl-0;
171 /delete-property/ pinctrl-names;
172 managed = "in-band-status";
173 phy-mode = "sgmii";
174 phy = <&cp0_phy1>;
175 phys = <&cp0_comphy1 2>;
176 };
177
178 &cp0_gpio1 {
179 pcie0-0-w-disable-hog {
180 gpio-hog;
181 gpios = <6 GPIO_ACTIVE_LOW>;
182 output-low;
183 line-name = "pcie0.0-w-disable";
184 };
185
186 /* J34 */
187 m2-full-card-power-off-hog {
188 gpio-hog;
189 gpios = <8 GPIO_ACTIVE_LOW>;
190 output-low;
191 line-name = "m2-full-card-power-off";
192 };
193 };
194
195 &cp0_i2c0 {
196 /* assembly option */
197 fan-controller@18 {
198 compatible = "ti,amc6821";
199 reg = <0x18>;
200 };
201
202 expander0: gpio@41 {
203 compatible = "nxp,pca9536";
204 reg = <0x41>;
205
206 usb-a-vbus0-ilimit-hog {
207 gpio-hog;
208 gpios = <0 GPIO_ACTIVE_LOW>;
209 input;
210 line-name = "vbus0-ilimit";
211 };
212
213 /* duplicate connection, controlled by soc gpio */
214 usb-vbus0-enable-hog {
215 gpio-hog;
216 gpios = <1 GPIO_ACTIVE_HIGH>;
217 input;
218 line-name = "vbus0-enable";
219 };
220
221 usb-a-vbus1-ilimit-hog {
222 gpio-hog;
223 gpios = <2 GPIO_ACTIVE_LOW>;
224 input;
225 line-name = "vbus1-ilimit";
226 };
227
228 /* duplicate connection, controlled by soc gpio */
229 usb-vbus1-enable-hog {
230 gpio-hog;
231 gpios = <3 GPIO_ACTIVE_HIGH>;
232 input;
233 line-name = "vbus1-enable";
234 };
235 };
236
237 carrier_eeprom: eeprom@52 {
238 compatible = "atmel,24c02";
239 reg = <0x52>;
240 pagesize = <8>;
241 };
242
243 /* usb-hub@60 */
244
245 /* assembly option */
246 carrier_rtc: rtc@68 {
247 compatible = "st,m41t83";
248 reg = <0x68>;
249 pinctrl-0 = <&cp1_rtc_pins>;
250 pinctrl-names = "default";
251 interrupt-parent = <&cp1_gpio1>;
252 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
253 reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>;
254 };
255 };
256
257 &cp0_i2c1 {
258 /*
259 * Routed to SFP.
260 * Limit to 100kHz for compatibility with SFP modules,
261 * featuring AT24C01A/02/04 at addresses 0x50/0x51.
262 */
263 clock-frequency = <100000>;
264 pinctrl-0 = <&cp0_i2c1_pins>;
265 pinctrl-names = "default";
266 status = "okay";
267 };
268
269 &cp0_mdio {
270 /*
271 * SoM + Carrier each have a PHY at address 0.
272 * Remove the SoM phy node, and skip adding the carrier node.
273 * SGMII Auto-Negotation is enabled by bootloader for
274 * autonomous operation without mdio control.
275 */
276 /delete-node/ ethernet-phy@0;
277
278 /* U17016 */
279 cp0_phy1: ethernet-phy@1 {
280 reg = <1>;
281 /*
282 * Configure LEDs default behaviour:
283 * - LED[0]: link is 1000Mbps: On (yellow)
284 * - LED[1]: link/activity: On/blink (green)
285 * - LED[2]: high impedance (floating)
286 */
287 marvell,reg-init = <3 16 0xf000 0x0a17>;
288
289 leds {
290 #address-cells = <1>;
291 #size-cells = <0>;
292
293 led@0 {
294 reg = <0>;
295 color = <LED_COLOR_ID_YELLOW>;
296 function = LED_FUNCTION_LAN;
297 default-state = "keep";
298 };
299
300 led@1 {
301 reg = <1>;
302 color = <LED_COLOR_ID_GREEN>;
303 function = LED_FUNCTION_LAN;
304 default-state = "keep";
305 };
306 };
307 };
308 };
309
310 /* SRDS #0 - miniPCIe */
311 &cp0_pcie0 {
312 num-lanes = <1>;
313 phys = <&cp0_comphy0 0>;
314 status = "okay";
315 };
316
317 /* SRDS #5 - M.2 B-Key (J34) */
318 &cp0_pcie2 {
319 num-lanes = <1>;
320 phys = <&cp0_comphy5 2>;
321 status = "okay";
322 };
323
324 &cp0_pinctrl {
325 pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>;
326 pinctrl-names = "default";
327
328 cp0_i2c1_pins: cp0-i2c1-pins {
329 marvell,pins = "mpp35", "mpp36";
330 marvell,function = "i2c1";
331 };
332
333 cp0_led_pins: cp0-led-pins {
334 marvell,pins = "mpp4", "mpp7";
335 marvell,function = "gpio";
336 };
337
338 cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {
339 marvell,pins = "mpp8";
340 marvell,function = "gpio";
341 };
342
343 cp0_mmc0_pins: cp0-mmc0-pins {
344 marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
345 "mpp59", "mpp60", "mpp61";
346 marvell,function = "sdio";
347 };
348
349 cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {
350 marvell,pins = "mpp6";
351 marvell,function = "gpio";
352 };
353
354 cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {
355 marvell,pins = "mpp27";
356 marvell,function = "gpio";
357 };
358
359 cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {
360 marvell,pins = "mpp28";
361 marvell,function = "gpio";
362 };
363
364 cp0_sfp0_pins: cp0-sfp0-pins {
365 marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34";
366 marvell,function = "gpio";
367 };
368
369 cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
370 marvell,pins = "mpp12";
371 marvell,function = "spi1";
372 };
373 };
374
375 /* microSD */
376 &cp0_sdhci0 {
377 pinctrl-0 = <&cp0_mmc0_pins>;
378 pinctrl-names = "default";
379 bus-width = <4>;
380 no-1-8-v;
381 status = "okay";
382 };
383
384 &cp0_spi1 {
385 /* add pin for chip-select 1 */
386 pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
387
388 flash@1 {
389 compatible = "jedec,spi-nor";
390 reg = <1>;
391 /* read command supports max. 50MHz */
392 spi-max-frequency = <50000000>;
393 };
394 };
395
396 /* USB-2.0 Host to USB-Hub */
397 &cp0_usb3_0 {
398 phys = <&cp0_utmi0>;
399 phy-names = "utmi";
400 dr_mode = "host";
401 status = "okay";
402 };
403
404 /* SRDS #4 - USB-3.0 Host to USB-Hub */
405 &cp0_usb3_1 {
406 phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
407 phy-names = "comphy", "utmi";
408 dr_mode = "host";
409 status = "okay";
410 };
411
412 &cp0_utmi {
413 status = "okay";
414 };
415
416 &cp0_utmi1 {
417 status = "disabled";
418 };
419
420 &cp1_ethernet {
421 status = "okay";
422 };
423
424 /* SRDS #4 - SFP+ 10GE */
425 &cp1_eth0 {
426 managed = "in-band-status";
427 phy-mode = "10gbase-r";
428 phys = <&cp1_comphy4 0>;
429 sfp = <&sfp1>;
430 status = "okay";
431 };
432
433 /* SRDS #3 - SGMII 1GE */
434 &cp1_eth1 {
435 managed = "in-band-status";
436 phy-mode = "sgmii";
437 phy = <&cp1_phy0>;
438 phys = <&cp0_comphy3 1>;
439 status = "okay";
440 };
441
442 /* SRDS #5 - SGMII 1GE */
443 &cp1_eth2 {
444 managed = "in-band-status";
445 phy-mode = "sgmii";
446 phy = <&cp1_phy1>;
447 phys = <&cp0_comphy5 2>;
448 status = "okay";
449 };
450
451 &cp1_gpio1 {
452 status = "okay";
453
454 /* J30 */
455 m2-full-card-power-off-hog-0 {
456 gpio-hog;
457 gpios = <29 GPIO_ACTIVE_LOW>;
458 output-low;
459 line-name = "m2-full-card-power-off";
460 };
461
462 /* J44 */
463 m2-full-card-power-off-hog-1 {
464 gpio-hog;
465 gpios = <30 GPIO_ACTIVE_LOW>;
466 output-low;
467 line-name = "m2-full-card-power-off";
468 };
469 };
470
471 &cp1_gpio2 {
472 status = "okay";
473 };
474
475 &cp1_i2c1 {
476 /*
477 * Routed to SFP.
478 * Limit to 100kHz for compatibility with SFP modules,
479 * featuring AT24C01A/02/04 at addresses 0x50/0x51.
480 */
481 clock-frequency = <100000>;
482 pinctrl-0 = <&cp1_i2c1_pins>;
483 pinctrl-names = "default";
484 status = "okay";
485 };
486
487 &cp1_mdio {
488 pinctrl-0 = <&cp1_mdio_pins>;
489 pinctrl-names = "default";
490 status = "okay";
491
492 cp1_phy0: ethernet-phy@0 {
493 reg = <0>;
494 /*
495 * Configure LEDs default behaviour:
496 * - LED[0]: link is 1000Mbps: On (yellow)
497 * - LED[1]: link/activity: On/blink (green)
498 * - LED[2]: high impedance (floating)
499 */
500 marvell,reg-init = <3 16 0xf000 0x0a17>;
501
502 leds {
503 #address-cells = <1>;
504 #size-cells = <0>;
505
506 led@0 {
507 reg = <0>;
508 color = <LED_COLOR_ID_YELLOW>;
509 function = LED_FUNCTION_LAN;
510 default-state = "keep";
511 };
512
513 led@1 {
514 reg = <1>;
515 color = <LED_COLOR_ID_GREEN>;
516 function = LED_FUNCTION_LAN;
517 default-state = "keep";
518 };
519 };
520 };
521
522 cp1_phy1: ethernet-phy@1 {
523 reg = <1>;
524 /*
525 * Configure LEDs default behaviour:
526 * - LED[0]: link is 1000Mbps: On (yellow)
527 * - LED[1]: link/activity: On/blink (green)
528 * - LED[2]: high impedance (floating)
529 */
530 marvell,reg-init = <3 16 0xf000 0x0a17>;
531
532 leds {
533 #address-cells = <1>;
534 #size-cells = <0>;
535
536 led@0 {
537 reg = <0>;
538 color = <LED_COLOR_ID_YELLOW>;
539 function = LED_FUNCTION_LAN;
540 default-state = "keep";
541 };
542
543 led@1 {
544 reg = <1>;
545 color = <LED_COLOR_ID_GREEN>;
546 function = LED_FUNCTION_LAN;
547 default-state = "keep";
548 };
549 };
550 };
551 };
552
553 /* SRDS #0 - M.2 (J30) */
554 &cp1_pcie0 {
555 num-lanes = <1>;
556 phys = <&cp1_comphy0 0>;
557 status = "okay";
558 };
559
560 &cp1_rtc {
561 status = "disabled";
562 };
563
564 /* SRDS #1 - SATA on M.2 (J44) */
565 &cp1_sata0 {
566 phys = <&cp1_comphy1 0>;
567 status = "okay";
568
569 /* only port 0 is available */
570 /delete-node/ sata-port@1;
571 };
572
573 &cp1_syscon0 {
574 cp1_pinctrl: pinctrl {
575 compatible = "marvell,cp115-standalone-pinctrl";
576 pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>;
577 pinctrl-names = "default";
578
579 cp1_i2c1_pins: cp0-i2c1-pins {
580 marvell,pins = "mpp35", "mpp36";
581 marvell,function = "i2c1";
582 };
583
584 cp1_led_pins: cp1-led-pins {
585 marvell,pins = "mpp54", "mpp55";
586 marvell,function = "gpio";
587 };
588
589 cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {
590 marvell,pins = "mpp29";
591 marvell,function = "gpio";
592 };
593
594 cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {
595 marvell,pins = "mpp30";
596 marvell,function = "gpio";
597 };
598
599 cp1_mdio_pins: cp1-mdio-pins {
600 marvell,pins = "mpp37", "mpp38";
601 marvell,function = "ge";
602 };
603
604 cp1_rtc_pins: cp1-rtc-pins {
605 marvell,pins = "mpp12", "mpp13";
606 marvell,function = "gpio";
607 };
608
609 cp1_sfp1_pins: cp1-sfp1-pins {
610 marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50";
611 marvell,function = "gpio";
612 };
613 };
614 };
615
616 /*
617 * SRDS #2 - USB-3.0 Host to M.2 (J44)
618 * USB-2.0 Host to M.2 (J30)
619 */
620 &cp1_usb3_0 {
621 phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
622 phy-names = "comphy", "utmi";
623 dr_mode = "host";
624 status = "okay";
625 };
626
627 /* USB-2.0 Host to M.2 (J44) */
628 &cp1_usb3_1 {
629 phys = <&cp1_utmi1>;
630 phy-names = "utmi";
631 dr_mode = "host";
632 status = "okay";
633 };
634
635 &cp1_utmi {
636 status = "okay";
637 };
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