1 /*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
15
16 / {
17 model = "MediaTek MT7622 RFB1 board";
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
28 };
29
30 cpus {
31 cpu@0 {
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
34 };
35
36 cpu@1 {
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
39 };
40 };
41
42 gpio-keys {
43 compatible = "gpio-keys";
44
45 key-factory {
46 label = "factory";
47 linux,code = <BTN_0>;
48 gpios = <&pio 0 0>;
49 };
50
51 key-wps {
52 label = "wps";
53 linux,code = <KEY_WPS_BUTTON>;
54 gpios = <&pio 102 0>;
55 };
56 };
57
58 memory@40000000 {
59 reg = <0 0x40000000 0 0x20000000>;
60 device_type = "memory";
61 };
62
63 reg_1p8v: regulator-1p8v {
64 compatible = "regulator-fixed";
65 regulator-name = "fixed-1.8V";
66 regulator-min-microvolt = <1800000>;
67 regulator-max-microvolt = <1800000>;
68 regulator-always-on;
69 };
70
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 reg_5v: regulator-5v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-5V";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 regulator-boot-on;
86 regulator-always-on;
87 };
88 };
89
90 &bch {
91 status = "disabled";
92 };
93
94 &btif {
95 status = "okay";
96 };
97
98 &cir {
99 pinctrl-names = "default";
100 pinctrl-0 = <&irrx_pins>;
101 status = "okay";
102 };
103
104 ð {
105 pinctrl-names = "default";
106 pinctrl-0 = <ð_pins>;
107 status = "okay";
108
109 gmac0: mac@0 {
110 compatible = "mediatek,eth-mac";
111 reg = <0>;
112 phy-mode = "2500base-x";
113
114 fixed-link {
115 speed = <2500>;
116 full-duplex;
117 pause;
118 };
119 };
120
121 gmac1: mac@1 {
122 compatible = "mediatek,eth-mac";
123 reg = <1>;
124 phy-mode = "rgmii";
125
126 fixed-link {
127 speed = <1000>;
128 full-duplex;
129 pause;
130 };
131 };
132
133 mdio-bus {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 switch@0 {
138 compatible = "mediatek,mt7531";
139 reg = <0>;
140 reset-gpios = <&pio 54 0>;
141
142 ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 port@0 {
147 reg = <0>;
148 label = "lan0";
149 };
150
151 port@1 {
152 reg = <1>;
153 label = "lan1";
154 };
155
156 port@2 {
157 reg = <2>;
158 label = "lan2";
159 };
160
161 port@3 {
162 reg = <3>;
163 label = "lan3";
164 };
165
166 port@4 {
167 reg = <4>;
168 label = "wan";
169 };
170
171 port@5 {
172 reg = <5>;
173 ethernet = <&gmac1>;
174 phy-mode = "rgmii";
175
176 fixed-link {
177 speed = <1000>;
178 full-duplex;
179 pause;
180 };
181 };
182
183 port@6 {
184 reg = <6>;
185 label = "cpu";
186 ethernet = <&gmac0>;
187 phy-mode = "2500base-x";
188
189 fixed-link {
190 speed = <2500>;
191 full-duplex;
192 pause;
193 };
194 };
195 };
196 };
197
198 };
199 };
200
201 &i2c1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&i2c1_pins>;
204 status = "okay";
205 };
206
207 &i2c2 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c2_pins>;
210 status = "okay";
211 };
212
213 &mmc0 {
214 pinctrl-names = "default", "state_uhs";
215 pinctrl-0 = <&emmc_pins_default>;
216 pinctrl-1 = <&emmc_pins_uhs>;
217 status = "okay";
218 bus-width = <8>;
219 max-frequency = <50000000>;
220 cap-mmc-highspeed;
221 mmc-hs200-1_8v;
222 vmmc-supply = <®_3p3v>;
223 vqmmc-supply = <®_1p8v>;
224 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
225 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
226 non-removable;
227 };
228
229 &mmc1 {
230 pinctrl-names = "default", "state_uhs";
231 pinctrl-0 = <&sd0_pins_default>;
232 pinctrl-1 = <&sd0_pins_uhs>;
233 status = "okay";
234 bus-width = <4>;
235 max-frequency = <50000000>;
236 cap-sd-highspeed;
237 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
238 vmmc-supply = <®_3p3v>;
239 vqmmc-supply = <®_3p3v>;
240 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
242 };
243
244 &nandc {
245 pinctrl-names = "default";
246 pinctrl-0 = <¶llel_nand_pins>;
247 status = "disabled";
248 };
249
250 &nor_flash {
251 pinctrl-names = "default";
252 pinctrl-0 = <&spi_nor_pins>;
253 status = "disabled";
254
255 flash@0 {
256 compatible = "jedec,spi-nor";
257 reg = <0>;
258 };
259 };
260
261 &pcie0 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pcie0_pins>;
264 status = "okay";
265 };
266
267 &pio {
268 /* eMMC is shared pin with parallel NAND */
269 emmc_pins_default: emmc-pins-default {
270 mux {
271 function = "emmc";
272 groups = "emmc", "emmc_rst";
273 };
274
275 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
276 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
277 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
278 */
279 conf-cmd-dat {
280 pins = "NDL0", "NDL1", "NDL2",
281 "NDL3", "NDL4", "NDL5",
282 "NDL6", "NDL7", "NRB";
283 input-enable;
284 bias-pull-up;
285 };
286
287 conf-clk {
288 pins = "NCLE";
289 bias-pull-down;
290 };
291 };
292
293 emmc_pins_uhs: emmc-pins-uhs {
294 mux {
295 function = "emmc";
296 groups = "emmc";
297 };
298
299 conf-cmd-dat {
300 pins = "NDL0", "NDL1", "NDL2",
301 "NDL3", "NDL4", "NDL5",
302 "NDL6", "NDL7", "NRB";
303 input-enable;
304 drive-strength = <4>;
305 bias-pull-up;
306 };
307
308 conf-clk {
309 pins = "NCLE";
310 drive-strength = <4>;
311 bias-pull-down;
312 };
313 };
314
315 eth_pins: eth-pins {
316 mux {
317 function = "eth";
318 groups = "mdc_mdio", "rgmii_via_gmac2";
319 };
320 };
321
322 i2c1_pins: i2c1-pins {
323 mux {
324 function = "i2c";
325 groups = "i2c1_0";
326 };
327 };
328
329 i2c2_pins: i2c2-pins {
330 mux {
331 function = "i2c";
332 groups = "i2c2_0";
333 };
334 };
335
336 i2s1_pins: i2s1-pins {
337 mux {
338 function = "i2s";
339 groups = "i2s_out_mclk_bclk_ws",
340 "i2s1_in_data",
341 "i2s1_out_data";
342 };
343
344 conf {
345 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
346 "I2S_WS", "I2S_MCLK";
347 drive-strength = <12>;
348 bias-pull-down;
349 };
350 };
351
352 irrx_pins: irrx-pins {
353 mux {
354 function = "ir";
355 groups = "ir_1_rx";
356 };
357 };
358
359 irtx_pins: irtx-pins {
360 mux {
361 function = "ir";
362 groups = "ir_1_tx";
363 };
364 };
365
366 /* Parallel nand is shared pin with eMMC */
367 parallel_nand_pins: parallel-nand-pins {
368 mux {
369 function = "flash";
370 groups = "par_nand";
371 };
372 };
373
374 pcie0_pins: pcie0-pins {
375 mux {
376 function = "pcie";
377 groups = "pcie0_pad_perst",
378 "pcie0_1_waken",
379 "pcie0_1_clkreq";
380 };
381 };
382
383 pcie1_pins: pcie1-pins {
384 mux {
385 function = "pcie";
386 groups = "pcie1_pad_perst",
387 "pcie1_0_waken",
388 "pcie1_0_clkreq";
389 };
390 };
391
392 pmic_bus_pins: pmic-bus-pins {
393 mux {
394 function = "pmic";
395 groups = "pmic_bus";
396 };
397 };
398
399 pwm7_pins: pwm1-2-pins {
400 mux {
401 function = "pwm";
402 groups = "pwm_ch7_2";
403 };
404 };
405
406 wled_pins: wled-pins {
407 mux {
408 function = "led";
409 groups = "wled";
410 };
411 };
412
413 sd0_pins_default: sd0-pins-default {
414 mux {
415 function = "sd";
416 groups = "sd_0";
417 };
418
419 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
420 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
421 * DAT2, DAT3, CMD, CLK for SD respectively.
422 */
423 conf-cmd-data {
424 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
425 "I2S2_IN","I2S4_OUT";
426 input-enable;
427 drive-strength = <8>;
428 bias-pull-up;
429 };
430 conf-clk {
431 pins = "I2S3_OUT";
432 drive-strength = <12>;
433 bias-pull-down;
434 };
435 conf-cd {
436 pins = "TXD3";
437 bias-pull-up;
438 };
439 };
440
441 sd0_pins_uhs: sd0-pins-uhs {
442 mux {
443 function = "sd";
444 groups = "sd_0";
445 };
446
447 conf-cmd-data {
448 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
449 "I2S2_IN","I2S4_OUT";
450 input-enable;
451 bias-pull-up;
452 };
453
454 conf-clk {
455 pins = "I2S3_OUT";
456 bias-pull-down;
457 };
458 };
459
460 /* Serial NAND is shared pin with SPI-NOR */
461 serial_nand_pins: serial-nand-pins {
462 mux {
463 function = "flash";
464 groups = "snfi";
465 };
466 };
467
468 spic0_pins: spic0-pins {
469 mux {
470 function = "spi";
471 groups = "spic0_0";
472 };
473 };
474
475 spic1_pins: spic1-pins {
476 mux {
477 function = "spi";
478 groups = "spic1_0";
479 };
480 };
481
482 /* SPI-NOR is shared pin with serial NAND */
483 spi_nor_pins: spi-nor-pins {
484 mux {
485 function = "flash";
486 groups = "spi_nor";
487 };
488 };
489
490 /* serial NAND is shared pin with SPI-NOR */
491 serial_nand_pins: serial-nand-pins {
492 mux {
493 function = "flash";
494 groups = "snfi";
495 };
496 };
497
498 uart0_pins: uart0-pins {
499 mux {
500 function = "uart";
501 groups = "uart0_0_tx_rx" ;
502 };
503 };
504
505 uart2_pins: uart2-pins {
506 mux {
507 function = "uart";
508 groups = "uart2_1_tx_rx" ;
509 };
510 };
511
512 watchdog_pins: watchdog-pins {
513 mux {
514 function = "watchdog";
515 groups = "watchdog";
516 };
517 };
518
519 wmac_pins: wmac-pins {
520 mux {
521 function = "antsel";
522 groups = "antsel0", "antsel1", "antsel2", "antsel3",
523 "antsel4", "antsel5", "antsel6", "antsel7",
524 "antsel8", "antsel9", "antsel12", "antsel13",
525 "antsel14", "antsel15", "antsel16", "antsel17";
526 };
527 };
528 };
529
530 &pwm {
531 pinctrl-names = "default";
532 pinctrl-0 = <&pwm7_pins>;
533 status = "okay";
534 };
535
536 &pwrap {
537 pinctrl-names = "default";
538 pinctrl-0 = <&pmic_bus_pins>;
539
540 status = "okay";
541 };
542
543 &sata {
544 status = "okay";
545 };
546
547 &sata_phy {
548 status = "okay";
549 };
550
551 &spi0 {
552 pinctrl-names = "default";
553 pinctrl-0 = <&spic0_pins>;
554 status = "okay";
555 };
556
557 &spi1 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&spic1_pins>;
560 status = "okay";
561 };
562
563 &ssusb {
564 vusb33-supply = <®_3p3v>;
565 vbus-supply = <®_5v>;
566 status = "okay";
567 };
568
569 &u3phy {
570 status = "okay";
571 };
572
573 &uart0 {
574 pinctrl-names = "default";
575 pinctrl-0 = <&uart0_pins>;
576 status = "okay";
577 };
578
579 &uart2 {
580 pinctrl-names = "default";
581 pinctrl-0 = <&uart2_pins>;
582 status = "okay";
583 };
584
585 &watchdog {
586 pinctrl-names = "default";
587 pinctrl-0 = <&watchdog_pins>;
588 status = "okay";
589 };
590
591 &wmac {
592 pinctrl-names = "default";
593 pinctrl-0 = <&wmac_pins>;
594 status = "okay";
595 };
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