1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
6
7 / {
8 compatible = "mediatek,mt7981b";
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "arm,cortex-a53";
19 reg = <0x0>;
20 device_type = "cpu";
21 enable-method = "psci";
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a53";
26 reg = <0x1>;
27 device_type = "cpu";
28 enable-method = "psci";
29 };
30 };
31
32 oscillator-40m {
33 compatible = "fixed-clock";
34 clock-frequency = <40000000>;
35 clock-output-names = "clkxtal";
36 #clock-cells = <0>;
37 };
38
39 psci {
40 compatible = "arm,psci-1.0";
41 method = "smc";
42 };
43
44 soc {
45 compatible = "simple-bus";
46 ranges;
47 #address-cells = <2>;
48 #size-cells = <2>;
49
50 gic: interrupt-controller@c000000 {
51 compatible = "arm,gic-v3";
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
54 interrupt-parent = <&gic>;
55 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-controller;
57 #interrupt-cells = <3>;
58 };
59
60 infracfg: clock-controller@10001000 {
61 compatible = "mediatek,mt7981-infracfg", "syscon";
62 reg = <0 0x10001000 0 0x1000>;
63 #clock-cells = <1>;
64 };
65
66 topckgen: clock-controller@1001b000 {
67 compatible = "mediatek,mt7981-topckgen", "syscon";
68 reg = <0 0x1001b000 0 0x1000>;
69 #clock-cells = <1>;
70 };
71
72 watchdog: watchdog@1001c000 {
73 compatible = "mediatek,mt7986-wdt";
74 reg = <0 0x1001c000 0 0x1000>;
75 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
76 #reset-cells = <1>;
77 };
78
79 clock-controller@1001e000 {
80 compatible = "mediatek,mt7981-apmixedsys";
81 reg = <0 0x1001e000 0 0x1000>;
82 #clock-cells = <1>;
83 };
84
85 pwm@10048000 {
86 compatible = "mediatek,mt7981-pwm";
87 reg = <0 0x10048000 0 0x1000>;
88 clocks = <&infracfg CLK_INFRA_PWM_STA>,
89 <&infracfg CLK_INFRA_PWM_HCK>,
90 <&infracfg CLK_INFRA_PWM1_CK>,
91 <&infracfg CLK_INFRA_PWM2_CK>,
92 <&infracfg CLK_INFRA_PWM3_CK>;
93 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
94 #pwm-cells = <2>;
95 };
96
97 i2c@11007000 {
98 compatible = "mediatek,mt7981-i2c";
99 reg = <0 0x11007000 0 0x1000>,
100 <0 0x10217080 0 0x80>;
101 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
103 <&infracfg CLK_INFRA_AP_DMA_CK>,
104 <&infracfg CLK_INFRA_I2C_MCK_CK>,
105 <&infracfg CLK_INFRA_I2C_PCK_CK>;
106 clock-names = "main", "dma", "arb", "pmic";
107 #address-cells = <1>;
108 #size-cells = <0>;
109 status = "disabled";
110 };
111
112 pio: pinctrl@11d00000 {
113 compatible = "mediatek,mt7981-pinctrl";
114 reg = <0 0x11d00000 0 0x1000>,
115 <0 0x11c00000 0 0x1000>,
116 <0 0x11c10000 0 0x1000>,
117 <0 0x11d20000 0 0x1000>,
118 <0 0x11e00000 0 0x1000>,
119 <0 0x11e20000 0 0x1000>,
120 <0 0x11f00000 0 0x1000>,
121 <0 0x11f10000 0 0x1000>,
122 <0 0x1000b000 0 0x1000>;
123 reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
124 "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
125 interrupt-controller;
126 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-parent = <&gic>;
128 gpio-ranges = <&pio 0 0 56>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 #interrupt-cells = <2>;
132 };
133
134 efuse@11f20000 {
135 compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
136 reg = <0 0x11f20000 0 0x1000>;
137 #address-cells = <1>;
138 #size-cells = <1>;
139 };
140
141 clock-controller@15000000 {
142 compatible = "mediatek,mt7981-ethsys", "syscon";
143 reg = <0 0x15000000 0 0x1000>;
144 #clock-cells = <1>;
145 #reset-cells = <1>;
146 };
147
148 wifi@18000000 {
149 compatible = "mediatek,mt7981-wmac";
150 reg = <0 0x18000000 0 0x1000000>,
151 <0 0x10003000 0 0x1000>,
152 <0 0x11d10000 0 0x1000>;
153 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
158 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
159 clock-names = "mcu", "ap2conn";
160 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
161 reset-names = "consys";
162 };
163 };
164
165 timer {
166 compatible = "arm,armv8-timer";
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
169 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
170 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
171 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
172 };
173 };
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