1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
6
7 / {
8 compatible = "mediatek,mt7981b";
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "arm,cortex-a53";
19 reg = <0x0>;
20 device_type = "cpu";
21 enable-method = "psci";
22 };
23
24 cpu@1 {
25 compatible = "arm,cortex-a53";
26 reg = <0x1>;
27 device_type = "cpu";
28 enable-method = "psci";
29 };
30 };
31
32 oscillator-40m {
33 compatible = "fixed-clock";
34 clock-frequency = <40000000>;
35 clock-output-names = "clkxtal";
36 #clock-cells = <0>;
37 };
38
39 psci {
40 compatible = "arm,psci-1.0";
41 method = "smc";
42 };
43
44 soc {
45 compatible = "simple-bus";
46 ranges;
47 #address-cells = <2>;
48 #size-cells = <2>;
49
50 gic: interrupt-controller@c000000 {
51 compatible = "arm,gic-v3";
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
54 interrupt-parent = <&gic>;
55 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-controller;
57 #interrupt-cells = <3>;
58 };
59
60 infracfg: clock-controller@10001000 {
61 compatible = "mediatek,mt7981-infracfg", "syscon";
62 reg = <0 0x10001000 0 0x1000>;
63 #clock-cells = <1>;
64 };
65
66 topckgen: clock-controller@1001b000 {
67 compatible = "mediatek,mt7981-topckgen", "syscon";
68 reg = <0 0x1001b000 0 0x1000>;
69 #clock-cells = <1>;
70 };
71
72 watchdog: watchdog@1001c000 {
73 compatible = "mediatek,mt7986-wdt";
74 reg = <0 0x1001c000 0 0x1000>;
75 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
76 #reset-cells = <1>;
77 };
78
79 clock-controller@1001e000 {
80 compatible = "mediatek,mt7981-apmixedsys";
81 reg = <0 0x1001e000 0 0x1000>;
82 #clock-cells = <1>;
83 };
84
85 pwm@10048000 {
86 compatible = "mediatek,mt7981-pwm";
87 reg = <0 0x10048000 0 0x1000>;
88 clocks = <&infracfg CLK_INFRA_PWM_STA>,
89 <&infracfg CLK_INFRA_PWM_HCK>,
90 <&infracfg CLK_INFRA_PWM1_CK>,
91 <&infracfg CLK_INFRA_PWM2_CK>,
92 <&infracfg CLK_INFRA_PWM3_CK>;
93 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
94 #pwm-cells = <2>;
95 };
96
97 serial@11002000 {
98 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
99 reg = <0 0x11002000 0 0x100>;
100 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-names = "uart", "wakeup";
102 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
103 <&infracfg CLK_INFRA_UART0_CK>;
104 clock-names = "baud", "bus";
105 status = "disabled";
106 };
107
108 serial@11003000 {
109 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
110 reg = <0 0x11003000 0 0x100>;
111 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "uart", "wakeup";
113 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
114 <&infracfg CLK_INFRA_UART1_CK>;
115 clock-names = "baud", "bus";
116 status = "disabled";
117 };
118
119 serial@11004000 {
120 compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
121 reg = <0 0x11004000 0 0x100>;
122 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-names = "uart", "wakeup";
124 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
125 <&infracfg CLK_INFRA_UART2_CK>;
126 clock-names = "baud", "bus";
127 status = "disabled";
128 };
129
130 i2c@11007000 {
131 compatible = "mediatek,mt7981-i2c";
132 reg = <0 0x11007000 0 0x1000>,
133 <0 0x10217080 0 0x80>;
134 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
136 <&infracfg CLK_INFRA_AP_DMA_CK>,
137 <&infracfg CLK_INFRA_I2C_MCK_CK>,
138 <&infracfg CLK_INFRA_I2C_PCK_CK>;
139 clock-names = "main", "dma", "arb", "pmic";
140 #address-cells = <1>;
141 #size-cells = <0>;
142 status = "disabled";
143 };
144
145 spi@11009000 {
146 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
147 reg = <0 0x11009000 0 0x1000>;
148 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&topckgen CLK_TOP_CB_M_D2>,
150 <&topckgen CLK_TOP_SPI_SEL>,
151 <&infracfg CLK_INFRA_SPI2_CK>,
152 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
153 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 status = "disabled";
157 };
158
159 spi@1100a000 {
160 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
161 reg = <0 0x1100a000 0 0x1000>;
162 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&topckgen CLK_TOP_CB_M_D2>,
164 <&topckgen CLK_TOP_SPI_SEL>,
165 <&infracfg CLK_INFRA_SPI0_CK>,
166 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
167 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 status = "disabled";
171 };
172
173 spi@1100b000 {
174 compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
175 reg = <0 0x1100b000 0 0x1000>;
176 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&topckgen CLK_TOP_CB_M_D2>,
178 <&topckgen CLK_TOP_SPI_SEL>,
179 <&infracfg CLK_INFRA_SPI1_CK>,
180 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
181 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 status = "disabled";
185 };
186
187 pio: pinctrl@11d00000 {
188 compatible = "mediatek,mt7981-pinctrl";
189 reg = <0 0x11d00000 0 0x1000>,
190 <0 0x11c00000 0 0x1000>,
191 <0 0x11c10000 0 0x1000>,
192 <0 0x11d20000 0 0x1000>,
193 <0 0x11e00000 0 0x1000>,
194 <0 0x11e20000 0 0x1000>,
195 <0 0x11f00000 0 0x1000>,
196 <0 0x11f10000 0 0x1000>,
197 <0 0x1000b000 0 0x1000>;
198 reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
199 "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
200 interrupt-controller;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-parent = <&gic>;
203 gpio-ranges = <&pio 0 0 56>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 #interrupt-cells = <2>;
207 };
208
209 efuse@11f20000 {
210 compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
211 reg = <0 0x11f20000 0 0x1000>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 };
215
216 clock-controller@15000000 {
217 compatible = "mediatek,mt7981-ethsys", "syscon";
218 reg = <0 0x15000000 0 0x1000>;
219 #clock-cells = <1>;
220 #reset-cells = <1>;
221 };
222
223 wifi@18000000 {
224 compatible = "mediatek,mt7981-wmac";
225 reg = <0 0x18000000 0 0x1000000>,
226 <0 0x10003000 0 0x1000>,
227 <0 0x11d10000 0 0x1000>;
228 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
233 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
234 clock-names = "mcu", "ap2conn";
235 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
236 reset-names = "consys";
237 };
238 };
239
240 timer {
241 compatible = "arm,armv8-timer";
242 interrupt-parent = <&gic>;
243 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
244 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
245 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
247 };
248 };
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