1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8 /dts-v1/;
9 #include "mt8183.dtsi"
10 #include "mt6358.dtsi"
11
12 / {
13 model = "MediaTek MT8183 evaluation board";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
16
17 aliases {
18 serial0 = &uart0;
19 };
20
21 memory@40000000 {
22 device_type = "memory";
23 reg = <0 0x40000000 0 0x80000000>;
24 };
25
26 chosen {
27 stdout-path = "serial0:921600n8";
28 };
29
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
33 ranges;
34 scp_mem_reserved: memory@50000000 {
35 compatible = "shared-dma-pool";
36 reg = <0 0x50000000 0 0x2900000>;
37 no-map;
38 };
39 };
40
41 thermal-sensor {
42 compatible = "murata,ncp03wf104";
43 pullup-uv = <1800000>;
44 pullup-ohm = <390000>;
45 pulldown-ohm = <0>;
46 io-channels = <&auxadc 0>;
47 };
48 };
49
50 &auxadc {
51 status = "okay";
52 };
53
54 &gpu {
55 mali-supply = <&mt6358_vgpu_reg>;
56 };
57
58 &i2c0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins_0>;
61 status = "okay";
62 clock-frequency = <100000>;
63 };
64
65 &i2c1 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2c_pins_1>;
68 status = "okay";
69 clock-frequency = <100000>;
70 };
71
72 &i2c2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&i2c_pins_2>;
75 status = "okay";
76 clock-frequency = <100000>;
77 };
78
79 &i2c3 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&i2c_pins_3>;
82 status = "okay";
83 clock-frequency = <100000>;
84 };
85
86 &i2c4 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c_pins_4>;
89 status = "okay";
90 clock-frequency = <1000000>;
91 };
92
93 &i2c5 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c_pins_5>;
96 status = "okay";
97 clock-frequency = <1000000>;
98 };
99
100 &mmc0 {
101 status = "okay";
102 pinctrl-names = "default", "state_uhs";
103 pinctrl-0 = <&mmc0_pins_default>;
104 pinctrl-1 = <&mmc0_pins_uhs>;
105 bus-width = <8>;
106 max-frequency = <200000000>;
107 cap-mmc-highspeed;
108 mmc-hs200-1_8v;
109 mmc-hs400-1_8v;
110 cap-mmc-hw-reset;
111 no-sdio;
112 no-sd;
113 hs400-ds-delay = <0x12814>;
114 vmmc-supply = <&mt6358_vemc_reg>;
115 vqmmc-supply = <&mt6358_vio18_reg>;
116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
117 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
118 non-removable;
119 };
120
121 &mmc1 {
122 status = "okay";
123 pinctrl-names = "default", "state_uhs";
124 pinctrl-0 = <&mmc1_pins_default>;
125 pinctrl-1 = <&mmc1_pins_uhs>;
126 bus-width = <4>;
127 max-frequency = <200000000>;
128 cap-sd-highspeed;
129 sd-uhs-sdr50;
130 sd-uhs-sdr104;
131 cap-sdio-irq;
132 no-mmc;
133 no-sd;
134 vmmc-supply = <&mt6358_vmch_reg>;
135 vqmmc-supply = <&mt6358_vmc_reg>;
136 keep-power-in-suspend;
137 wakeup-source;
138 non-removable;
139 };
140
141 &mt6358_vgpu_reg {
142 regulator-min-microvolt = <625000>;
143 regulator-max-microvolt = <900000>;
144
145 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
146 regulator-coupled-max-spread = <100000>;
147 };
148
149 &mt6358_vsram_gpu_reg {
150 regulator-min-microvolt = <850000>;
151 regulator-max-microvolt = <1000000>;
152
153 regulator-coupled-with = <&mt6358_vgpu_reg>;
154 regulator-coupled-max-spread = <100000>;
155 };
156
157 &pio {
158 i2c_pins_0: i2c0 {
159 pins_i2c {
160 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
161 <PINMUX_GPIO83__FUNC_SCL0>;
162 mediatek,pull-up-adv = <3>;
163 };
164 };
165
166 i2c_pins_1: i2c1 {
167 pins_i2c {
168 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
169 <PINMUX_GPIO84__FUNC_SCL1>;
170 mediatek,pull-up-adv = <3>;
171 };
172 };
173
174 i2c_pins_2: i2c2 {
175 pins_i2c {
176 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
177 <PINMUX_GPIO104__FUNC_SDA2>;
178 mediatek,pull-up-adv = <3>;
179 };
180 };
181
182 i2c_pins_3: i2c3 {
183 pins_i2c {
184 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
185 <PINMUX_GPIO51__FUNC_SDA3>;
186 mediatek,pull-up-adv = <3>;
187 };
188 };
189
190 i2c_pins_4: i2c4 {
191 pins_i2c {
192 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
193 <PINMUX_GPIO106__FUNC_SDA4>;
194 mediatek,pull-up-adv = <3>;
195 };
196 };
197
198 i2c_pins_5: i2c5 {
199 pins_i2c {
200 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
201 <PINMUX_GPIO49__FUNC_SDA5>;
202 mediatek,pull-up-adv = <3>;
203 };
204 };
205
206 spi_pins_0: spi0 {
207 pins_spi {
208 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
209 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
210 <PINMUX_GPIO87__FUNC_SPI0_MO>,
211 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
212 bias-disable;
213 };
214 };
215
216 mmc0_pins_default: mmc0default {
217 pins_cmd_dat {
218 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
219 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
220 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
221 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
222 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
223 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
224 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
225 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
226 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
227 input-enable;
228 bias-pull-up;
229 };
230
231 pins_clk {
232 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
233 bias-pull-down;
234 };
235
236 pins_rst {
237 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
238 bias-pull-up;
239 };
240 };
241
242 mmc0_pins_uhs: mmc0 {
243 pins_cmd_dat {
244 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
245 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
246 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
247 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
248 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
249 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
250 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
251 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
252 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
253 input-enable;
254 drive-strength = <MTK_DRIVE_10mA>;
255 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
256 };
257
258 pins_clk {
259 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
260 drive-strength = <MTK_DRIVE_10mA>;
261 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
262 };
263
264 pins_ds {
265 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
266 drive-strength = <MTK_DRIVE_10mA>;
267 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
268 };
269
270 pins_rst {
271 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
272 drive-strength = <MTK_DRIVE_10mA>;
273 bias-pull-up;
274 };
275 };
276
277 mmc1_pins_default: mmc1default {
278 pins_cmd_dat {
279 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
280 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
281 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
282 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
283 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
284 input-enable;
285 bias-pull-up;
286 };
287
288 pins_clk {
289 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
290 input-enable;
291 bias-pull-down;
292 };
293
294 pins_pmu {
295 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
296 <PINMUX_GPIO166__FUNC_GPIO166>;
297 output-high;
298 };
299 };
300
301 mmc1_pins_uhs: mmc1 {
302 pins_cmd_dat {
303 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
304 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
305 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
306 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
307 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
308 drive-strength = <MTK_DRIVE_6mA>;
309 input-enable;
310 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
311 };
312
313 pins_clk {
314 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
315 drive-strength = <MTK_DRIVE_6mA>;
316 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
317 input-enable;
318 };
319 };
320
321 spi_pins_1: spi1 {
322 pins_spi {
323 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
324 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
325 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
326 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
327 bias-disable;
328 };
329 };
330
331 spi_pins_2: spi2 {
332 pins_spi {
333 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
334 <PINMUX_GPIO1__FUNC_SPI2_MO>,
335 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
336 <PINMUX_GPIO94__FUNC_SPI2_MI>;
337 bias-disable;
338 };
339 };
340
341 spi_pins_3: spi3 {
342 pins_spi {
343 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
344 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
345 <PINMUX_GPIO23__FUNC_SPI3_MO>,
346 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
347 bias-disable;
348 };
349 };
350
351 spi_pins_4: spi4 {
352 pins_spi {
353 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
354 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
355 <PINMUX_GPIO19__FUNC_SPI4_MO>,
356 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
357 bias-disable;
358 };
359 };
360
361 spi_pins_5: spi5 {
362 pins_spi {
363 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
364 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
365 <PINMUX_GPIO15__FUNC_SPI5_MO>,
366 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
367 bias-disable;
368 };
369 };
370
371 pwm_pins_1: pwm1 {
372 pins_pwm {
373 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
374 };
375 };
376 };
377
378 &pmic {
379 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
380 };
381
382 &mfg {
383 domain-supply = <&mt6358_vgpu_reg>;
384 };
385
386 &spi0 {
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi_pins_0>;
389 mediatek,pad-select = <0>;
390 status = "okay";
391 };
392
393 &spi1 {
394 pinctrl-names = "default";
395 pinctrl-0 = <&spi_pins_1>;
396 mediatek,pad-select = <0>;
397 status = "okay";
398 };
399
400 &spi2 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi_pins_2>;
403 mediatek,pad-select = <0>;
404 status = "okay";
405 };
406
407 &spi3 {
408 pinctrl-names = "default";
409 pinctrl-0 = <&spi_pins_3>;
410 mediatek,pad-select = <0>;
411 status = "okay";
412 };
413
414 &spi4 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&spi_pins_4>;
417 mediatek,pad-select = <0>;
418 status = "okay";
419 };
420
421 &spi5 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&spi_pins_5>;
424 mediatek,pad-select = <0>;
425 status = "okay";
426
427 };
428
429 &cci {
430 proc-supply = <&mt6358_vproc12_reg>;
431 };
432
433 &cpu0 {
434 proc-supply = <&mt6358_vproc12_reg>;
435 };
436
437 &cpu1 {
438 proc-supply = <&mt6358_vproc12_reg>;
439 };
440
441 &cpu2 {
442 proc-supply = <&mt6358_vproc12_reg>;
443 };
444
445 &cpu3 {
446 proc-supply = <&mt6358_vproc12_reg>;
447 };
448
449 &cpu4 {
450 proc-supply = <&mt6358_vproc11_reg>;
451 };
452
453 &cpu5 {
454 proc-supply = <&mt6358_vproc11_reg>;
455 };
456
457 &cpu6 {
458 proc-supply = <&mt6358_vproc11_reg>;
459 };
460
461 &cpu7 {
462 proc-supply = <&mt6358_vproc11_reg>;
463 };
464
465 &uart0 {
466 status = "okay";
467 };
468
469 &pwm1 {
470 status = "okay";
471 pinctrl-0 = <&pwm_pins_1>;
472 pinctrl-names = "default";
473 };
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