1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "mt8183.dtsi"
11 #include "mt6358.dtsi"
12
13 / {
14 aliases {
15 serial0 = &uart0;
16 mmc0 = &mmc0;
17 mmc1 = &mmc1;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 backlight_lcd0: backlight_lcd0 {
25 compatible = "pwm-backlight";
26 pwms = <&pwm0 0 500000>;
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
32 status = "okay";
33 };
34
35 memory@40000000 {
36 device_type = "memory";
37 reg = <0 0x40000000 0 0x80000000>;
38 };
39
40 clk32k: oscillator1 {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 clock-output-names = "clk32k";
45 };
46
47 it6505_pp18_reg: regulator0 {
48 compatible = "regulator-fixed";
49 regulator-name = "it6505_pp18";
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
52 gpio = <&pio 178 0>;
53 enable-active-high;
54 };
55
56 lcd_pp3300: regulator1 {
57 compatible = "regulator-fixed";
58 regulator-name = "lcd_pp3300";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 regulator-always-on;
62 regulator-boot-on;
63 };
64
65 bl_pp5000: regulator2 {
66 compatible = "regulator-fixed";
67 regulator-name = "bl_pp5000";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 regulator-always-on;
71 regulator-boot-on;
72 };
73
74 mmc1_fixed_power: regulator3 {
75 compatible = "regulator-fixed";
76 regulator-name = "mmc1_power";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 };
80
81 mmc1_fixed_io: regulator4 {
82 compatible = "regulator-fixed";
83 regulator-name = "mmc1_io";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 };
87
88 pp1800_alw: regulator5 {
89 compatible = "regulator-fixed";
90 regulator-name = "pp1800_alw";
91 regulator-always-on;
92 regulator-boot-on;
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 };
96
97 pp3300_alw: regulator6 {
98 compatible = "regulator-fixed";
99 regulator-name = "pp3300_alw";
100 regulator-always-on;
101 regulator-boot-on;
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 };
105
106 /* system wide semi-regulated power rail from charger */
107 reg_vsys: regulator-vsys {
108 compatible = "regulator-fixed";
109 regulator-name = "vsys";
110 regulator-always-on;
111 regulator-boot-on;
112 };
113
114 reserved_memory: reserved-memory {
115 #address-cells = <2>;
116 #size-cells = <2>;
117 ranges;
118
119 scp_mem_reserved: memory@50000000 {
120 compatible = "shared-dma-pool";
121 reg = <0 0x50000000 0 0x2900000>;
122 no-map;
123 };
124 };
125
126 sound: mt8183-sound {
127 mediatek,platform = <&afe>;
128 pinctrl-names = "default",
129 "aud_tdm_out_on",
130 "aud_tdm_out_off";
131 pinctrl-0 = <&aud_pins_default>;
132 pinctrl-1 = <&aud_pins_tdm_out_on>;
133 pinctrl-2 = <&aud_pins_tdm_out_off>;
134 status = "okay";
135 };
136
137 btsco: bt-sco {
138 compatible = "linux,bt-sco";
139 };
140
141 wifi_pwrseq: wifi-pwrseq {
142 compatible = "mmc-pwrseq-simple";
143 pinctrl-names = "default";
144 pinctrl-0 = <&wifi_pins_pwrseq>;
145
146 /* Toggle WIFI_ENABLE to reset the chip. */
147 reset-gpios = <&pio 119 1>;
148 };
149
150 wifi_wakeup: wifi-wakeup {
151 compatible = "gpio-keys";
152 pinctrl-names = "default";
153 pinctrl-0 = <&wifi_pins_wakeup>;
154
155 wifi_wakeup_event: event-wowlan {
156 label = "Wake on WiFi";
157 gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
158 linux,code = <KEY_WAKEUP>;
159 wakeup-source;
160 };
161 };
162
163 tboard_thermistor1: thermal-sensor1 {
164 compatible = "generic-adc-thermal";
165 #thermal-sensor-cells = <0>;
166 io-channels = <&auxadc 0>;
167 io-channel-names = "sensor-channel";
168 temperature-lookup-table = < (-5000) 1553
169 0 1488
170 5000 1412
171 10000 1326
172 15000 1232
173 20000 1132
174 25000 1029
175 30000 925
176 35000 823
177 40000 726
178 45000 635
179 50000 552
180 55000 478
181 60000 411
182 65000 353
183 70000 303
184 75000 260
185 80000 222
186 85000 190
187 90000 163
188 95000 140
189 100000 121
190 105000 104
191 110000 90
192 115000 78
193 120000 67
194 125000 59>;
195 };
196
197 tboard_thermistor2: thermal-sensor2 {
198 compatible = "generic-adc-thermal";
199 #thermal-sensor-cells = <0>;
200 io-channels = <&auxadc 1>;
201 io-channel-names = "sensor-channel";
202 temperature-lookup-table = < (-5000) 1553
203 0 1488
204 5000 1412
205 10000 1326
206 15000 1232
207 20000 1132
208 25000 1029
209 30000 925
210 35000 823
211 40000 726
212 45000 635
213 50000 552
214 55000 478
215 60000 411
216 65000 353
217 70000 303
218 75000 260
219 80000 222
220 85000 190
221 90000 163
222 95000 140
223 100000 121
224 105000 104
225 110000 90
226 115000 78
227 120000 67
228 125000 59>;
229 };
230 };
231
232 &auxadc {
233 status = "okay";
234 };
235
236 &cci {
237 proc-supply = <&mt6358_vproc12_reg>;
238 };
239
240 &cpu0 {
241 proc-supply = <&mt6358_vproc12_reg>;
242 };
243
244 &cpu1 {
245 proc-supply = <&mt6358_vproc12_reg>;
246 };
247
248 &cpu2 {
249 proc-supply = <&mt6358_vproc12_reg>;
250 };
251
252 &cpu3 {
253 proc-supply = <&mt6358_vproc12_reg>;
254 };
255
256 &cpu4 {
257 proc-supply = <&mt6358_vproc11_reg>;
258 };
259
260 &cpu5 {
261 proc-supply = <&mt6358_vproc11_reg>;
262 };
263
264 &cpu6 {
265 proc-supply = <&mt6358_vproc11_reg>;
266 };
267
268 &cpu7 {
269 proc-supply = <&mt6358_vproc11_reg>;
270 };
271
272 &dsi0 {
273 status = "okay";
274 #address-cells = <1>;
275 #size-cells = <0>;
276 panel: panel@0 {
277 /* compatible will be set in board dts */
278 reg = <0>;
279 enable-gpios = <&pio 45 0>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&panel_pins_default>;
282 avdd-supply = <&ppvarn_lcd>;
283 avee-supply = <&ppvarp_lcd>;
284 pp1800-supply = <&pp1800_lcd>;
285 backlight = <&backlight_lcd0>;
286 rotation = <270>;
287 port {
288 panel_in: endpoint {
289 remote-endpoint = <&dsi_out>;
290 };
291 };
292 };
293
294 ports {
295 port {
296 dsi_out: endpoint {
297 remote-endpoint = <&panel_in>;
298 };
299 };
300 };
301 };
302
303 &gic {
304 mediatek,broken-save-restore-fw;
305 };
306
307 &gpu {
308 mali-supply = <&mt6358_vgpu_reg>;
309 };
310
311 &i2c0 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&i2c0_pins>;
314 status = "okay";
315 clock-frequency = <400000>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 };
319
320 &i2c1 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c1_pins>;
323 status = "okay";
324 clock-frequency = <100000>;
325 };
326
327 &i2c3 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c3_pins>;
330 status = "okay";
331 clock-frequency = <100000>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 };
335
336 &i2c5 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c5_pins>;
339 status = "okay";
340 clock-frequency = <100000>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 };
344
345 &i2c6 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c6_pins>;
348 status = "okay";
349 clock-frequency = <100000>;
350 };
351
352 &mipi_tx0 {
353 status = "okay";
354 };
355
356 &mmc0 {
357 status = "okay";
358 pinctrl-names = "default", "state_uhs";
359 pinctrl-0 = <&mmc0_pins_default>;
360 pinctrl-1 = <&mmc0_pins_uhs>;
361 bus-width = <8>;
362 max-frequency = <200000000>;
363 cap-mmc-highspeed;
364 mmc-hs200-1_8v;
365 mmc-hs400-1_8v;
366 cap-mmc-hw-reset;
367 no-sdio;
368 no-sd;
369 hs400-ds-delay = <0x12814>;
370 vmmc-supply = <&mt6358_vemc_reg>;
371 vqmmc-supply = <&mt6358_vio18_reg>;
372 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
373 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
374 non-removable;
375 };
376
377 &mmc1 {
378 status = "okay";
379 pinctrl-names = "default", "state_uhs";
380 pinctrl-0 = <&mmc1_pins_default>;
381 pinctrl-1 = <&mmc1_pins_uhs>;
382 vmmc-supply = <&mmc1_fixed_power>;
383 vqmmc-supply = <&mmc1_fixed_io>;
384 mmc-pwrseq = <&wifi_pwrseq>;
385 bus-width = <4>;
386 max-frequency = <200000000>;
387 cap-sd-highspeed;
388 sd-uhs-sdr50;
389 sd-uhs-sdr104;
390 keep-power-in-suspend;
391 wakeup-source;
392 cap-sdio-irq;
393 non-removable;
394 no-mmc;
395 no-sd;
396 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
397 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400
401 qca_wifi: qca-wifi@1 {
402 compatible = "qcom,ath10k";
403 reg = <1>;
404 };
405 };
406
407 &mt6358_vdram2_reg {
408 regulator-always-on;
409 };
410
411 &mt6358codec {
412 Avdd-supply = <&mt6358_vaud28_reg>;
413 };
414
415 &mt6358regulator {
416 vsys-ldo1-supply = <®_vsys>;
417 vsys-ldo2-supply = <®_vsys>;
418 vsys-ldo3-supply = <®_vsys>;
419 vsys-vcore-supply = <®_vsys>;
420 vsys-vdram1-supply = <®_vsys>;
421 vsys-vgpu-supply = <®_vsys>;
422 vsys-vmodem-supply = <®_vsys>;
423 vsys-vpa-supply = <®_vsys>;
424 vsys-vproc11-supply = <®_vsys>;
425 vsys-vproc12-supply = <®_vsys>;
426 vsys-vs1-supply = <®_vsys>;
427 vsys-vs2-supply = <®_vsys>;
428 vs1-ldo1-supply = <&mt6358_vs1_reg>;
429 vs2-ldo1-supply = <&mt6358_vdram1_reg>;
430 vs2-ldo2-supply = <&mt6358_vs2_reg>;
431 vs2-ldo3-supply = <&mt6358_vs2_reg>;
432 vs2-ldo4-supply = <&mt6358_vs2_reg>;
433 };
434
435 &mt6358_vgpu_reg {
436 regulator-max-microvolt = <900000>;
437
438 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
439 regulator-coupled-max-spread = <100000>;
440 };
441
442 &mt6358_vsim1_reg {
443 regulator-min-microvolt = <2700000>;
444 regulator-max-microvolt = <2700000>;
445 };
446
447 &mt6358_vsim2_reg {
448 regulator-min-microvolt = <2700000>;
449 regulator-max-microvolt = <2700000>;
450 };
451
452 &mt6358_vsram_gpu_reg {
453 regulator-min-microvolt = <850000>;
454 regulator-max-microvolt = <1000000>;
455
456 regulator-coupled-with = <&mt6358_vgpu_reg>;
457 regulator-coupled-max-spread = <100000>;
458 };
459
460 &pio {
461 aud_pins_default: audiopins {
462 pins-bus {
463 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
464 <PINMUX_GPIO98__FUNC_I2S2_BCK>,
465 <PINMUX_GPIO101__FUNC_I2S2_LRCK>,
466 <PINMUX_GPIO102__FUNC_I2S2_DI>,
467 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
468 <PINMUX_GPIO89__FUNC_I2S5_BCK>,
469 <PINMUX_GPIO90__FUNC_I2S5_LRCK>,
470 <PINMUX_GPIO91__FUNC_I2S5_DO>,
471 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
472 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
473 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
474 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
475 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
476 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
477 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
478 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
479 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
480 };
481 };
482
483 aud_pins_tdm_out_on: audiotdmouton {
484 pins-bus {
485 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
486 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
487 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
488 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
489 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
490 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
491 drive-strength = <6>;
492 };
493 };
494
495 aud_pins_tdm_out_off: audiotdmoutoff {
496 pins-bus {
497 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
498 <PINMUX_GPIO170__FUNC_GPIO170>,
499 <PINMUX_GPIO171__FUNC_GPIO171>,
500 <PINMUX_GPIO172__FUNC_GPIO172>,
501 <PINMUX_GPIO173__FUNC_GPIO173>,
502 <PINMUX_GPIO10__FUNC_GPIO10>;
503 input-enable;
504 bias-pull-down;
505 drive-strength = <2>;
506 };
507 };
508
509 bt_pins: bt-pins {
510 pins-bt-en {
511 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
512 output-low;
513 };
514 };
515
516 ec_ap_int_odl: ec-ap-int-odl {
517 pins1 {
518 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
519 input-enable;
520 bias-pull-up;
521 };
522 };
523
524 h1_int_od_l: h1-int-od-l {
525 pins1 {
526 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
527 input-enable;
528 };
529 };
530
531 i2c0_pins: i2c0 {
532 pins-bus {
533 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
534 <PINMUX_GPIO83__FUNC_SCL0>;
535 mediatek,pull-up-adv = <3>;
536 };
537 };
538
539 i2c1_pins: i2c1 {
540 pins-bus {
541 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
542 <PINMUX_GPIO84__FUNC_SCL1>;
543 mediatek,pull-up-adv = <3>;
544 };
545 };
546
547 i2c2_pins: i2c2 {
548 pins-bus {
549 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
550 <PINMUX_GPIO104__FUNC_SDA2>;
551 bias-disable;
552 };
553 };
554
555 i2c3_pins: i2c3 {
556 pins-bus {
557 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
558 <PINMUX_GPIO51__FUNC_SDA3>;
559 mediatek,pull-up-adv = <3>;
560 };
561 };
562
563 i2c4_pins: i2c4 {
564 pins-bus {
565 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
566 <PINMUX_GPIO106__FUNC_SDA4>;
567 bias-disable;
568 };
569 };
570
571 i2c5_pins: i2c5 {
572 pins-bus {
573 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
574 <PINMUX_GPIO49__FUNC_SDA5>;
575 mediatek,pull-up-adv = <3>;
576 };
577 };
578
579 i2c6_pins: i2c6 {
580 pins-bus {
581 pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
582 <PINMUX_GPIO12__FUNC_SDA6>;
583 bias-disable;
584 };
585 };
586
587 mmc0_pins_default: mmc0-pins-default {
588 pins-cmd-dat {
589 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
590 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
591 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
592 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
593 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
594 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
595 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
596 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
597 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
598 input-enable;
599 drive-strength = <MTK_DRIVE_14mA>;
600 mediatek,pull-up-adv = <01>;
601 };
602
603 pins-clk {
604 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
605 drive-strength = <MTK_DRIVE_14mA>;
606 mediatek,pull-down-adv = <10>;
607 };
608
609 pins-rst {
610 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
611 drive-strength = <MTK_DRIVE_14mA>;
612 mediatek,pull-down-adv = <01>;
613 };
614 };
615
616 mmc0_pins_uhs: mmc0-pins-uhs {
617 pins-cmd-dat {
618 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
619 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
620 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
621 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
622 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
623 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
624 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
625 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
626 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
627 input-enable;
628 drive-strength = <MTK_DRIVE_14mA>;
629 mediatek,pull-up-adv = <01>;
630 };
631
632 pins-clk {
633 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
634 drive-strength = <MTK_DRIVE_14mA>;
635 mediatek,pull-down-adv = <10>;
636 };
637
638 pins-ds {
639 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
640 drive-strength = <MTK_DRIVE_14mA>;
641 mediatek,pull-down-adv = <10>;
642 };
643
644 pins-rst {
645 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
646 drive-strength = <MTK_DRIVE_14mA>;
647 mediatek,pull-up-adv = <01>;
648 };
649 };
650
651 mmc1_pins_default: mmc1-pins-default {
652 pins-cmd-dat {
653 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
654 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
655 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
656 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
657 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
658 input-enable;
659 mediatek,pull-up-adv = <10>;
660 };
661
662 pins-clk {
663 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
664 input-enable;
665 mediatek,pull-down-adv = <10>;
666 };
667 };
668
669 mmc1_pins_uhs: mmc1-pins-uhs {
670 pins-cmd-dat {
671 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
672 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
673 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
674 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
675 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
676 drive-strength = <6>;
677 input-enable;
678 mediatek,pull-up-adv = <10>;
679 };
680
681 pins-clk {
682 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
683 drive-strength = <8>;
684 mediatek,pull-down-adv = <10>;
685 input-enable;
686 };
687 };
688
689 panel_pins_default: panel-pins-default {
690 panel-reset {
691 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
692 output-low;
693 bias-pull-up;
694 };
695 };
696
697 pwm0_pin_default: pwm0-pin-default {
698 pins1 {
699 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
700 output-high;
701 bias-pull-up;
702 };
703 pins2 {
704 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
705 };
706 };
707
708 scp_pins: scp {
709 pins-scp-uart {
710 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
711 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
712 };
713 };
714
715 spi0_pins: spi0 {
716 pins-spi {
717 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
718 <PINMUX_GPIO86__FUNC_GPIO86>,
719 <PINMUX_GPIO87__FUNC_SPI0_MO>,
720 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
721 bias-disable;
722 };
723 };
724
725 spi1_pins: spi1 {
726 pins-spi {
727 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
728 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
729 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
730 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
731 bias-disable;
732 };
733 };
734
735 spi2_pins: spi2 {
736 pins-spi {
737 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
738 <PINMUX_GPIO1__FUNC_SPI2_MO>,
739 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
740 bias-disable;
741 };
742 pins-spi-mi {
743 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
744 mediatek,pull-down-adv = <00>;
745 };
746 };
747
748 spi3_pins: spi3 {
749 pins-spi {
750 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
751 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
752 <PINMUX_GPIO23__FUNC_SPI3_MO>,
753 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
754 bias-disable;
755 };
756 };
757
758 spi4_pins: spi4 {
759 pins-spi {
760 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
761 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
762 <PINMUX_GPIO19__FUNC_SPI4_MO>,
763 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
764 bias-disable;
765 };
766 };
767
768 spi5_pins: spi5 {
769 pins-spi {
770 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
771 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
772 <PINMUX_GPIO15__FUNC_SPI5_MO>,
773 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
774 bias-disable;
775 };
776 };
777
778 uart0_pins_default: uart0-pins-default {
779 pins-rx {
780 pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
781 input-enable;
782 bias-pull-up;
783 };
784 pins-tx {
785 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
786 };
787 };
788
789 uart1_pins_default: uart1-pins-default {
790 pins-rx {
791 pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
792 input-enable;
793 bias-pull-up;
794 };
795 pins-tx {
796 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
797 };
798 pins-rts {
799 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
800 };
801 pins-cts {
802 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
803 input-enable;
804 };
805 };
806
807 uart1_pins_sleep: uart1-pins-sleep {
808 pins-rx {
809 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
810 input-enable;
811 bias-pull-up;
812 };
813 pins-tx {
814 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
815 };
816 pins-rts {
817 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
818 };
819 pins-cts {
820 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
821 input-enable;
822 };
823 };
824
825 wifi_pins_pwrseq: wifi-pins-pwrseq {
826 pins-wifi-enable {
827 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
828 output-low;
829 };
830 };
831
832 wifi_pins_wakeup: wifi-pins-wakeup {
833 pins-wifi-wakeup {
834 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
835 input-enable;
836 };
837 };
838 };
839
840 &pmic {
841 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
842 };
843
844 &pwm0 {
845 status = "okay";
846 pinctrl-names = "default";
847 pinctrl-0 = <&pwm0_pin_default>;
848 };
849
850 &scp {
851 status = "okay";
852
853 firmware-name = "mediatek/mt8183/scp.img";
854 pinctrl-names = "default";
855 pinctrl-0 = <&scp_pins>;
856
857 cros-ec-rpmsg {
858 compatible = "google,cros-ec-rpmsg";
859 mediatek,rpmsg-name = "cros-ec-rpmsg";
860 };
861 };
862
863 &mfg_async {
864 domain-supply = <&mt6358_vsram_gpu_reg>;
865 };
866
867 &mfg {
868 domain-supply = <&mt6358_vgpu_reg>;
869 };
870
871 &soc_data {
872 status = "okay";
873 };
874
875 &spi0 {
876 pinctrl-names = "default";
877 pinctrl-0 = <&spi0_pins>;
878 mediatek,pad-select = <0>;
879 status = "okay";
880 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
881
882 tpm@0 {
883 compatible = "google,cr50";
884 reg = <0>;
885 spi-max-frequency = <1000000>;
886 pinctrl-names = "default";
887 pinctrl-0 = <&h1_int_od_l>;
888 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
889 };
890 };
891
892 &spi1 {
893 pinctrl-names = "default";
894 pinctrl-0 = <&spi1_pins>;
895 mediatek,pad-select = <0>;
896 status = "okay";
897
898 w25q64dw: flash@0 {
899 compatible = "winbond,w25q64dw", "jedec,spi-nor";
900 reg = <0>;
901 spi-max-frequency = <25000000>;
902 };
903 };
904
905 &spi2 {
906 pinctrl-names = "default";
907 pinctrl-0 = <&spi2_pins>;
908 mediatek,pad-select = <0>;
909 status = "okay";
910
911 cros_ec: cros-ec@0 {
912 compatible = "google,cros-ec-spi";
913 reg = <0>;
914 spi-max-frequency = <3000000>;
915 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&ec_ap_int_odl>;
918 wakeup-source;
919
920 i2c_tunnel: i2c-tunnel {
921 compatible = "google,cros-ec-i2c-tunnel";
922 google,remote-bus = <1>;
923 #address-cells = <1>;
924 #size-cells = <0>;
925 };
926
927 usbc_extcon: extcon0 {
928 compatible = "google,extcon-usbc-cros-ec";
929 google,usb-port-id = <0>;
930 };
931
932 typec {
933 compatible = "google,cros-ec-typec";
934 #address-cells = <1>;
935 #size-cells = <0>;
936
937 usb_c0: connector@0 {
938 compatible = "usb-c-connector";
939 reg = <0>;
940 power-role = "dual";
941 data-role = "host";
942 try-power-role = "sink";
943 };
944 };
945 };
946 };
947
948 &spi3 {
949 pinctrl-names = "default";
950 pinctrl-0 = <&spi3_pins>;
951 mediatek,pad-select = <0>;
952 status = "disabled";
953 };
954
955 &spi4 {
956 pinctrl-names = "default";
957 pinctrl-0 = <&spi4_pins>;
958 mediatek,pad-select = <0>;
959 status = "disabled";
960 };
961
962 &spi5 {
963 pinctrl-names = "default";
964 pinctrl-0 = <&spi5_pins>;
965 mediatek,pad-select = <0>;
966 status = "disabled";
967 };
968
969 &ssusb {
970 dr_mode = "host";
971 wakeup-source;
972 vusb33-supply = <&mt6358_vusb_reg>;
973 status = "okay";
974 };
975
976 &thermal_zones {
977 tboard1 {
978 polling-delay = <1000>; /* milliseconds */
979 polling-delay-passive = <0>; /* milliseconds */
980 thermal-sensors = <&tboard_thermistor1>;
981 };
982
983 tboard2 {
984 polling-delay = <1000>; /* milliseconds */
985 polling-delay-passive = <0>; /* milliseconds */
986 thermal-sensors = <&tboard_thermistor2>;
987 };
988 };
989
990 &u3phy {
991 status = "okay";
992 };
993
994 &uart0 {
995 pinctrl-names = "default";
996 pinctrl-0 = <&uart0_pins_default>;
997 status = "okay";
998 };
999
1000 &uart1 {
1001 pinctrl-names = "default", "sleep";
1002 pinctrl-0 = <&uart1_pins_default>;
1003 pinctrl-1 = <&uart1_pins_sleep>;
1004 status = "okay";
1005 /delete-property/ interrupts;
1006 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
1007 <&pio 121 IRQ_TYPE_EDGE_FALLING>;
1008
1009 bluetooth: bluetooth {
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&bt_pins>;
1012 status = "okay";
1013 compatible = "qcom,qca6174-bt";
1014 enable-gpios = <&pio 120 0>;
1015 clocks = <&clk32k>;
1016 firmware-name = "nvm_00440302_i2s.bin";
1017 };
1018 };
1019
1020 &usb_host {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 vusb33-supply = <&mt6358_vusb_reg>;
1024 status = "okay";
1025
1026 hub@1 {
1027 compatible = "usb5e3,610";
1028 reg = <1>;
1029 };
1030 };
1031
1032 #include <arm/cros-ec-sbs.dtsi>
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