1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5 /dts-v1/;
6 #include "mt8186.dtsi"
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
12
13 / {
14 aliases {
15 i2c0 = &i2c0;
16 i2c1 = &i2c1;
17 i2c2 = &i2c2;
18 i2c3 = &i2c3;
19 i2c5 = &i2c5;
20 mmc0 = &mmc0;
21 mmc1 = &mmc1;
22 serial0 = &uart0;
23 };
24
25 chosen {
26 stdout-path = "serial0:115200n8";
27 };
28
29 memory@40000000 {
30 device_type = "memory";
31 /* The size should be filled in by the bootloader. */
32 reg = <0 0x40000000 0 0>;
33 };
34
35 backlight_lcd0: backlight-lcd0 {
36 compatible = "pwm-backlight";
37 pwms = <&pwm0 0 500000>;
38 power-supply = <&ppvar_sys>;
39 enable-gpios = <&pio 152 0>;
40 brightness-levels = <0 1023>;
41 num-interpolated-steps = <1023>;
42 default-brightness-level = <576>;
43 };
44
45 bt-sco {
46 compatible = "linux,bt-sco";
47 #sound-dai-cells = <0>;
48 };
49
50 dmic-codec {
51 compatible = "dmic-codec";
52 #sound-dai-cells = <0>;
53 num-channels = <2>;
54 wakeup-delay-ms = <50>;
55 };
56
57 gpio_keys: gpio-keys {
58 compatible = "gpio-keys";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pen_eject>;
61
62 pen_insert: pen-insert-switch {
63 label = "Pen Insert";
64 /* Insert = low, eject = high */
65 gpios = <&pio 18 GPIO_ACTIVE_LOW>;
66 wakeup-event-action = <EV_ACT_DEASSERTED>;
67 wakeup-source;
68 linux,code = <SW_PEN_INSERTED>;
69 linux,input-type = <EV_SW>;
70 };
71 };
72
73 pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx {
74 compatible = "regulator-fixed";
75 pinctrl-names = "default";
76 pinctrl-0 = <&en_pp1800_dpbrdg>;
77 gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
78 regulator-name = "pp1800_dpbrdg_dx";
79 enable-active-high;
80 vin-supply = <&mt6366_vio18_reg>;
81 };
82
83 pp3300_disp_x: regulator-pp3300-disp-x {
84 compatible = "regulator-fixed";
85 pinctrl-names = "default";
86 pinctrl-0 = <&edp_panel_fixed_pins>;
87 gpios = <&pio 153 GPIO_ACTIVE_HIGH>;
88 regulator-name = "pp3300_disp_x";
89 enable-active-high;
90 regulator-boot-on;
91 vin-supply = <&pp3300_z2>;
92 };
93
94 /* system wide LDO 3.3V power rail */
95 pp3300_z5: regulator-pp3300-ldo-z5 {
96 compatible = "regulator-fixed";
97 regulator-name = "pp3300_ldo_z5";
98 regulator-always-on;
99 regulator-boot-on;
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 vin-supply = <&ppvar_sys>;
103 };
104
105 /* separately switched 3.3V power rail */
106 pp3300_s3: regulator-pp3300-s3 {
107 compatible = "regulator-fixed";
108 regulator-name = "pp3300_s3";
109 /* automatically sequenced by PMIC EXT_PMIC_EN2 */
110 regulator-always-on;
111 regulator-boot-on;
112 vin-supply = <&pp3300_z2>;
113 };
114
115 /* system wide 3.3V power rail */
116 pp3300_z2: regulator-pp3300-z2 {
117 compatible = "regulator-fixed";
118 regulator-name = "pp3300_z2";
119 /* EN pin tied to pp4200_z2, which is controlled by EC */
120 regulator-always-on;
121 regulator-boot-on;
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 vin-supply = <&ppvar_sys>;
125 };
126
127 /* system wide 4.2V power rail */
128 pp4200_z2: regulator-pp4200-z2 {
129 compatible = "regulator-fixed";
130 regulator-name = "pp4200_z2";
131 /* controlled by EC */
132 regulator-always-on;
133 regulator-boot-on;
134 regulator-min-microvolt = <4200000>;
135 regulator-max-microvolt = <4200000>;
136 vin-supply = <&ppvar_sys>;
137 };
138
139 /* system wide switching 5.0V power rail */
140 pp5000_z2: regulator-pp5000-z2 {
141 compatible = "regulator-fixed";
142 regulator-name = "pp5000_z2";
143 /* controlled by EC */
144 regulator-always-on;
145 regulator-boot-on;
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
148 vin-supply = <&ppvar_sys>;
149 };
150
151 /* system wide semi-regulated power rail from battery or USB */
152 ppvar_sys: regulator-ppvar-sys {
153 compatible = "regulator-fixed";
154 regulator-name = "ppvar_sys";
155 regulator-always-on;
156 regulator-boot-on;
157 };
158
159 reserved_memory: reserved-memory {
160 #address-cells = <2>;
161 #size-cells = <2>;
162 ranges;
163
164 adsp_dma_mem: memory@61000000 {
165 compatible = "shared-dma-pool";
166 reg = <0 0x61000000 0 0x100000>;
167 no-map;
168 };
169
170 adsp_mem: memory@60000000 {
171 compatible = "shared-dma-pool";
172 reg = <0 0x60000000 0 0xA00000>;
173 no-map;
174 };
175
176 scp_mem: memory@50000000 {
177 compatible = "shared-dma-pool";
178 reg = <0 0x50000000 0 0x10a0000>;
179 no-map;
180 };
181 };
182
183 sound: sound {
184 compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound";
185 pinctrl-names = "aud_clk_mosi_off",
186 "aud_clk_mosi_on",
187 "aud_clk_miso_off",
188 "aud_clk_miso_on",
189 "aud_dat_miso_off",
190 "aud_dat_miso_on",
191 "aud_dat_mosi_off",
192 "aud_dat_mosi_on",
193 "aud_gpio_i2s0_off",
194 "aud_gpio_i2s0_on",
195 "aud_gpio_i2s1_off",
196 "aud_gpio_i2s1_on",
197 "aud_gpio_i2s2_off",
198 "aud_gpio_i2s2_on",
199 "aud_gpio_i2s3_off",
200 "aud_gpio_i2s3_on",
201 "aud_gpio_pcm_off",
202 "aud_gpio_pcm_on",
203 "aud_gpio_dmic_sec";
204 pinctrl-0 = <&aud_clk_mosi_off>;
205 pinctrl-1 = <&aud_clk_mosi_on>;
206 pinctrl-2 = <&aud_clk_miso_off>;
207 pinctrl-3 = <&aud_clk_miso_on>;
208 pinctrl-4 = <&aud_dat_miso_off>;
209 pinctrl-5 = <&aud_dat_miso_on>;
210 pinctrl-6 = <&aud_dat_mosi_off>;
211 pinctrl-7 = <&aud_dat_mosi_on>;
212 pinctrl-8 = <&aud_gpio_i2s0_off>;
213 pinctrl-9 = <&aud_gpio_i2s0_on>;
214 pinctrl-10 = <&aud_gpio_i2s1_off>;
215 pinctrl-11 = <&aud_gpio_i2s1_on>;
216 pinctrl-12 = <&aud_gpio_i2s2_off>;
217 pinctrl-13 = <&aud_gpio_i2s2_on>;
218 pinctrl-14 = <&aud_gpio_i2s3_off>;
219 pinctrl-15 = <&aud_gpio_i2s3_on>;
220 pinctrl-16 = <&aud_gpio_pcm_off>;
221 pinctrl-17 = <&aud_gpio_pcm_on>;
222 pinctrl-18 = <&aud_gpio_dmic_sec>;
223 mediatek,adsp = <&adsp>;
224 mediatek,platform = <&afe>;
225
226 audio-routing =
227 "Headphone", "HPOL",
228 "Headphone", "HPOR",
229 "IN1P", "Headset Mic",
230 "Speakers", "Speaker",
231 "HDMI1", "TX";
232
233 hs-playback-dai-link {
234 link-name = "I2S0";
235 dai-format = "i2s";
236 mediatek,clk-provider = "cpu";
237 codec {
238 sound-dai = <&rt5682s 0>;
239 };
240 };
241
242 hs-capture-dai-link {
243 link-name = "I2S1";
244 dai-format = "i2s";
245 mediatek,clk-provider = "cpu";
246 codec {
247 sound-dai = <&rt5682s 0>;
248 };
249 };
250
251 spk-share-dai-link {
252 link-name = "I2S2";
253 mediatek,clk-provider = "cpu";
254 };
255
256 spk-hdmi-playback-dai-link {
257 link-name = "I2S3";
258 dai-format = "i2s";
259 mediatek,clk-provider = "cpu";
260 /* RT1019P and IT6505 connected to the same I2S line */
261 codec {
262 sound-dai = <&it6505dptx>, <&rt1019p>;
263 };
264 };
265 };
266
267 rt1019p: speaker-codec {
268 compatible = "realtek,rt1019p";
269 pinctrl-names = "default";
270 pinctrl-0 = <&rt1019p_pins_default>;
271 #sound-dai-cells = <0>;
272 sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
273 };
274
275 usb_p1_vbus: regulator-usb-p1-vbus {
276 compatible = "regulator-fixed";
277 gpio = <&pio 148 GPIO_ACTIVE_HIGH>;
278 regulator-name = "vbus1";
279 regulator-min-microvolt = <5000000>;
280 regulator-max-microvolt = <5000000>;
281 enable-active-high;
282 vin-supply = <&pp5000_z2>;
283 };
284
285 wifi_pwrseq: wifi-pwrseq {
286 compatible = "mmc-pwrseq-simple";
287 pinctrl-names = "default";
288 pinctrl-0 = <&wifi_enable_pin>;
289 post-power-on-delay-ms = <50>;
290 reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
291 };
292
293 wifi_wakeup: wifi-wakeup {
294 compatible = "gpio-keys";
295 pinctrl-names = "default";
296 pinctrl-0 = <&wifi_wakeup_pin>;
297
298 wowlan-event {
299 label = "Wake on WiFi";
300 gpios = <&pio 7 GPIO_ACTIVE_LOW>;
301 linux,code = <KEY_WAKEUP>;
302 wakeup-source;
303 };
304 };
305 };
306
307 &adsp {
308 memory-region = <&adsp_dma_mem>, <&adsp_mem>;
309 status = "okay";
310 };
311
312 &afe {
313 status = "okay";
314 };
315
316 &cci {
317 proc-supply = <&mt6366_vproc12_reg>;
318 };
319
320 &cpu0 {
321 proc-supply = <&mt6366_vproc12_reg>;
322 };
323
324 &cpu1 {
325 proc-supply = <&mt6366_vproc12_reg>;
326 };
327
328 &cpu2 {
329 proc-supply = <&mt6366_vproc12_reg>;
330 };
331
332 &cpu3 {
333 proc-supply = <&mt6366_vproc12_reg>;
334 };
335
336 &cpu4 {
337 proc-supply = <&mt6366_vproc12_reg>;
338 };
339
340 &cpu5 {
341 proc-supply = <&mt6366_vproc12_reg>;
342 };
343
344 &cpu6 {
345 proc-supply = <&mt6366_vproc11_reg>;
346 };
347
348 &cpu7 {
349 proc-supply = <&mt6366_vproc11_reg>;
350 };
351
352 &dpi {
353 pinctrl-names = "default", "sleep";
354 pinctrl-0 = <&dpi_pins_default>;
355 pinctrl-1 = <&dpi_pins_sleep>;
356 status = "okay";
357 };
358
359 &dpi_out {
360 remote-endpoint = <&it6505_in>;
361 };
362
363 &dsi0 {
364 status = "okay";
365 };
366
367 &gic {
368 mediatek,broken-save-restore-fw;
369 };
370
371 &gpu {
372 mali-supply = <&mt6366_vgpu_reg>;
373 status = "okay";
374 };
375
376 &i2c0 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c0_pins>;
379 status = "okay";
380 };
381
382 &i2c1 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c1_pins>;
385 clock-frequency = <400000>;
386 i2c-scl-internal-delay-ns = <8000>;
387 status = "okay";
388 };
389
390 &i2c2 {
391 pinctrl-names = "default";
392 /*
393 * Trackpad pin put here to work around second source components
394 * sharing the pinmux in steelix designs.
395 */
396 pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>;
397 clock-frequency = <400000>;
398 i2c-scl-internal-delay-ns = <10000>;
399 status = "okay";
400
401 trackpad@15 {
402 compatible = "elan,ekth3000";
403 reg = <0x15>;
404 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
405 vcc-supply = <&pp3300_s3>;
406 wakeup-source;
407 };
408 };
409
410 &i2c3 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c3_pins>;
413 clock-frequency = <100000>;
414 status = "okay";
415
416 it6505dptx: dp-bridge@5c {
417 compatible = "ite,it6505";
418 reg = <0x5c>;
419 interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&it6505_pins>;
422 #sound-dai-cells = <0>;
423 ovdd-supply = <&mt6366_vsim2_reg>;
424 pwr18-supply = <&pp1800_dpbrdg_dx>;
425 reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>;
426
427 ports {
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 port@0 {
432 reg = <0>;
433
434 it6505_in: endpoint {
435 link-frequencies = /bits/ 64 <150000000>;
436 remote-endpoint = <&dpi_out>;
437 };
438 };
439
440 port@1 {
441 reg = <1>;
442 };
443 };
444 };
445 };
446
447 &i2c5 {
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c5_pins>;
450 status = "okay";
451
452 rt5682s: codec@1a {
453 compatible = "realtek,rt5682s";
454 reg = <0x1a>;
455 interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>;
456 #sound-dai-cells = <1>;
457 AVDD-supply = <&mt6366_vio18_reg>;
458 DBVDD-supply = <&mt6366_vio18_reg>;
459 LDO1-IN-supply = <&mt6366_vio18_reg>;
460 MICVDD-supply = <&pp3300_z2>;
461 realtek,jd-src = <1>;
462 };
463 };
464
465 &mfg0 {
466 domain-supply = <&mt6366_vsram_gpu_reg>;
467 };
468
469 &mfg1 {
470 domain-supply = <&mt6366_vgpu_reg>;
471 };
472
473 &mipi_tx0 {
474 status = "okay";
475 };
476
477 &mmc0 {
478 pinctrl-names = "default", "state_uhs";
479 pinctrl-0 = <&mmc0_pins_default>;
480 pinctrl-1 = <&mmc0_pins_uhs>;
481 bus-width = <8>;
482 max-frequency = <200000000>;
483 non-removable;
484 cap-mmc-highspeed;
485 mmc-hs200-1_8v;
486 mmc-hs400-1_8v;
487 supports-cqe;
488 no-sd;
489 no-sdio;
490 cap-mmc-hw-reset;
491 hs400-ds-delay = <0x11814>;
492 mediatek,hs400-ds-dly3 = <0x14>;
493 vmmc-supply = <&mt6366_vemc_reg>;
494 vqmmc-supply = <&mt6366_vio18_reg>;
495 status = "okay";
496 };
497
498 &mmc1 {
499 pinctrl-names = "default", "state_uhs", "state_eint";
500 pinctrl-0 = <&mmc1_pins_default>;
501 pinctrl-1 = <&mmc1_pins_uhs>;
502 pinctrl-2 = <&mmc1_pins_eint>;
503 /delete-property/ interrupts;
504 interrupt-names = "msdc", "sdio_wakeup";
505 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
506 <&pio 87 IRQ_TYPE_LEVEL_LOW>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 bus-width = <4>;
510 max-frequency = <200000000>;
511 cap-sd-highspeed;
512 sd-uhs-sdr104;
513 sd-uhs-sdr50;
514 keep-power-in-suspend;
515 wakeup-source;
516 cap-sdio-irq;
517 no-mmc;
518 no-sd;
519 non-removable;
520 vmmc-supply = <&pp3300_s3>;
521 vqmmc-supply = <&mt6366_vio18_reg>;
522 mmc-pwrseq = <&wifi_pwrseq>;
523 status = "okay";
524
525 bluetooth@2 {
526 compatible = "mediatek,mt7921s-bluetooth";
527 reg = <2>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&bt_pins_reset>;
530 reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>;
531 };
532 };
533
534 &nor_flash {
535 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&nor_pins_default>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540 status = "okay";
541
542 flash@0 {
543 compatible = "jedec,spi-nor";
544 reg = <0>;
545 spi-max-frequency = <39000000>;
546 };
547 };
548
549 &pio {
550 /* 185 lines */
551 gpio-line-names = "TP",
552 "TP",
553 "TP",
554 "I2S0_HP_DI",
555 "I2S3_DP_SPKR_DO",
556 "SAR_INT_ODL",
557 "BT_WAKE_AP_ODL",
558 "WIFI_INT_ODL",
559 "DPBRDG_INT_ODL",
560 "EDPBRDG_INT_ODL",
561 "EC_AP_HPD_OD",
562 "TCHPAD_INT_ODL",
563 "TCHSCR_INT_1V8_ODL",
564 "EC_AP_INT_ODL",
565 "EC_IN_RW_ODL",
566 "GSC_AP_INT_ODL",
567 /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
568 "AP_FLASH_WP_L",
569 "HP_INT_ODL",
570 "PEN_EJECT_OD",
571 "WCAM_PWDN_L",
572 "WCAM_RST_L",
573 "UCAM_SEN_EN",
574 "UCAM_RST_L",
575 "LTE_RESET_L",
576 "LTE_SAR_DETECT_L",
577 "I2S2_DP_SPK_MCK",
578 "I2S2_DP_SPKR_BCK",
579 "I2S2_DP_SPKR_LRCK",
580 "I2S2_DP_SPKR_DI (TP)",
581 "EN_PP1000_EDPBRDG",
582 "EN_PP1800_EDPBRDG",
583 "EN_PP3300_EDPBRDG",
584 "UART_GSC_TX_AP_RX",
585 "UART_AP_TX_GSC_RX",
586 "UART_DBGCON_TX_ADSP_RX",
587 "UART_ADSP_TX_DBGCON_RX",
588 "EN_PP1000_DPBRDG",
589 "TCHSCR_REPORT_DISABLE",
590 "EN_PP3300_DPBRDG",
591 "EN_PP1800_DPBRDG",
592 "SPI_AP_CLK_EC",
593 "SPI_AP_CS_EC_L",
594 "SPI_AP_DO_EC_DI",
595 "SPI_AP_DI_EC_DO",
596 "SPI_AP_CLK_GSC",
597 "SPI_AP_CS_GSC_L",
598 "SPI_AP_DO_GSC_DI",
599 "SPI_AP_DI_GSC_DO",
600 "UART_DBGCON_TX_SCP_RX",
601 "UART_SCP_TX_DBGCON_RX",
602 "EN_PP1200_CAM_X",
603 "EN_PP2800A_VCM_X",
604 "EN_PP2800A_UCAM_X",
605 "EN_PP2800A_WCAM_X",
606 "WLAN_MODULE_RST_L",
607 "EN_PP1200_UCAM_X",
608 "I2S1_HP_DO",
609 "I2S1_HP_BCK",
610 "I2S1_HP_LRCK",
611 "I2S1_HP_MCK",
612 "TCHSCR_RST_1V8_L",
613 "SPI_AP_CLK_ROM",
614 "SPI_AP_CS_ROM_L",
615 "SPI_AP_DO_ROM_DI",
616 "SPI_AP_DI_ROM_DO",
617 "NC",
618 "NC",
619 "EMMC_STRB",
620 "EMMC_CLK",
621 "EMMC_CMD",
622 "EMMC_RST_L",
623 "EMMC_DATA0",
624 "EMMC_DATA1",
625 "EMMC_DATA2",
626 "EMMC_DATA3",
627 "EMMC_DATA4",
628 "EMMC_DATA5",
629 "EMMC_DATA6",
630 "EMMC_DATA7",
631 "AP_KPCOL0",
632 "NC",
633 "NC",
634 "NC",
635 "TP",
636 "SDIO_CLK",
637 "SDIO_CMD",
638 "SDIO_DATA0",
639 "SDIO_DATA1",
640 "SDIO_DATA2",
641 "SDIO_DATA3",
642 "NC",
643 "NC",
644 "NC",
645 "NC",
646 "NC",
647 "NC",
648 "EDPBRDG_PWREN",
649 "BL_PWM_1V8",
650 "EDPBRDG_RST_L",
651 "MIPI_DPI_CLK",
652 "MIPI_DPI_VSYNC",
653 "MIPI_DPI_HSYNC",
654 "MIPI_DPI_DE",
655 "MIPI_DPI_D0",
656 "MIPI_DPI_D1",
657 "MIPI_DPI_D2",
658 "MIPI_DPI_D3",
659 "MIPI_DPI_D4",
660 "MIPI_DPI_D5",
661 "MIPI_DPI_D6",
662 "MIPI_DPI_DA7",
663 "MIPI_DPI_D8",
664 "MIPI_DPI_D9",
665 "MIPI_DPI_D10",
666 "MIPI_DPI_D11",
667 "PCM_BT_CLK",
668 "PCM_BT_SYNC",
669 "PCM_BT_DI",
670 "PCM_BT_DO",
671 "JTAG_TMS_TP",
672 "JTAG_TCK_TP",
673 "JTAG_TDI_TP",
674 "JTAG_TDO_TP",
675 "JTAG_TRSTN_TP",
676 "CLK_24M_WCAM",
677 "CLK_24M_UCAM",
678 "UCAM_DET_ODL",
679 "AP_I2C_EDPBRDG_SCL_1V8",
680 "AP_I2C_EDPBRDG_SDA_1V8",
681 "AP_I2C_TCHSCR_SCL_1V8",
682 "AP_I2C_TCHSCR_SDA_1V8",
683 "AP_I2C_TCHPAD_SCL_1V8",
684 "AP_I2C_TCHPAD_SDA_1V8",
685 "AP_I2C_DPBRDG_SCL_1V8",
686 "AP_I2C_DPBRDG_SDA_1V8",
687 "AP_I2C_WLAN_SCL_1V8",
688 "AP_I2C_WLAN_SDA_1V8",
689 "AP_I2C_AUD_SCL_1V8",
690 "AP_I2C_AUD_SDA_1V8",
691 "AP_I2C_TPM_SCL_1V8",
692 "AP_I2C_UCAM_SDA_1V8",
693 "AP_I2C_UCAM_SCL_1V8",
694 "AP_I2C_UCAM_SDA_1V8",
695 "AP_I2C_WCAM_SCL_1V8",
696 "AP_I2C_WCAM_SDA_1V8",
697 "SCP_I2C_SENSOR_SCL_1V8",
698 "SCP_I2C_SENSOR_SDA_1V8",
699 "AP_EC_WARM_RST_REQ",
700 "AP_XHCI_INIT_DONE",
701 "USB3_HUB_RST_L",
702 "EN_SPKR",
703 "BEEP_ON",
704 "AP_EDP_BKLTEN",
705 "EN_PP3300_DISP_X",
706 "EN_PP3300_SDBRDG_X",
707 "BT_KILL_1V8_L",
708 "WIFI_KILL_1V8_L",
709 "PWRAP_SPI0_CSN",
710 "PWRAP_SPI0_CK",
711 "PWRAP_SPI0_MO",
712 "PWRAP_SPI0_MI",
713 "SRCLKENA0",
714 "SRCLKENA1",
715 "SCP_VREQ_VAO",
716 "AP_RTC_CLK32K",
717 "AP_PMIC_WDTRST_L",
718 "AUD_CLK_MOSI",
719 "AUD_SYNC_MOSI",
720 "AUD_DAT_MOSI0",
721 "AUD_DAT_MOSI1",
722 "AUD_CLK_MISO",
723 "AUD_SYNC_MISO",
724 "AUD_DAT_MISO0",
725 "AUD_DAT_MISO1",
726 "NC",
727 "NC",
728 "DPBRDG_PWREN",
729 "DPBRDG_RST_L",
730 "LTE_W_DISABLE_L",
731 "LTE_SAR_DETECT_L",
732 "EN_PP3300_LTE_X",
733 "LTE_PWR_OFF_L",
734 "LTE_RESET_L",
735 "TP",
736 "TP";
737
738 aud_clk_mosi_off: aud-clk-mosi-off-pins {
739 pins-clk-sync {
740 pinmux = <PINMUX_GPIO166__FUNC_GPIO166>,
741 <PINMUX_GPIO167__FUNC_GPIO167>;
742 input-enable;
743 bias-pull-down;
744 };
745 };
746
747 aud_clk_mosi_on: aud-clk-mosi-on-pins {
748 pins-clk-sync {
749 pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>,
750 <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>;
751 };
752 };
753
754 aud_clk_miso_off: aud-clk-miso-off-pins {
755 pins-clk-sync {
756 pinmux = <PINMUX_GPIO170__FUNC_GPIO170>,
757 <PINMUX_GPIO171__FUNC_GPIO171>;
758 input-enable;
759 bias-pull-down;
760 };
761 };
762
763 aud_clk_miso_on: aud-clk-miso-on-pins {
764 pins-clk-sync {
765 pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>,
766 <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>;
767 };
768 };
769
770 aud_dat_mosi_off: aud-dat-mosi-off-pins {
771 pins-dat {
772 pinmux = <PINMUX_GPIO168__FUNC_GPIO168>,
773 <PINMUX_GPIO169__FUNC_GPIO169>;
774 input-enable;
775 bias-pull-down;
776 };
777 };
778
779 aud_dat_mosi_on: aud-dat-mosi-on-pins {
780 pins-dat {
781 pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>,
782 <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>;
783 };
784 };
785
786 aud_dat_miso_off: aud-dat-miso-off-pins {
787 pins-dat {
788 pinmux = <PINMUX_GPIO172__FUNC_GPIO172>,
789 <PINMUX_GPIO173__FUNC_GPIO173>;
790 input-enable;
791 bias-pull-down;
792 };
793 };
794
795 aud_dat_miso_on: aud-dat-miso-on-pins {
796 pins-dat {
797 pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>,
798 <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>;
799 input-schmitt-enable;
800 bias-disable;
801 };
802 };
803
804 aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins {
805 pins-sdata {
806 pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
807 };
808 };
809
810 aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins {
811 pins-sdata {
812 pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>;
813 };
814 };
815
816 aud_gpio_i2s1_off: aud-gpio-i2s-off-pins {
817 pins-clk-sdata {
818 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>,
819 <PINMUX_GPIO57__FUNC_GPIO57>,
820 <PINMUX_GPIO58__FUNC_GPIO58>,
821 <PINMUX_GPIO59__FUNC_GPIO59>;
822 output-low;
823 };
824 };
825
826 aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins {
827 pins-clk-sdata {
828 pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>,
829 <PINMUX_GPIO57__FUNC_I2S1_BCK>,
830 <PINMUX_GPIO58__FUNC_I2S1_LRCK>,
831 <PINMUX_GPIO59__FUNC_I2S1_MCK>;
832 };
833 };
834
835 aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins {
836 pins-cmd-dat {
837 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>,
838 <PINMUX_GPIO27__FUNC_GPIO27>;
839 output-low;
840 };
841 };
842
843 aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins {
844 pins-clk {
845 pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>,
846 <PINMUX_GPIO27__FUNC_I2S2_LRCK>;
847 drive-strength = <4>;
848 };
849 };
850
851 aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins {
852 pins-sdata {
853 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
854 output-low;
855 };
856 };
857
858 aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins {
859 pins-sdata {
860 pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>;
861 drive-strength = <4>;
862 };
863 };
864
865 aud_gpio_pcm_off: aud-gpio-pcm-off-pins {
866 pins-clk-sdata {
867 pinmux = <PINMUX_GPIO115__FUNC_GPIO115>,
868 <PINMUX_GPIO116__FUNC_GPIO116>,
869 <PINMUX_GPIO117__FUNC_GPIO117>,
870 <PINMUX_GPIO118__FUNC_GPIO118>;
871 output-low;
872 };
873 };
874
875 aud_gpio_pcm_on: aud-gpio-pcm-on-pins {
876 pins-clk-sdata {
877 pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>,
878 <PINMUX_GPIO116__FUNC_PCM_SYNC>,
879 <PINMUX_GPIO117__FUNC_PCM_DI>,
880 <PINMUX_GPIO118__FUNC_PCM_DO>;
881 };
882 };
883
884 aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins {
885 pins {
886 pinmux = <PINMUX_GPIO23__FUNC_GPIO23>;
887 output-low;
888 };
889 };
890
891 bt_pins_reset: bt-reset-pins {
892 pins-bt-reset {
893 pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
894 output-high;
895 };
896 };
897
898 dpi_pins_sleep: dpi-sleep-pins {
899 pins-cmd-dat {
900 pinmux = <PINMUX_GPIO103__FUNC_GPIO103>,
901 <PINMUX_GPIO104__FUNC_GPIO104>,
902 <PINMUX_GPIO105__FUNC_GPIO105>,
903 <PINMUX_GPIO106__FUNC_GPIO106>,
904 <PINMUX_GPIO107__FUNC_GPIO107>,
905 <PINMUX_GPIO108__FUNC_GPIO108>,
906 <PINMUX_GPIO109__FUNC_GPIO109>,
907 <PINMUX_GPIO110__FUNC_GPIO110>,
908 <PINMUX_GPIO111__FUNC_GPIO111>,
909 <PINMUX_GPIO112__FUNC_GPIO112>,
910 <PINMUX_GPIO113__FUNC_GPIO113>,
911 <PINMUX_GPIO114__FUNC_GPIO114>,
912 <PINMUX_GPIO101__FUNC_GPIO101>,
913 <PINMUX_GPIO100__FUNC_GPIO100>,
914 <PINMUX_GPIO102__FUNC_GPIO102>,
915 <PINMUX_GPIO99__FUNC_GPIO99>;
916 drive-strength = <10>;
917 output-low;
918 };
919 };
920
921 dpi_pins_default: dpi-default-pins {
922 pins-cmd-dat {
923 pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>,
924 <PINMUX_GPIO104__FUNC_DPI_DATA1>,
925 <PINMUX_GPIO105__FUNC_DPI_DATA2>,
926 <PINMUX_GPIO106__FUNC_DPI_DATA3>,
927 <PINMUX_GPIO107__FUNC_DPI_DATA4>,
928 <PINMUX_GPIO108__FUNC_DPI_DATA5>,
929 <PINMUX_GPIO109__FUNC_DPI_DATA6>,
930 <PINMUX_GPIO110__FUNC_DPI_DATA7>,
931 <PINMUX_GPIO111__FUNC_DPI_DATA8>,
932 <PINMUX_GPIO112__FUNC_DPI_DATA9>,
933 <PINMUX_GPIO113__FUNC_DPI_DATA10>,
934 <PINMUX_GPIO114__FUNC_DPI_DATA11>,
935 <PINMUX_GPIO101__FUNC_DPI_HSYNC>,
936 <PINMUX_GPIO100__FUNC_DPI_VSYNC>,
937 <PINMUX_GPIO102__FUNC_DPI_DE>,
938 <PINMUX_GPIO99__FUNC_DPI_PCLK>;
939 drive-strength = <10>;
940 };
941 };
942
943 ec_ap_int: cros-ec-int-pins {
944 pins-ec-ap-int-odl {
945 pinmux = <PINMUX_GPIO13__FUNC_GPIO13>;
946 input-enable;
947 };
948 };
949
950 edp_panel_fixed_pins: edp-panel-fixed-pins {
951 pins-vreg-en {
952 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
953 output-high;
954 };
955 };
956
957 en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins {
958 pins-vreg-en {
959 pinmux = <PINMUX_GPIO39__FUNC_GPIO39>;
960 output-low;
961 };
962 };
963
964 gsc_int: gsc-int-pins {
965 pins-gsc-ap-int-odl {
966 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
967 input-enable;
968 };
969 };
970
971 i2c0_pins: i2c0-pins {
972 pins-bus {
973 pinmux = <PINMUX_GPIO128__FUNC_SDA0>,
974 <PINMUX_GPIO127__FUNC_SCL0>;
975 bias-disable;
976 drive-strength = <4>;
977 input-enable;
978 };
979 };
980
981 i2c1_pins: i2c1-pins {
982 pins-bus {
983 pinmux = <PINMUX_GPIO130__FUNC_SDA1>,
984 <PINMUX_GPIO129__FUNC_SCL1>;
985 bias-disable;
986 drive-strength = <4>;
987 input-enable;
988 };
989 };
990
991 i2c2_pins: i2c2-pins {
992 pins-bus {
993 pinmux = <PINMUX_GPIO132__FUNC_SDA2>,
994 <PINMUX_GPIO131__FUNC_SCL2>;
995 bias-disable;
996 drive-strength = <4>;
997 input-enable;
998 };
999 };
1000
1001 i2c3_pins: i2c3-pins {
1002 pins-bus {
1003 pinmux = <PINMUX_GPIO134__FUNC_SDA3>,
1004 <PINMUX_GPIO133__FUNC_SCL3>;
1005 bias-disable;
1006 drive-strength = <4>;
1007 input-enable;
1008 };
1009 };
1010
1011 i2c5_pins: i2c5-pins {
1012 pins-bus {
1013 pinmux = <PINMUX_GPIO138__FUNC_SDA5>,
1014 <PINMUX_GPIO137__FUNC_SCL5>;
1015 bias-disable;
1016 drive-strength = <4>;
1017 input-enable;
1018 };
1019 };
1020
1021 it6505_pins: it6505-pins {
1022 pins-hpd {
1023 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>;
1024 input-enable;
1025 bias-pull-up;
1026 };
1027
1028 pins-int {
1029 pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
1030 input-enable;
1031 bias-pull-up;
1032 };
1033
1034 pins-reset {
1035 pinmux = <PINMUX_GPIO177__FUNC_GPIO177>;
1036 output-low;
1037 bias-pull-up;
1038 };
1039 };
1040
1041 mmc0_pins_default: mmc0-default-pins {
1042 pins-clk {
1043 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>;
1044 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1045 };
1046
1047 pins-cmd-dat {
1048 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>,
1049 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>,
1050 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>,
1051 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>,
1052 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>,
1053 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>,
1054 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>,
1055 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>,
1056 <PINMUX_GPIO69__FUNC_MSDC0_CMD>;
1057 input-enable;
1058 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1059 };
1060
1061 pins-rst {
1062 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>;
1063 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1064 };
1065 };
1066
1067 mmc0_pins_uhs: mmc0-uhs-pins {
1068 pins-clk {
1069 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>;
1070 drive-strength = <6>;
1071 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1072 };
1073
1074 pins-cmd-dat {
1075 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>,
1076 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>,
1077 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>,
1078 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>,
1079 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>,
1080 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>,
1081 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>,
1082 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>,
1083 <PINMUX_GPIO69__FUNC_MSDC0_CMD>;
1084 input-enable;
1085 drive-strength = <6>;
1086 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1087 };
1088
1089 pins-ds {
1090 pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>;
1091 drive-strength = <6>;
1092 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1093 };
1094
1095 pins-rst {
1096 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>;
1097 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1098 };
1099 };
1100
1101 mmc1_pins_default: mmc1-default-pins {
1102 pins-clk {
1103 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>;
1104 drive-strength = <6>;
1105 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1106 };
1107
1108 pins-cmd-dat {
1109 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>,
1110 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>,
1111 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>,
1112 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>,
1113 <PINMUX_GPIO85__FUNC_MSDC1_CMD>;
1114 input-enable;
1115 drive-strength = <6>;
1116 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1117 };
1118 };
1119
1120 mmc1_pins_uhs: mmc1-uhs-pins {
1121 pins-clk {
1122 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>;
1123 drive-strength = <6>;
1124 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1125 };
1126
1127 pins-cmd-dat {
1128 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>,
1129 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>,
1130 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>,
1131 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>,
1132 <PINMUX_GPIO85__FUNC_MSDC1_CMD>;
1133 input-enable;
1134 drive-strength = <8>;
1135 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1136 };
1137 };
1138
1139 mmc1_pins_eint: mmc1-eint-pins {
1140 pins-dat1 {
1141 pinmux = <PINMUX_GPIO87__FUNC_GPIO87>;
1142 input-enable;
1143 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1144 };
1145 };
1146
1147 nor_pins_default: nor-default-pins {
1148 pins-clk-dat {
1149 pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>,
1150 <PINMUX_GPIO61__FUNC_SPINOR_CK>,
1151 <PINMUX_GPIO64__FUNC_SPINOR_IO1>;
1152 drive-strength = <6>;
1153 bias-pull-down;
1154 };
1155
1156 pins-cs-dat {
1157 pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>,
1158 <PINMUX_GPIO65__FUNC_SPINOR_IO2>,
1159 <PINMUX_GPIO66__FUNC_SPINOR_IO3>;
1160 drive-strength = <6>;
1161 bias-pull-up;
1162 };
1163 };
1164
1165 pen_eject: pen-eject-pins {
1166 pins {
1167 pinmux = <PINMUX_GPIO18__FUNC_GPIO18>;
1168 input-enable;
1169 /* External pull-up. */
1170 bias-disable;
1171 };
1172 };
1173
1174 pwm0_pin: disp-pwm-pins {
1175 pins {
1176 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>;
1177 output-high;
1178 };
1179 };
1180
1181 rt1019p_pins_default: rt1019p-default-pins {
1182 pins-sdb {
1183 pinmux = <PINMUX_GPIO150__FUNC_GPIO150>;
1184 output-low;
1185 };
1186 };
1187
1188 scp_pins: scp-default-pins {
1189 pins-scp-uart {
1190 pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>,
1191 <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>;
1192 };
1193 };
1194
1195 spi1_pins: spi1-pins {
1196 pins-bus {
1197 pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>,
1198 <PINMUX_GPIO41__FUNC_SPI1_CSB_A>,
1199 <PINMUX_GPIO42__FUNC_SPI1_MO_A>,
1200 <PINMUX_GPIO43__FUNC_SPI1_MI_A>;
1201 bias-disable;
1202 input-enable;
1203 };
1204 };
1205
1206 spi2_pins: spi2-pins {
1207 pins-bus {
1208 pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>,
1209 <PINMUX_GPIO45__FUNC_GPIO45>,
1210 <PINMUX_GPIO46__FUNC_SPI2_MO_A>,
1211 <PINMUX_GPIO47__FUNC_SPI2_MI_A>;
1212 bias-disable;
1213 input-enable;
1214 };
1215 };
1216
1217 spmi_pins: spmi-pins {
1218 pins-bus {
1219 pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>,
1220 <PINMUX_GPIO184__FUNC_SPMI_SDA>;
1221 };
1222 };
1223
1224 touchscreen_pins: touchscreen-pins {
1225 pins-irq {
1226 pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
1227 input-enable;
1228 bias-pull-up;
1229 };
1230
1231 pins-reset {
1232 pinmux = <PINMUX_GPIO60__FUNC_GPIO60>;
1233 output-high;
1234 };
1235
1236 pins-report-sw {
1237 pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
1238 output-low;
1239 };
1240 };
1241
1242 trackpad_pin: trackpad-default-pins {
1243 pins-int-n {
1244 pinmux = <PINMUX_GPIO11__FUNC_GPIO11>;
1245 input-enable;
1246 bias-disable; /* pulled externally */
1247 };
1248 };
1249
1250 wifi_enable_pin: wifi-enable-pins {
1251 pins-wifi-enable {
1252 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
1253 };
1254 };
1255
1256 wifi_wakeup_pin: wifi-wakeup-pins {
1257 pins-wifi-wakeup {
1258 pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
1259 input-enable;
1260 };
1261 };
1262 };
1263
1264 &pwm0 {
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&pwm0_pin>;
1267 status = "okay";
1268 };
1269
1270 &pwrap {
1271 pmic {
1272 compatible = "mediatek,mt6366", "mediatek,mt6358";
1273 interrupt-controller;
1274 interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>;
1275 #interrupt-cells = <2>;
1276
1277 mt6366codec: codec {
1278 compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";
1279 Avdd-supply = <&mt6366_vaud28_reg>;
1280 mediatek,dmic-mode = <1>; /* one-wire */
1281 };
1282
1283 mt6366_regulators: regulators {
1284 compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator";
1285 vsys-ldo1-supply = <&pp4200_z2>;
1286 vsys-ldo2-supply = <&pp4200_z2>;
1287 vsys-ldo3-supply = <&pp4200_z2>;
1288 vsys-vcore-supply = <&pp4200_z2>;
1289 vsys-vdram1-supply = <&pp4200_z2>;
1290 vsys-vgpu-supply = <&pp4200_z2>;
1291 vsys-vmodem-supply = <&pp4200_z2>;
1292 vsys-vpa-supply = <&pp4200_z2>;
1293 vsys-vproc11-supply = <&pp4200_z2>;
1294 vsys-vproc12-supply = <&pp4200_z2>;
1295 vsys-vs1-supply = <&pp4200_z2>;
1296 vsys-vs2-supply = <&pp4200_z2>;
1297 vs1-ldo1-supply = <&mt6366_vs1_reg>;
1298 vs2-ldo1-supply = <&mt6366_vdram1_reg>;
1299 vs2-ldo2-supply = <&mt6366_vs2_reg>;
1300 vs2-ldo3-supply = <&mt6366_vs2_reg>;
1301
1302 vcore {
1303 regulator-name = "pp0750_dvdd_core";
1304 regulator-min-microvolt = <550000>;
1305 regulator-max-microvolt = <800000>;
1306 regulator-ramp-delay = <6250>;
1307 regulator-enable-ramp-delay = <200>;
1308 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1309 MT6397_BUCK_MODE_FORCE_PWM>;
1310 regulator-always-on;
1311 };
1312
1313 mt6366_vdram1_reg: vdram1 {
1314 regulator-name = "pp1125_emi_vdd2";
1315 regulator-min-microvolt = <1125000>;
1316 regulator-max-microvolt = <1125000>;
1317 regulator-ramp-delay = <12500>;
1318 regulator-enable-ramp-delay = <0>;
1319 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1320 MT6397_BUCK_MODE_FORCE_PWM>;
1321 regulator-always-on;
1322 };
1323
1324 mt6366_vgpu_reg: vgpu {
1325 /*
1326 * Called "ppvar_dvdd_gpu" in the schematic.
1327 * Called "ppvar_dvdd_vgpu" here to match
1328 * regulator coupling requirements.
1329 */
1330 regulator-name = "ppvar_dvdd_vgpu";
1331 regulator-min-microvolt = <500000>;
1332 regulator-max-microvolt = <950000>;
1333 regulator-ramp-delay = <6250>;
1334 regulator-enable-ramp-delay = <200>;
1335 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1336 MT6397_BUCK_MODE_FORCE_PWM>;
1337 regulator-coupled-with = <&mt6366_vsram_gpu_reg>;
1338 regulator-coupled-max-spread = <10000>;
1339 };
1340
1341 mt6366_vproc11_reg: vproc11 {
1342 regulator-name = "ppvar_dvdd_proc_bc_mt6366";
1343 regulator-min-microvolt = <600000>;
1344 regulator-max-microvolt = <1200000>;
1345 regulator-ramp-delay = <6250>;
1346 regulator-enable-ramp-delay = <200>;
1347 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1348 MT6397_BUCK_MODE_FORCE_PWM>;
1349 regulator-always-on;
1350 };
1351
1352 mt6366_vproc12_reg: vproc12 {
1353 regulator-name = "ppvar_dvdd_proc_lc";
1354 regulator-min-microvolt = <600000>;
1355 regulator-max-microvolt = <1200000>;
1356 regulator-ramp-delay = <6250>;
1357 regulator-enable-ramp-delay = <200>;
1358 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO
1359 MT6397_BUCK_MODE_FORCE_PWM>;
1360 regulator-always-on;
1361 };
1362
1363 mt6366_vs1_reg: vs1 {
1364 regulator-name = "pp2000_vs1";
1365 regulator-min-microvolt = <2000000>;
1366 regulator-max-microvolt = <2000000>;
1367 regulator-ramp-delay = <12500>;
1368 regulator-enable-ramp-delay = <0>;
1369 regulator-always-on;
1370 };
1371
1372 mt6366_vs2_reg: vs2 {
1373 regulator-name = "pp1350_vs2";
1374 regulator-min-microvolt = <1350000>;
1375 regulator-max-microvolt = <1350000>;
1376 regulator-ramp-delay = <12500>;
1377 regulator-enable-ramp-delay = <0>;
1378 regulator-always-on;
1379 };
1380
1381 va12 {
1382 regulator-name = "pp1200_va12";
1383 regulator-min-microvolt = <1200000>;
1384 regulator-max-microvolt = <1200000>;
1385 regulator-enable-ramp-delay = <270>;
1386 regulator-always-on;
1387 };
1388
1389 mt6366_vaud28_reg: vaud28 {
1390 regulator-name = "pp2800_vaud28";
1391 regulator-min-microvolt = <2800000>;
1392 regulator-max-microvolt = <2800000>;
1393 regulator-enable-ramp-delay = <270>;
1394 };
1395
1396 mt6366_vaux18_reg: vaux18 {
1397 regulator-name = "pp1840_vaux18";
1398 regulator-min-microvolt = <1800000>;
1399 regulator-max-microvolt = <1840000>;
1400 regulator-enable-ramp-delay = <270>;
1401 };
1402
1403 mt6366_vbif28_reg: vbif28 {
1404 regulator-name = "pp2800_vbif28";
1405 regulator-min-microvolt = <2800000>;
1406 regulator-max-microvolt = <2800000>;
1407 regulator-enable-ramp-delay = <270>;
1408 };
1409
1410 mt6366_vcn18_reg: vcn18 {
1411 regulator-name = "pp1800_vcn18_x";
1412 regulator-min-microvolt = <1800000>;
1413 regulator-max-microvolt = <1800000>;
1414 regulator-enable-ramp-delay = <270>;
1415 };
1416
1417 mt6366_vcn28_reg: vcn28 {
1418 regulator-name = "pp2800_vcn28_x";
1419 regulator-min-microvolt = <2800000>;
1420 regulator-max-microvolt = <2800000>;
1421 regulator-enable-ramp-delay = <270>;
1422 };
1423
1424 mt6366_vefuse_reg: vefuse {
1425 regulator-name = "pp1800_vefuse";
1426 regulator-min-microvolt = <1800000>;
1427 regulator-max-microvolt = <1800000>;
1428 regulator-enable-ramp-delay = <270>;
1429 };
1430
1431 mt6366_vfe28_reg: vfe28 {
1432 regulator-name = "pp2800_vfe28_x";
1433 regulator-min-microvolt = <2800000>;
1434 regulator-max-microvolt = <2800000>;
1435 regulator-enable-ramp-delay = <270>;
1436 };
1437
1438 mt6366_vemc_reg: vemc {
1439 regulator-name = "pp3000_vemc";
1440 regulator-min-microvolt = <3000000>;
1441 regulator-max-microvolt = <3000000>;
1442 regulator-enable-ramp-delay = <60>;
1443 };
1444
1445 mt6366_vibr_reg: vibr {
1446 regulator-name = "pp2800_vibr_x";
1447 regulator-min-microvolt = <2800000>;
1448 regulator-max-microvolt = <2800000>;
1449 regulator-enable-ramp-delay = <60>;
1450 };
1451
1452 mt6366_vio18_reg: vio18 {
1453 regulator-name = "pp1800_vio18_s3";
1454 regulator-min-microvolt = <1800000>;
1455 regulator-max-microvolt = <1800000>;
1456 regulator-enable-ramp-delay = <2700>;
1457 regulator-always-on;
1458 };
1459
1460 mt6366_vio28_reg: vio28 {
1461 regulator-name = "pp2800_vio28_x";
1462 regulator-min-microvolt = <2800000>;
1463 regulator-max-microvolt = <2800000>;
1464 regulator-enable-ramp-delay = <270>;
1465 };
1466
1467 mt6366_vm18_reg: vm18 {
1468 regulator-name = "pp1800_emi_vdd1";
1469 regulator-min-microvolt = <1800000>;
1470 regulator-max-microvolt = <1840000>;
1471 regulator-enable-ramp-delay = <325>;
1472 regulator-always-on;
1473 };
1474
1475 mt6366_vmc_reg: vmc {
1476 regulator-name = "pp3000_vmc";
1477 regulator-min-microvolt = <3000000>;
1478 regulator-max-microvolt = <3000000>;
1479 regulator-enable-ramp-delay = <60>;
1480 };
1481
1482 mt6366_vmddr_reg: vmddr {
1483 regulator-name = "pm0750_emi_vmddr";
1484 regulator-min-microvolt = <700000>;
1485 regulator-max-microvolt = <750000>;
1486 regulator-enable-ramp-delay = <325>;
1487 regulator-always-on;
1488 };
1489
1490 mt6366_vmch_reg: vmch {
1491 regulator-name = "pp3000_vmch";
1492 regulator-min-microvolt = <3000000>;
1493 regulator-max-microvolt = <3000000>;
1494 regulator-enable-ramp-delay = <60>;
1495 };
1496
1497 mt6366_vcn33_reg: vcn33 {
1498 regulator-name = "pp3300_vcn33_x";
1499 regulator-min-microvolt = <3300000>;
1500 regulator-max-microvolt = <3300000>;
1501 regulator-enable-ramp-delay = <270>;
1502 };
1503
1504 vdram2 {
1505 regulator-name = "pp0600_emi_vddq";
1506 regulator-min-microvolt = <600000>;
1507 regulator-max-microvolt = <600000>;
1508 regulator-enable-ramp-delay = <3300>;
1509 regulator-always-on;
1510 };
1511
1512 mt6366_vrf12_reg: vrf12 {
1513 regulator-name = "pp1200_vrf12_x";
1514 regulator-min-microvolt = <1200000>;
1515 regulator-max-microvolt = <1200000>;
1516 regulator-enable-ramp-delay = <120>;
1517 };
1518
1519 mt6366_vrf18_reg: vrf18 {
1520 regulator-name = "pp1800_vrf18_x";
1521 regulator-min-microvolt = <1800000>;
1522 regulator-max-microvolt = <1800000>;
1523 regulator-enable-ramp-delay = <120>;
1524 };
1525
1526 vsim1 {
1527 regulator-name = "pp1860_vsim1_x";
1528 regulator-min-microvolt = <1800000>;
1529 regulator-max-microvolt = <1860000>;
1530 regulator-enable-ramp-delay = <540>;
1531 };
1532
1533 mt6366_vsim2_reg: vsim2 {
1534 regulator-name = "pp2760_vsim2_x";
1535 regulator-min-microvolt = <2700000>;
1536 regulator-max-microvolt = <2760000>;
1537 regulator-enable-ramp-delay = <540>;
1538 };
1539
1540 mt6366_vsram_gpu_reg: vsram-gpu {
1541 regulator-name = "pp0900_dvdd_sram_gpu";
1542 regulator-min-microvolt = <850000>;
1543 regulator-max-microvolt = <1050000>;
1544 regulator-ramp-delay = <6250>;
1545 regulator-enable-ramp-delay = <240>;
1546 regulator-coupled-with = <&mt6366_vgpu_reg>;
1547 regulator-coupled-max-spread = <10000>;
1548 };
1549
1550 mt6366_vsram_others_reg: vsram-others {
1551 regulator-name = "pp0900_dvdd_sram_core";
1552 regulator-min-microvolt = <900000>;
1553 regulator-max-microvolt = <900000>;
1554 regulator-ramp-delay = <6250>;
1555 regulator-enable-ramp-delay = <240>;
1556 regulator-always-on;
1557 };
1558
1559 mt6366_vsram_proc11_reg: vsram-proc11 {
1560 regulator-name = "pp0900_dvdd_sram_bc";
1561 regulator-min-microvolt = <850000>;
1562 regulator-max-microvolt = <1120000>;
1563 regulator-ramp-delay = <6250>;
1564 regulator-enable-ramp-delay = <240>;
1565 regulator-always-on;
1566 };
1567
1568 mt6366_vsram_proc12_reg: vsram-proc12 {
1569 regulator-name = "pp0900_dvdd_sram_lc";
1570 regulator-min-microvolt = <850000>;
1571 regulator-max-microvolt = <1120000>;
1572 regulator-ramp-delay = <6250>;
1573 regulator-enable-ramp-delay = <240>;
1574 regulator-always-on;
1575 };
1576
1577 vusb {
1578 regulator-name = "pp3070_vusb";
1579 regulator-min-microvolt = <3000000>;
1580 regulator-max-microvolt = <3070000>;
1581 regulator-enable-ramp-delay = <270>;
1582 regulator-always-on;
1583 };
1584
1585 vxo22 {
1586 regulator-name = "pp2240_vxo22";
1587 regulator-min-microvolt = <2200000>;
1588 regulator-max-microvolt = <2240000>;
1589 regulator-enable-ramp-delay = <120>;
1590 /* Feeds DCXO internally */
1591 regulator-always-on;
1592 };
1593 };
1594
1595 rtc {
1596 compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc";
1597 };
1598 };
1599 };
1600
1601 &scp {
1602 pinctrl-names = "default";
1603 pinctrl-0 = <&scp_pins>;
1604 firmware-name = "mediatek/mt8186/scp.img";
1605 memory-region = <&scp_mem>;
1606 status = "okay";
1607
1608 cros-ec-rpmsg {
1609 compatible = "google,cros-ec-rpmsg";
1610 mediatek,rpmsg-name = "cros-ec-rpmsg";
1611 };
1612 };
1613
1614 &spi1 {
1615 pinctrl-names = "default";
1616 pinctrl-0 = <&spi1_pins>;
1617 mediatek,pad-select = <0>;
1618 status = "okay";
1619
1620 cros_ec: ec@0 {
1621 compatible = "google,cros-ec-spi";
1622 reg = <0>;
1623 interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>;
1624 pinctrl-names = "default";
1625 pinctrl-0 = <&ec_ap_int>;
1626 spi-max-frequency = <1000000>;
1627
1628 i2c_tunnel: i2c-tunnel {
1629 compatible = "google,cros-ec-i2c-tunnel";
1630 google,remote-bus = <1>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1633 };
1634
1635 typec {
1636 compatible = "google,cros-ec-typec";
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639
1640 usb_c0: connector@0 {
1641 compatible = "usb-c-connector";
1642 reg = <0>;
1643 label = "left";
1644 power-role = "dual";
1645 data-role = "host";
1646 try-power-role = "source";
1647 };
1648
1649 usb_c1: connector@1 {
1650 compatible = "usb-c-connector";
1651 reg = <1>;
1652 label = "right";
1653 power-role = "dual";
1654 data-role = "host";
1655 try-power-role = "source";
1656 };
1657 };
1658 };
1659 };
1660
1661 &spi2 {
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&spi2_pins>;
1664 cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>;
1665 mediatek,pad-select = <0>;
1666 status = "okay";
1667
1668 tpm@0 {
1669 compatible = "google,cr50";
1670 reg = <0>;
1671 interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&gsc_int>;
1674 spi-max-frequency = <1000000>;
1675 };
1676 };
1677
1678 &ssusb0 {
1679 status = "okay";
1680 };
1681
1682 &ssusb1 {
1683 status = "okay";
1684 };
1685
1686 &u3phy0 {
1687 status = "okay";
1688 };
1689
1690 &u3phy1 {
1691 status = "okay";
1692 };
1693
1694 &uart0 {
1695 status = "okay";
1696 };
1697
1698 &usb_host0 {
1699 vbus-supply = <&pp3300_s3>;
1700 status = "okay";
1701 };
1702
1703 &usb_host1 {
1704 vbus-supply = <&usb_p1_vbus>;
1705 status = "okay";
1706 };
1707
1708 &watchdog {
1709 mediatek,reset-by-toprgu;
1710 };
1711
1712 #include <arm/cros-ec-keyboard.dtsi>
1713 #include <arm/cros-ec-sbs.dtsi>
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