1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Ben Lok <ben.lok@mediatek.com>
5 * Macpaul Lin <macpaul.lin@mediatek.com>
6 */
7 /dts-v1/;
8
9 #include "mt8195.dtsi"
10 #include "mt6359.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
16 #include <dt-bindings/spmi/spmi.h>
17 #include <dt-bindings/usb/pd.h>
18
19 / {
20 model = "MediaTek Genio 1200 EVK-P1V2-EMMC";
21 compatible = "mediatek,mt8395-evk", "mediatek,mt8395",
22 "mediatek,mt8195";
23
24 aliases {
25 serial0 = &uart0;
26 ethernet0 = ð
27 };
28
29 chosen {
30 stdout-path = "serial0:921600n8";
31 };
32
33 firmware {
34 optee {
35 compatible = "linaro,optee-tz";
36 method = "smc";
37 };
38 };
39
40 memory@40000000 {
41 device_type = "memory";
42 reg = <0 0x40000000 0x2 0x00000000>;
43 };
44
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 /*
51 * 12 MiB reserved for OP-TEE (BL32)
52 * +-----------------------+ 0x43e0_0000
53 * | SHMEM 2MiB |
54 * +-----------------------+ 0x43c0_0000
55 * | | TA_RAM 8MiB |
56 * + TZDRAM +--------------+ 0x4340_0000
57 * | | TEE_RAM 2MiB |
58 * +-----------------------+ 0x4320_0000
59 */
60 optee_reserved: optee@43200000 {
61 no-map;
62 reg = <0 0x43200000 0 0x00c00000>;
63 };
64
65 scp_mem: memory@50000000 {
66 compatible = "shared-dma-pool";
67 reg = <0 0x50000000 0 0x2900000>;
68 no-map;
69 };
70
71 vpu_mem: memory@53000000 {
72 compatible = "shared-dma-pool";
73 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
74 };
75
76 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
77 bl31_secmon_mem: memory@54600000 {
78 no-map;
79 reg = <0 0x54600000 0x0 0x200000>;
80 };
81
82 snd_dma_mem: memory@60000000 {
83 compatible = "shared-dma-pool";
84 reg = <0 0x60000000 0 0x1100000>;
85 no-map;
86 };
87
88 apu_mem: memory@62000000 {
89 compatible = "shared-dma-pool";
90 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
91 };
92 };
93
94 backlight_lcd0: backlight-lcd0 {
95 compatible = "pwm-backlight";
96 pwms = <&disp_pwm0 0 500000>;
97 enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
98 brightness-levels = <0 1023>;
99 num-interpolated-steps = <1023>;
100 default-brightness-level = <576>;
101 };
102
103 backlight_lcd1: backlight-lcd1 {
104 compatible = "pwm-backlight";
105 pwms = <&disp_pwm1 0 500000>;
106 enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
107 brightness-levels = <0 1023>;
108 num-interpolated-steps = <1023>;
109 default-brightness-level = <576>;
110 };
111
112 can_clk: can-clk {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <20000000>;
116 clock-output-names = "can-clk";
117 };
118
119 edp_panel_fixed_3v3: regulator-0 {
120 compatible = "regulator-fixed";
121 regulator-name = "edp_panel_3v3";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 enable-active-high;
125 gpio = <&pio 6 GPIO_ACTIVE_HIGH>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&edp_panel_3v3_en_pins>;
128 };
129
130 edp_panel_fixed_12v: regulator-1 {
131 compatible = "regulator-fixed";
132 regulator-name = "edp_backlight_12v";
133 regulator-min-microvolt = <12000000>;
134 regulator-max-microvolt = <12000000>;
135 enable-active-high;
136 gpio = <&pio 96 GPIO_ACTIVE_HIGH>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&edp_panel_12v_en_pins>;
139 };
140
141 keys: gpio-keys {
142 compatible = "gpio-keys";
143
144 button-volume-up {
145 wakeup-source;
146 debounce-interval = <100>;
147 gpios = <&pio 106 GPIO_ACTIVE_LOW>;
148 label = "volume_up";
149 linux,code = <KEY_VOLUMEUP>;
150 };
151 };
152
153 wifi_fixed_3v3: regulator-2 {
154 compatible = "regulator-fixed";
155 regulator-name = "wifi_3v3";
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
158 gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
159 enable-active-high;
160 regulator-always-on;
161 };
162 };
163
164 &disp_pwm0 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm0_default_pins>;
167 status = "okay";
168 };
169
170 &dmic_codec {
171 wakeup-delay-ms = <200>;
172 };
173
174 ð {
175 phy-mode ="rgmii-rxid";
176 phy-handle = <ð_phy0>;
177 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
178 snps,reset-delays-us = <0 10000 10000>;
179 mediatek,tx-delay-ps = <2030>;
180 mediatek,mac-wol;
181 pinctrl-names = "default", "sleep";
182 pinctrl-0 = <ð_default_pins>;
183 pinctrl-1 = <ð_sleep_pins>;
184 status = "okay";
185
186 mdio {
187 compatible = "snps,dwmac-mdio";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 eth_phy0: eth-phy0@1 {
191 compatible = "ethernet-phy-id001c.c916";
192 reg = <0x1>;
193 };
194 };
195 };
196
197 &i2c0 {
198 clock-frequency = <400000>;
199 pinctrl-0 = <&i2c0_pins>;
200 pinctrl-names = "default";
201 status = "okay";
202 };
203
204 &i2c1 {
205 clock-frequency = <400000>;
206 pinctrl-0 = <&i2c1_pins>;
207 pinctrl-names = "default";
208 status = "okay";
209
210 touchscreen@5d {
211 compatible = "goodix,gt9271";
212 reg = <0x5d>;
213 interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>;
214 irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
215 reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
216 AVDD28-supply = <&mt6360_ldo1>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&touch_pins>;
219 };
220 };
221
222 &i2c2 {
223 clock-frequency = <400000>;
224 pinctrl-0 = <&i2c2_pins>;
225 pinctrl-names = "default";
226 status = "okay";
227 };
228
229 &i2c6 {
230 clock-frequency = <400000>;
231 pinctrl-0 = <&i2c6_pins>;
232 pinctrl-names = "default";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 status = "okay";
236
237 mt6360: pmic@34 {
238 compatible = "mediatek,mt6360";
239 reg = <0x34>;
240 interrupt-parent = <&pio>;
241 interrupts = <128 IRQ_TYPE_EDGE_FALLING>;
242 interrupt-names = "IRQB";
243 interrupt-controller;
244 #interrupt-cells = <1>;
245 pinctrl-0 = <&mt6360_pins>;
246
247 charger {
248 compatible = "mediatek,mt6360-chg";
249 richtek,vinovp-microvolt = <14500000>;
250
251 otg_vbus_regulator: usb-otg-vbus-regulator {
252 regulator-name = "usb-otg-vbus";
253 regulator-min-microvolt = <4425000>;
254 regulator-max-microvolt = <5825000>;
255 };
256 };
257
258 regulator {
259 compatible = "mediatek,mt6360-regulator";
260 LDO_VIN3-supply = <&mt6360_buck2>;
261
262 mt6360_buck1: buck1 {
263 regulator-name = "emi_vdd2";
264 regulator-min-microvolt = <300000>;
265 regulator-max-microvolt = <1300000>;
266 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
267 MT6360_OPMODE_LP
268 MT6360_OPMODE_ULP>;
269 regulator-always-on;
270 };
271
272 mt6360_buck2: buck2 {
273 regulator-name = "emi_vddq";
274 regulator-min-microvolt = <300000>;
275 regulator-max-microvolt = <1300000>;
276 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
277 MT6360_OPMODE_LP
278 MT6360_OPMODE_ULP>;
279 regulator-always-on;
280 };
281
282 mt6360_ldo1: ldo1 {
283 regulator-name = "tp1_p3v0";
284 regulator-min-microvolt = <3300000>;
285 regulator-max-microvolt = <3300000>;
286 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
287 MT6360_OPMODE_LP>;
288 regulator-always-on;
289 };
290
291 mt6360_ldo2: ldo2 {
292 regulator-name = "panel1_p1v8";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <1800000>;
295 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
296 MT6360_OPMODE_LP>;
297 };
298
299 mt6360_ldo3: ldo3 {
300 regulator-name = "vmc_pmu";
301 regulator-min-microvolt = <1200000>;
302 regulator-max-microvolt = <3600000>;
303 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
304 MT6360_OPMODE_LP>;
305 };
306
307 mt6360_ldo5: ldo5 {
308 regulator-name = "vmch_pmu";
309 regulator-min-microvolt = <2700000>;
310 regulator-max-microvolt = <3600000>;
311 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
312 MT6360_OPMODE_LP>;
313 };
314
315 /* This is a measure point, which name is mt6360_ldo1 on schematic */
316 mt6360_ldo6: ldo6 {
317 regulator-name = "mt6360_ldo1";
318 regulator-min-microvolt = <500000>;
319 regulator-max-microvolt = <2100000>;
320 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
321 MT6360_OPMODE_LP>;
322 };
323
324 mt6360_ldo7: ldo7 {
325 regulator-name = "emi_vmddr_en";
326 regulator-min-microvolt = <500000>;
327 regulator-max-microvolt = <2100000>;
328 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
329 MT6360_OPMODE_LP>;
330 regulator-always-on;
331 };
332 };
333 };
334 };
335
336 &mfg0 {
337 domain-supply = <&mt6315_7_vbuck1>;
338 };
339
340 &mmc0 {
341 status = "okay";
342 pinctrl-names = "default", "state_uhs";
343 pinctrl-0 = <&mmc0_default_pins>;
344 pinctrl-1 = <&mmc0_uhs_pins>;
345 bus-width = <8>;
346 max-frequency = <200000000>;
347 cap-mmc-highspeed;
348 mmc-hs200-1_8v;
349 mmc-hs400-1_8v;
350 cap-mmc-hw-reset;
351 no-sdio;
352 no-sd;
353 hs400-ds-delay = <0x14c11>;
354 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
355 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
356 non-removable;
357 };
358
359 &mmc1 {
360 pinctrl-names = "default", "state_uhs";
361 pinctrl-0 = <&mmc1_default_pins>;
362 pinctrl-1 = <&mmc1_uhs_pins>;
363 bus-width = <4>;
364 max-frequency = <200000000>;
365 cap-sd-highspeed;
366 sd-uhs-sdr50;
367 sd-uhs-sdr104;
368 no-mmc;
369 no-sdio;
370 vmmc-supply = <&mt6360_ldo5>;
371 vqmmc-supply = <&mt6360_ldo3>;
372 status = "okay";
373 non-removable;
374 };
375
376 &mt6359_vaud18_ldo_reg {
377 regulator-always-on;
378 };
379
380 &mt6359_vbbck_ldo_reg {
381 regulator-always-on;
382 };
383
384 /* For USB Hub */
385 &mt6359_vcamio_ldo_reg {
386 regulator-always-on;
387 };
388
389 &mt6359_vcn33_2_bt_ldo_reg {
390 regulator-min-microvolt = <3300000>;
391 regulator-max-microvolt = <3300000>;
392 };
393
394 &mt6359_vcore_buck_reg {
395 regulator-always-on;
396 };
397
398 &mt6359_vgpu11_buck_reg {
399 regulator-always-on;
400 };
401
402 &mt6359_vpu_buck_reg {
403 regulator-always-on;
404 };
405
406 &mt6359_vrf12_ldo_reg {
407 regulator-always-on;
408 };
409
410 &mt6359codec {
411 mediatek,mic-type-0 = <1>; /* ACC */
412 mediatek,mic-type-1 = <3>; /* DCC */
413 mediatek,mic-type-2 = <1>; /* ACC */
414 };
415
416 &pcie0 {
417 pinctrl-names = "default", "idle";
418 pinctrl-0 = <&pcie0_default_pins>;
419 pinctrl-1 = <&pcie0_idle_pins>;
420 status = "okay";
421 };
422
423 &pcie1 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pcie1_default_pins>;
426 status = "disabled";
427 };
428
429 &pciephy {
430 status = "okay";
431 };
432
433 &pio {
434 audio_default_pins: audio-default-pins {
435 pins-cmd-dat {
436 pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>,
437 <PINMUX_GPIO62__FUNC_DMIC1_DAT>,
438 <PINMUX_GPIO65__FUNC_PCM_DO>,
439 <PINMUX_GPIO66__FUNC_PCM_CLK>,
440 <PINMUX_GPIO67__FUNC_PCM_DI>,
441 <PINMUX_GPIO68__FUNC_PCM_SYNC>,
442 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
443 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
444 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
445 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
446 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
447 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
448 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>;
449 };
450 };
451
452 disp_pwm1_default_pins: disp-pwm1-default-pins {
453 pins1 {
454 pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>;
455 };
456 };
457
458 edp_panel_12v_en_pins: edp-panel-12v-en-pins {
459 pins1 {
460 pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
461 output-high;
462 };
463 };
464
465 edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {
466 pins1 {
467 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
468 output-high;
469 };
470 };
471
472 eth_default_pins: eth-default-pins {
473 pins-cc {
474 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
475 <PINMUX_GPIO86__FUNC_GBE_RXC>,
476 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
477 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
478 drive-strength = <8>;
479 };
480
481 pins-mdio {
482 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
483 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
484 input-enable;
485 };
486
487 pins-power {
488 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
489 <PINMUX_GPIO92__FUNC_GPIO92>;
490 output-high;
491 };
492
493 pins-rxd {
494 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
495 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
496 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
497 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
498 };
499
500 pins-txd {
501 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
502 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
503 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
504 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
505 drive-strength = <8>;
506 };
507 };
508
509 eth_sleep_pins: eth-sleep-pins {
510 pins-cc {
511 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
512 <PINMUX_GPIO86__FUNC_GPIO86>,
513 <PINMUX_GPIO87__FUNC_GPIO87>,
514 <PINMUX_GPIO88__FUNC_GPIO88>;
515 };
516
517 pins-mdio {
518 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
519 <PINMUX_GPIO90__FUNC_GPIO90>;
520 input-disable;
521 bias-disable;
522 };
523
524 pins-rxd {
525 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
526 <PINMUX_GPIO82__FUNC_GPIO82>,
527 <PINMUX_GPIO83__FUNC_GPIO83>,
528 <PINMUX_GPIO84__FUNC_GPIO84>;
529 };
530
531 pins-txd {
532 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
533 <PINMUX_GPIO78__FUNC_GPIO78>,
534 <PINMUX_GPIO79__FUNC_GPIO79>,
535 <PINMUX_GPIO80__FUNC_GPIO80>;
536 };
537 };
538
539 gpio_key_pins: gpio-keys-pins {
540 pins {
541 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
542 bias-pull-up;
543 input-enable;
544 };
545 };
546
547 i2c0_pins: i2c0-pins {
548 pins {
549 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
550 <PINMUX_GPIO9__FUNC_SCL0>;
551 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
552 drive-strength-microamp = <1000>;
553 };
554 };
555
556 i2c1_pins: i2c1-pins {
557 pins {
558 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
559 <PINMUX_GPIO11__FUNC_SCL1>;
560 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
561 drive-strength-microamp = <1000>;
562 };
563 };
564
565 i2c2_pins: i2c2-pins {
566 pins {
567 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
568 <PINMUX_GPIO13__FUNC_SCL2>;
569 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
570 drive-strength = <6>;
571 };
572 };
573
574 i2c6_pins: i2c6-pins {
575 pins {
576 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
577 <PINMUX_GPIO26__FUNC_SCL6>;
578 bias-pull-up;
579 };
580 };
581
582 mmc0_default_pins: mmc0-default-pins {
583 pins-clk {
584 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
585 drive-strength = <6>;
586 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
587 };
588
589 pins-cmd-dat {
590 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
591 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
592 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
593 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
594 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
595 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
596 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
597 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
598 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
599 input-enable;
600 drive-strength = <6>;
601 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
602 };
603
604 pins-rst {
605 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
606 drive-strength = <6>;
607 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
608 };
609 };
610
611 mmc0_uhs_pins: mmc0-uhs-pins {
612 pins-clk {
613 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
614 drive-strength = <8>;
615 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
616 };
617
618 pins-cmd-dat {
619 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
620 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
621 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
622 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
623 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
624 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
625 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
626 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
627 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
628 input-enable;
629 drive-strength = <8>;
630 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
631 };
632
633 pins-ds {
634 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
635 drive-strength = <8>;
636 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
637 };
638
639 pins-rst {
640 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
641 drive-strength = <8>;
642 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
643 };
644 };
645
646 mmc1_default_pins: mmc1-default-pins {
647 pins-clk {
648 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
649 drive-strength = <8>;
650 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
651 };
652
653 pins-cmd-dat {
654 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
655 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
656 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
657 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
658 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
659 input-enable;
660 drive-strength = <8>;
661 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
662 };
663 };
664
665 mmc1_uhs_pins: mmc1-uhs-pins {
666 pins-clk {
667 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
668 drive-strength = <8>;
669 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
670 };
671
672 pins-cmd-dat {
673 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
674 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
675 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
676 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
677 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
678 input-enable;
679 drive-strength = <8>;
680 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
681 };
682 };
683
684 mt6360_pins: mt6360-pins {
685 pins {
686 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>,
687 <PINMUX_GPIO128__FUNC_GPIO128>;
688 input-enable;
689 bias-pull-up;
690 };
691 };
692
693 pcie0_default_pins: pcie0-default-pins {
694 pins {
695 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
696 <PINMUX_GPIO20__FUNC_PERSTN>,
697 <PINMUX_GPIO21__FUNC_CLKREQN>;
698 bias-pull-up;
699 };
700 };
701
702 pcie0_idle_pins: pcie0-idle-pins {
703 pins {
704 pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
705 bias-disable;
706 output-low;
707 };
708 };
709
710 pcie1_default_pins: pcie1-default-pins {
711 pins {
712 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
713 <PINMUX_GPIO23__FUNC_CLKREQN_1>,
714 <PINMUX_GPIO24__FUNC_WAKEN_1>;
715 bias-pull-up;
716 };
717 };
718
719 pwm0_default_pins: pwm0-default-pins {
720 pins-cmd-dat {
721 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
722 };
723 };
724
725 spi1_pins: spi1-pins {
726 pins {
727 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
728 <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
729 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
730 <PINMUX_GPIO139__FUNC_SPIM1_MI>;
731 bias-disable;
732 };
733 };
734
735 spi2_pins: spi-pins {
736 pins {
737 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
738 <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
739 <PINMUX_GPIO142__FUNC_SPIM2_MO>,
740 <PINMUX_GPIO143__FUNC_SPIM2_MI>;
741 bias-disable;
742 };
743 };
744
745 touch_pins: touch-pins {
746 pins-irq {
747 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
748 input-enable;
749 bias-disable;
750 };
751
752 pins-reset {
753 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>;
754 output-high;
755 };
756 };
757
758 uart0_pins: uart0-pins {
759 pins {
760 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
761 <PINMUX_GPIO99__FUNC_URXD0>;
762 };
763 };
764
765 uart1_pins: uart1-pins {
766 pins {
767 pinmux = <PINMUX_GPIO100__FUNC_URTS1>,
768 <PINMUX_GPIO101__FUNC_UCTS1>,
769 <PINMUX_GPIO102__FUNC_UTXD1>,
770 <PINMUX_GPIO103__FUNC_URXD1>;
771 };
772 };
773 };
774
775 &pmic {
776 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
777 };
778
779 &scp {
780 memory-region = <&scp_mem>;
781 status = "okay";
782 };
783
784 &spi1 {
785 pinctrl-0 = <&spi1_pins>;
786 pinctrl-names = "default";
787 mediatek,pad-select = <0>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 status = "okay";
791 cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>;
792
793 can0: can@0 {
794 compatible = "microchip,mcp2518fd";
795 reg = <0>;
796 clocks = <&can_clk>;
797 spi-max-frequency = <20000000>;
798 interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>;
799 vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
800 xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
801 };
802 };
803
804 &spi2 {
805 pinctrl-0 = <&spi2_pins>;
806 pinctrl-names = "default";
807 mediatek,pad-select = <0>;
808 #address-cells = <1>;
809 #size-cells = <0>;
810 status = "okay";
811 };
812
813 &spmi {
814 #address-cells = <2>;
815 #size-cells = <0>;
816
817 mt6315_6: pmic@6 {
818 compatible = "mediatek,mt6315-regulator";
819 reg = <0x6 SPMI_USID>;
820
821 regulators {
822 mt6315_6_vbuck1: vbuck1 {
823 regulator-compatible = "vbuck1";
824 regulator-name = "Vbcpu";
825 regulator-min-microvolt = <300000>;
826 regulator-max-microvolt = <1193750>;
827 regulator-enable-ramp-delay = <256>;
828 regulator-allowed-modes = <0 1 2>;
829 regulator-always-on;
830 };
831 };
832 };
833
834 mt6315_7: pmic@7 {
835 compatible = "mediatek,mt6315-regulator";
836 reg = <0x7 SPMI_USID>;
837
838 regulators {
839 mt6315_7_vbuck1: vbuck1 {
840 regulator-compatible = "vbuck1";
841 regulator-name = "Vgpu";
842 regulator-min-microvolt = <300000>;
843 regulator-max-microvolt = <1193750>;
844 regulator-enable-ramp-delay = <256>;
845 regulator-allowed-modes = <0 1 2>;
846 };
847 };
848 };
849 };
850
851 &u3phy0 {
852 status = "okay";
853 };
854
855 &u3phy1 {
856 status = "okay";
857
858 u3port1: usb-phy@700 {
859 mediatek,force-mode;
860 };
861 };
862
863 &u3phy2 {
864 status = "okay";
865 };
866
867 &u3phy3 {
868 status = "okay";
869 };
870
871 &uart0 {
872 pinctrl-0 = <&uart0_pins>;
873 pinctrl-names = "default";
874 status = "okay";
875 };
876
877 &uart1 {
878 pinctrl-0 = <&uart1_pins>;
879 pinctrl-names = "default";
880 status = "okay";
881 };
882
883 &ufsphy {
884 status = "disabled";
885 };
886
887 &ssusb0 {
888 vusb33-supply = <&mt6359_vusb_ldo_reg>;
889 status = "okay";
890 };
891
892 &ssusb2 {
893 vusb33-supply = <&mt6359_vusb_ldo_reg>;
894 status = "okay";
895 };
896
897 &ssusb3 {
898 vusb33-supply = <&mt6359_vusb_ldo_reg>;
899 status = "okay";
900 };
901
902 &xhci0 {
903 status = "okay";
904 };
905
906 &xhci1 {
907 phys = <&u2port1 PHY_TYPE_USB2>,
908 <&u3port1 PHY_TYPE_USB3>;
909 vusb33-supply = <&mt6359_vusb_ldo_reg>;
910 status = "okay";
911 };
912
913 &xhci2 {
914 status = "okay";
915 };
916
917 &xhci3 {
918 status = "okay";
919 };
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