1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2024 Kontron Europe GmbH
4 *
5 * Author: Michael Walle <mwalle@kernel.org>
6 */
7 /dts-v1/;
8
9 #include "mt8195.dtsi"
10 #include "mt6359.dtsi"
11
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
16 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
17 #include <dt-bindings/spmi/spmi.h>
18
19 / {
20 model = "Kontron 3.5\"-SBC-i1200";
21 compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195";
22
23 aliases {
24 mmc0 = &mmc0;
25 mmc1 = &mmc1;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart0;
31 };
32
33 chosen {
34 stdout-path = "serial0:115200n8";
35 };
36
37 firmware {
38 optee {
39 compatible = "linaro,optee-tz";
40 method = "smc";
41 };
42 };
43
44 gpio-keys {
45 compatible = "gpio-keys";
46 pinctrl-names = "default";
47 pinctrl-0 = <&gpio_keys_pins>;
48
49 key-0 {
50 gpios = <&pio 106 GPIO_ACTIVE_LOW>;
51 label = "volume_up";
52 linux,code = <KEY_VOLUMEUP>;
53 wakeup-source;
54 debounce-interval = <15>;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 pinctrl-names = "default";
61 pinctrl-0 = <&led_pins>;
62
63 led-0 {
64 gpios = <&pio 107 GPIO_ACTIVE_HIGH>;
65 default-state = "keep";
66 function = LED_FUNCTION_POWER;
67 color = <LED_COLOR_ID_GREEN>;
68 };
69 };
70
71 memory@40000000 {
72 device_type = "memory";
73 reg = <0 0x40000000 0x0 0x80000000>;
74 };
75
76 vsys: regulator-vsys {
77 compatible = "regulator-fixed";
78 regulator-name = "vsys";
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <5000000>;
82 regulator-max-microvolt = <5000000>;
83 };
84
85 reserved-memory {
86 #address-cells = <2>;
87 #size-cells = <2>;
88 ranges;
89
90 /*
91 * 12 MiB reserved for OP-TEE (BL32)
92 * +-----------------------+ 0x43e0_0000
93 * | SHMEM 2MiB |
94 * +-----------------------+ 0x43c0_0000
95 * | | TA_RAM 8MiB |
96 * + TZDRAM +--------------+ 0x4340_0000
97 * | | TEE_RAM 2MiB |
98 * +-----------------------+ 0x4320_0000
99 */
100 optee_reserved: optee@43200000 {
101 no-map;
102 reg = <0 0x43200000 0 0x00c00000>;
103 };
104
105 scp_mem: memory@50000000 {
106 compatible = "shared-dma-pool";
107 reg = <0 0x50000000 0 0x2900000>;
108 no-map;
109 };
110
111 vpu_mem: memory@53000000 {
112 compatible = "shared-dma-pool";
113 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
114 };
115
116 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
117 bl31_secmon_mem: memory@54600000 {
118 no-map;
119 reg = <0 0x54600000 0x0 0x200000>;
120 };
121
122 snd_dma_mem: memory@60000000 {
123 compatible = "shared-dma-pool";
124 reg = <0 0x60000000 0 0x1100000>;
125 no-map;
126 };
127
128 apu_mem: memory@62000000 {
129 compatible = "shared-dma-pool";
130 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
131 };
132 };
133
134 thermal_sensor0: thermal-sensor-0 {
135 compatible = "generic-adc-thermal";
136 #thermal-sensor-cells = <0>;
137 io-channels = <&auxadc 0>;
138 io-channel-names = "sensor-channel";
139 temperature-lookup-table = <(-25000) 1474
140 (-20000) 1374
141 (-15000) 1260
142 (-10000) 1134
143 (-5000) 1004
144 0 874
145 5000 750
146 10000 635
147 15000 532
148 20000 443
149 25000 367
150 30000 303
151 35000 250
152 40000 206
153 45000 170
154 50000 141
155 55000 117
156 60000 97
157 65000 81
158 70000 68
159 75000 57
160 80000 48
161 85000 41
162 90000 35
163 95000 30
164 100000 25
165 105000 22
166 110000 19
167 115000 16
168 120000 14
169 125000 12
170 130000 10
171 135000 9
172 140000 8
173 145000 7
174 150000 6>;
175 };
176
177 thermal_sensor1: thermal-sensor-1 {
178 compatible = "generic-adc-thermal";
179 #thermal-sensor-cells = <0>;
180 io-channels = <&auxadc 1>;
181 io-channel-names = "sensor-channel";
182 temperature-lookup-table = <(-25000) 1474
183 (-20000) 1374
184 (-15000) 1260
185 (-10000) 1134
186 (-5000) 1004
187 0 874
188 5000 750
189 10000 635
190 15000 532
191 20000 443
192 25000 367
193 30000 303
194 35000 250
195 40000 206
196 45000 170
197 50000 141
198 55000 117
199 60000 97
200 65000 81
201 70000 68
202 75000 57
203 80000 48
204 85000 41
205 90000 35
206 95000 30
207 100000 25
208 105000 22
209 110000 19
210 115000 16
211 120000 14
212 125000 12
213 130000 10
214 135000 9
215 140000 8
216 145000 7
217 150000 6>;
218 };
219
220 thermal_sensor2: thermal-sensor-2 {
221 compatible = "generic-adc-thermal";
222 #thermal-sensor-cells = <0>;
223 io-channels = <&auxadc 2>;
224 io-channel-names = "sensor-channel";
225 temperature-lookup-table = <(-25000) 1474
226 (-20000) 1374
227 (-15000) 1260
228 (-10000) 1134
229 (-5000) 1004
230 0 874
231 5000 750
232 10000 635
233 15000 532
234 20000 443
235 25000 367
236 30000 303
237 35000 250
238 40000 206
239 45000 170
240 50000 141
241 55000 117
242 60000 97
243 65000 81
244 70000 68
245 75000 57
246 80000 48
247 85000 41
248 90000 35
249 95000 30
250 100000 25
251 105000 22
252 110000 19
253 115000 16
254 120000 14
255 125000 12
256 130000 10
257 135000 9
258 140000 8
259 145000 7
260 150000 6>;
261 };
262 };
263
264 &auxadc {
265 status = "okay";
266 };
267
268 ð {
269 phy-mode ="rgmii-id";
270 phy-handle = <ðernet_phy0>;
271 pinctrl-names = "default", "sleep";
272 pinctrl-0 = <ð_default_pins>;
273 pinctrl-1 = <ð_sleep_pins>;
274 status = "okay";
275
276 mdio {
277 ethernet_phy0: ethernet-phy@1 {
278 compatible = "ethernet-phy-id001c.c916";
279 reg = <0x1>;
280 interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>;
281 reset-assert-us = <10000>;
282 reset-deassert-us = <80000>;
283 reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>;
284 };
285 };
286 };
287
288 &gpu {
289 status = "okay";
290 mali-supply = <&mt6315_7_vbuck1>;
291 };
292
293 /* CSI1/CSI2 connector */
294 &i2c0 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&i2c0_pins>;
297 clock-frequency = <100000>;
298 status = "okay";
299 };
300
301 /* CSI3 connector */
302 &i2c1 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&i2c1_pins>;
305 clock-frequency = <100000>;
306 status = "okay";
307 };
308
309 &i2c2 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c2_pins>;
312 clock-frequency = <400000>;
313 status = "okay";
314
315 /* LVDS bridge @f */
316 };
317
318 /* Touch panel connector */
319 &i2c3 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c3_pins>;
322 clock-frequency = <100000>;
323 status = "okay";
324 };
325
326 /* B2B connector */
327 &i2c4 {
328 clock-frequency = <100000>;
329 pinctrl-0 = <&i2c4_pins>;
330 pinctrl-names = "default";
331 status = "okay";
332 };
333
334 &i2c6 {
335 clock-frequency = <400000>;
336 pinctrl-0 = <&i2c6_pins>;
337 pinctrl-names = "default";
338 status = "okay";
339
340 mt6360: pmic@34 {
341 compatible = "mediatek,mt6360";
342 reg = <0x34>;
343 interrupt-controller;
344 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
345 interrupt-names = "IRQB";
346 #interrupt-cells = <1>;
347
348 regulator {
349 compatible = "mediatek,mt6360-regulator";
350 LDO_VIN1-supply = <&vsys>;
351 LDO_VIN2-supply = <&vsys>;
352 LDO_VIN3-supply = <&vsys>;
353
354 mt6360_buck1: BUCK1 {
355 regulator-name = "emi_vdd2";
356 regulator-min-microvolt = <600000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
359 MT6360_OPMODE_LP
360 MT6360_OPMODE_ULP>;
361 regulator-always-on;
362 };
363
364 mt6360_buck2: BUCK2 {
365 regulator-name = "emi_vddq";
366 regulator-min-microvolt = <300000>;
367 regulator-max-microvolt = <1300000>;
368 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
369 MT6360_OPMODE_LP
370 MT6360_OPMODE_ULP>;
371 regulator-always-on;
372 };
373
374 mt6360_ldo1: LDO1 {
375 regulator-name = "mt6360_ldo1"; /* Test point */
376 regulator-min-microvolt = <1200000>;
377 regulator-max-microvolt = <3600000>;
378 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
379 MT6360_OPMODE_LP>;
380 };
381
382 mt6360_ldo2: LDO2 {
383 regulator-name = "panel1_p1v8";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
387 MT6360_OPMODE_LP>;
388 };
389
390 mt6360_ldo3: LDO3 {
391 regulator-name = "vmc_pmu";
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <3300000>;
394 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
395 MT6360_OPMODE_LP>;
396 };
397
398 mt6360_ldo5: LDO5 {
399 regulator-name = "vmch_pmu";
400 regulator-min-microvolt = <3300000>;
401 regulator-max-microvolt = <3300000>;
402 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
403 MT6360_OPMODE_LP>;
404 };
405
406 mt6360_ldo6: LDO6 {
407 regulator-name = "mt6360_ldo6"; /* Test point */
408 regulator-min-microvolt = <500000>;
409 regulator-max-microvolt = <2100000>;
410 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
411 MT6360_OPMODE_LP>;
412 };
413
414 mt6360_ldo7: LDO7 {
415 regulator-name = "emi_vmddr_en";
416 regulator-min-microvolt = <1800000>;
417 regulator-max-microvolt = <1800000>;
418 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
419 MT6360_OPMODE_LP>;
420 regulator-always-on;
421 };
422 };
423 };
424 };
425
426 &mmc0 {
427 pinctrl-names = "default", "state_uhs";
428 pinctrl-0 = <&mmc0_default_pins>;
429 pinctrl-1 = <&mmc0_uhs_pins>;
430 bus-width = <8>;
431 max-frequency = <200000000>;
432 hs400-ds-delay = <0x14c11>;
433 cap-mmc-highspeed;
434 cap-mmc-hw-reset;
435 mmc-hs200-1_8v;
436 mmc-hs400-1_8v;
437 no-sdio;
438 no-sd;
439 non-removable;
440 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
441 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
442 status = "okay";
443 };
444
445 &mmc1 {
446 pinctrl-names = "default", "state_uhs";
447 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>;
448 pinctrl-1 = <&mmc1_default_pins>;
449 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
450 bus-width = <4>;
451 max-frequency = <200000000>;
452 cap-sd-highspeed;
453 sd-uhs-sdr50;
454 sd-uhs-sdr104;
455 no-mmc;
456 vmmc-supply = <&mt6360_ldo5>;
457 vqmmc-supply = <&mt6360_ldo3>;
458 status = "okay";
459 };
460
461 &mt6359_vbbck_ldo_reg {
462 regulator-always-on;
463 };
464
465 &mt6359_vcore_buck_reg {
466 regulator-always-on;
467 };
468
469 &mt6359_vgpu11_buck_reg {
470 regulator-always-on;
471 };
472
473 &mt6359_vproc1_buck_reg {
474 regulator-always-on;
475 };
476
477 &mt6359_vproc2_buck_reg {
478 regulator-always-on;
479 };
480
481 &mt6359_vpu_buck_reg {
482 regulator-always-on;
483 };
484
485 &mt6359_vrf12_ldo_reg {
486 regulator-always-on;
487 };
488
489 &mt6359_vsram_md_ldo_reg {
490 regulator-always-on;
491 };
492
493 &mt6359_vsram_others_ldo_reg {
494 regulator-always-on;
495 };
496
497 &nor_flash {
498 pinctrl-names = "default";
499 pinctrl-0 = <&nor_pins_default>;
500 status = "okay";
501
502 flash@0 {
503 compatible = "jedec,spi-nor";
504 reg = <0>;
505 spi-max-frequency = <52000000>;
506 spi-rx-bus-width = <2>;
507 spi-tx-bus-width = <2>;
508 };
509 };
510
511 &pcie0 {
512 pinctrl-names = "default";
513 pinctrl-0 = <&pcie0_pins_default>;
514 status = "okay";
515 };
516
517 &pcie1 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&pcie1_pins_default>;
520 status = "okay";
521 };
522
523 &pciephy {
524 status = "okay";
525 };
526
527 &pio {
528 eth_default_pins: eth-default-pins {
529 pins-txd {
530 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
531 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
532 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
533 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
534 drive-strength = <8>;
535 };
536
537 pins-rxd {
538 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
539 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
540 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
541 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
542 };
543
544 pins-cc {
545 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
546 <PINMUX_GPIO86__FUNC_GBE_RXC>,
547 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
548 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
549 drive-strength = <8>;
550 };
551
552 pins-mdio {
553 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
554 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
555 input-enable;
556 };
557
558 pins-power {
559 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
560 <PINMUX_GPIO92__FUNC_GPIO92>;
561 output-high;
562 };
563
564 pins-reset {
565 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
566 output-high;
567 };
568
569 pins-interrupt {
570 pinmux = <PINMUX_GPIO94__FUNC_GPIO94>;
571 input-enable;
572 };
573 };
574
575 eth_sleep_pins: eth-sleep-pins {
576 pins-txd {
577 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
578 <PINMUX_GPIO78__FUNC_GPIO78>,
579 <PINMUX_GPIO79__FUNC_GPIO79>,
580 <PINMUX_GPIO80__FUNC_GPIO80>;
581 };
582
583 pins-cc {
584 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
585 <PINMUX_GPIO88__FUNC_GPIO88>,
586 <PINMUX_GPIO87__FUNC_GPIO87>,
587 <PINMUX_GPIO86__FUNC_GPIO86>;
588 };
589
590 pins-rxd {
591 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
592 <PINMUX_GPIO82__FUNC_GPIO82>,
593 <PINMUX_GPIO83__FUNC_GPIO83>,
594 <PINMUX_GPIO84__FUNC_GPIO84>;
595 };
596
597 pins-mdio {
598 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
599 <PINMUX_GPIO90__FUNC_GPIO90>;
600 input-disable;
601 bias-disable;
602 };
603 };
604
605 gpio_keys_pins: gpio-keys-pins {
606 pins {
607 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
608 input-enable;
609 };
610 };
611
612 i2c0_pins: i2c0-pins {
613 pins {
614 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
615 <PINMUX_GPIO9__FUNC_SCL0>;
616 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
617 drive-strength-microamp = <1000>;
618 };
619 };
620
621 i2c1_pins: i2c1-pins {
622 pins {
623 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
624 <PINMUX_GPIO11__FUNC_SCL1>;
625 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
626 drive-strength-microamp = <1000>;
627 };
628 };
629
630 i2c2_pins: i2c2-default-pins {
631 pins-bus {
632 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
633 <PINMUX_GPIO13__FUNC_SCL2>;
634 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
635 drive-strength-microamp = <1000>;
636 };
637 };
638
639 i2c3_pins: i2c3-pins {
640 pins {
641 pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
642 <PINMUX_GPIO15__FUNC_SCL3>;
643 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
644 drive-strength-microamp = <1000>;
645 };
646 };
647
648 i2c4_pins: i2c4-pins {
649 pins {
650 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
651 <PINMUX_GPIO17__FUNC_SCL4>;
652 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
653 drive-strength-microamp = <1000>;
654 };
655 };
656
657 i2c6_pins: i2c6-pins {
658 pins {
659 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
660 <PINMUX_GPIO26__FUNC_SCL6>;
661 bias-pull-up;
662 drive-strength-microamp = <1000>;
663 };
664 };
665
666 mmc0_default_pins: mmc0-default-pins {
667 pins-clk {
668 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
669 drive-strength = <6>;
670 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
671 };
672
673 pins-cmd-dat {
674 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
675 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
676 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
677 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
678 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
679 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
680 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
681 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
682 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
683 input-enable;
684 drive-strength = <6>;
685 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
686 };
687
688 pins-rst {
689 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
690 drive-strength = <6>;
691 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
692 };
693 };
694
695 mmc0_uhs_pins: mmc0-uhs-pins {
696 pins-clk {
697 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
698 drive-strength = <8>;
699 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
700 };
701
702 pins-cmd-dat {
703 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
704 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
705 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
706 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
707 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
708 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
709 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
710 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
711 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
712 input-enable;
713 drive-strength = <8>;
714 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
715 };
716
717 pins-ds {
718 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
719 drive-strength = <8>;
720 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
721 };
722
723 pins-rst {
724 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
725 drive-strength = <8>;
726 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
727 };
728 };
729
730 mmc1_default_pins: mmc1-default-pins {
731 pins-clk {
732 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
733 drive-strength = <8>;
734 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
735 };
736
737 pins-cmd-dat {
738 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
739 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
740 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
741 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
742 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
743 input-enable;
744 drive-strength = <8>;
745 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
746 };
747 };
748
749 mmc1_detect_pins: mmc1-detect-pins {
750 pins-insert {
751 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
752 bias-pull-up;
753 };
754 };
755
756 nor_pins_default: nor-default-pins {
757 pins-ck-io {
758 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
759 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
760 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
761 drive-strength = <6>;
762 bias-pull-down;
763 };
764
765 pins-cs {
766 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
767 drive-strength = <6>;
768 bias-pull-up;
769 };
770 };
771
772 pcie0_pins_default: pcie0-default-pins {
773 pins-bus {
774 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
775 <PINMUX_GPIO20__FUNC_PERSTN>,
776 <PINMUX_GPIO21__FUNC_CLKREQN>;
777 bias-pull-up;
778 };
779 };
780
781 pcie1_pins_default: pcie1-default-pins {
782 pins-bus {
783 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
784 <PINMUX_GPIO1__FUNC_CLKREQN_1>,
785 <PINMUX_GPIO2__FUNC_WAKEN_1>;
786 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
787 };
788 };
789
790 led_pins: led-pins {
791 pins-power-en {
792 pinmux = <PINMUX_GPIO107__FUNC_GPIO107>;
793 output-high;
794 };
795 };
796
797 spi0_pins: spi0-default-pins {
798 pins-cs-mosi-clk {
799 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
800 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
801 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
802 bias-disable;
803 };
804
805 pins-miso {
806 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
807 bias-pull-down;
808 };
809 };
810
811 spi1_pins: spi1-default-pins {
812 pins-cs-mosi-clk {
813 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
814 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
815 <PINMUX_GPIO137__FUNC_SPIM1_CLK>;
816 bias-disable;
817 };
818
819 pins-miso {
820 pinmux = <PINMUX_GPIO139__FUNC_SPIM1_MI>;
821 bias-pull-down;
822 };
823 };
824
825 uart0_pins: uart0-pins {
826 pins-rx {
827 pinmux = <PINMUX_GPIO99__FUNC_URXD0>;
828 input-enable;
829 bias-pull-up;
830 };
831
832 pins-tx {
833 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>;
834 };
835 };
836
837 uart1_pins: uart1-pins {
838 pins-rx {
839 pinmux = <PINMUX_GPIO103__FUNC_URXD1>;
840 input-enable;
841 bias-pull-up;
842 };
843
844 pins-tx {
845 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>;
846 };
847
848 pins-rts {
849 pinmux = <PINMUX_GPIO100__FUNC_URTS1>;
850 };
851
852 pins-cts {
853 pinmux = <PINMUX_GPIO101__FUNC_UCTS1>;
854 input-enable;
855 };
856 };
857
858 uart2_pins: uart2-pins {
859 pins-rx {
860 pinmux = <PINMUX_GPIO68__FUNC_URXD2>;
861 input-enable;
862 bias-pull-up;
863 };
864
865 pins-tx {
866 pinmux = <PINMUX_GPIO67__FUNC_UTXD2>;
867 };
868
869 pins-rts {
870 pinmux = <PINMUX_GPIO66__FUNC_URTS2>;
871 };
872
873 pins-cts {
874 pinmux = <PINMUX_GPIO65__FUNC_UCTS2>;
875 input-enable;
876 };
877 };
878
879 uart3_pins: uart3-pins {
880 pins-rx {
881 pinmux = <PINMUX_GPIO5__FUNC_URXD3>;
882 input-enable;
883 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
884 };
885
886 pins-tx {
887 pinmux = <PINMUX_GPIO4__FUNC_UTXD3>;
888 };
889 };
890
891 uart4_pins: uart4-pins {
892 pins-rx {
893 pinmux = <PINMUX_GPIO7__FUNC_URXD4>;
894 input-enable;
895 bias-pull-up;
896 };
897
898 pins-tx {
899 pinmux = <PINMUX_GPIO6__FUNC_UTXD4>;
900 };
901 };
902 };
903
904 &pmic {
905 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
906 };
907
908 &scp {
909 memory-region = <&scp_mem>;
910 firmware-name = "mediatek/mt8195/scp.img";
911 status = "okay";
912 };
913
914 &spmi {
915 #address-cells = <2>;
916 #size-cells = <0>;
917
918 mt6315@6 {
919 compatible = "mediatek,mt6315-regulator";
920 reg = <0x6 SPMI_USID>;
921
922 regulators {
923 mt6315_6_vbuck1: vbuck1 {
924 regulator-name = "Vbcpu";
925 regulator-min-microvolt = <300000>;
926 regulator-max-microvolt = <1193750>;
927 regulator-enable-ramp-delay = <256>;
928 regulator-ramp-delay = <6250>;
929 regulator-allowed-modes = <0 1 2>;
930 regulator-always-on;
931 };
932 };
933 };
934
935 mt6315@7 {
936 compatible = "mediatek,mt6315-regulator";
937 reg = <0x7 SPMI_USID>;
938
939 regulators {
940 mt6315_7_vbuck1: vbuck1 {
941 regulator-name = "Vgpu";
942 regulator-min-microvolt = <625000>;
943 regulator-max-microvolt = <1193750>;
944 regulator-enable-ramp-delay = <256>;
945 regulator-ramp-delay = <6250>;
946 regulator-allowed-modes = <0 1 2>;
947 regulator-always-on;
948 };
949 };
950 };
951 };
952
953 /* USB3.2 front port */
954 &ssusb0 {
955 dr_mode = "host";
956 vusb33-supply = <&mt6359_vusb_ldo_reg>;
957 status = "okay";
958 };
959
960 /* USB2.0 M.2 Key-E */
961 &ssusb2 {
962 vusb33-supply = <&mt6359_vusb_ldo_reg>;
963 status = "okay";
964 };
965
966 /* USB2.0 to on-board usb hub */
967 &ssusb3 {
968 vusb33-supply = <&mt6359_vusb_ldo_reg>;
969 status = "okay";
970 };
971
972 &spi0 {
973 pinctrl-names = "default";
974 pinctrl-0 = <&spi0_pins>;
975 mediatek,pad-select = <0>;
976 status = "okay";
977
978 tpm: tpm@0 {
979 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
980 reg = <0>;
981 spi-max-frequency = <18500000>;
982 };
983 };
984
985 /* B2B connector */
986 &spi1 {
987 pinctrl-names = "default";
988 pinctrl-0 = <&spi1_pins>;
989 mediatek,pad-select = <0>;
990 status = "okay";
991 };
992
993 &thermal_zones {
994 cpu-thermal {
995 polling-delay = <1000>; /* milliseconds */
996 polling-delay-passive = <0>; /* milliseconds */
997 thermal-sensors = <&thermal_sensor0>;
998
999 trips {
1000 trip-alert {
1001 temperature = <85000>;
1002 hysteresis = <2000>;
1003 type = "passive";
1004 };
1005
1006 trip-crit {
1007 temperature = <95000>;
1008 hysteresis = <2000>;
1009 type = "critical";
1010 };
1011 };
1012 };
1013
1014 pcb-top-thermal {
1015 polling-delay = <1000>; /* milliseconds */
1016 polling-delay-passive = <0>; /* milliseconds */
1017 thermal-sensors = <&thermal_sensor1>;
1018
1019 trips {
1020 trip-alert {
1021 temperature = <75000>;
1022 hysteresis = <2000>;
1023 type = "passive";
1024 };
1025
1026 trip-crit {
1027 temperature = <85000>;
1028 hysteresis = <2000>;
1029 type = "critical";
1030 };
1031 };
1032 };
1033
1034 pcb-bottom-thermal {
1035 polling-delay = <1000>; /* milliseconds */
1036 polling-delay-passive = <0>; /* milliseconds */
1037 thermal-sensors = <&thermal_sensor2>;
1038
1039 trips {
1040 trip-alert {
1041 temperature = <75000>;
1042 hysteresis = <2000>;
1043 type = "passive";
1044 };
1045
1046 trip-crit {
1047 temperature = <85000>;
1048 hysteresis = <2000>;
1049 type = "critical";
1050 };
1051 };
1052 };
1053 };
1054
1055 &uart0 {
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&uart0_pins>;
1058 status = "okay";
1059 };
1060
1061 &uart1 {
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&uart1_pins>;
1064 uart-has-rtscts;
1065 status = "okay";
1066 };
1067
1068 &uart2 {
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&uart2_pins>;
1071 uart-has-rtscts;
1072 status = "okay";
1073 };
1074
1075 &uart3 {
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&uart3_pins>;
1078 status = "okay";
1079 };
1080
1081 &uart4 {
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&uart4_pins>;
1084 status = "okay";
1085 };
1086
1087 /* USB3 */
1088 &u3phy0 {
1089 status = "okay";
1090 };
1091
1092 /* PCIe1/USB2 */
1093 &u3phy1 {
1094 status = "okay";
1095 };
1096
1097 /* USB2 */
1098 &u3phy2 {
1099 status = "okay";
1100 };
1101
1102 /* USB2 */
1103 &u3phy3 {
1104 status = "okay";
1105 };
1106
1107 /* USB3.2 front port */
1108 &xhci0 {
1109 status = "okay";
1110 };
1111
1112 /* USB2.0 M.2 Key-B */
1113 &xhci1 {
1114 phys = <&u2port1 PHY_TYPE_USB2>;
1115 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1116 mediatek,u3p-dis-msk = <0x01>;
1117 status = "okay";
1118 };
1119
1120 /* USB2.0 M.2 Key-E */
1121 &xhci2 {
1122 status = "okay";
1123 };
1124
1125 /* USB2.0 to on-board usb hub */
1126 &xhci3 {
1127 status = "okay";
1128 };
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