1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Copyright (c) 2019 BayLibre, SAS.
5 * Author: Fabien Parent <fparent@baylibre.com>
6 */
7
8 #include <dt-bindings/clock/mt8516-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/phy/phy.h>
12
13 #include "mt8516-pinfunc.h"
14
15 / {
16 compatible = "mediatek,mt8516";
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cluster0_opp: opp-table-0 {
22 compatible = "operating-points-v2";
23 opp-shared;
24 opp-598000000 {
25 opp-hz = /bits/ 64 <598000000>;
26 opp-microvolt = <1150000>;
27 };
28 opp-747500000 {
29 opp-hz = /bits/ 64 <747500000>;
30 opp-microvolt = <1150000>;
31 };
32 opp-1040000000 {
33 opp-hz = /bits/ 64 <1040000000>;
34 opp-microvolt = <1200000>;
35 };
36 opp-1196000000 {
37 opp-hz = /bits/ 64 <1196000000>;
38 opp-microvolt = <1250000>;
39 };
40 opp-1300000000 {
41 opp-hz = /bits/ 64 <1300000000>;
42 opp-microvolt = <1300000>;
43 };
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a35";
53 reg = <0x0>;
54 enable-method = "psci";
55 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
56 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
58 <&topckgen CLK_TOP_MAINPLL_D2>;
59 clock-names = "cpu", "intermediate";
60 operating-points-v2 = <&cluster0_opp>;
61 };
62
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a35";
66 reg = <0x1>;
67 enable-method = "psci";
68 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
69 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
71 <&topckgen CLK_TOP_MAINPLL_D2>;
72 clock-names = "cpu", "intermediate";
73 operating-points-v2 = <&cluster0_opp>;
74 };
75
76 cpu2: cpu@2 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a35";
79 reg = <0x2>;
80 enable-method = "psci";
81 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
82 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
84 <&topckgen CLK_TOP_MAINPLL_D2>;
85 clock-names = "cpu", "intermediate";
86 operating-points-v2 = <&cluster0_opp>;
87 };
88
89 cpu3: cpu@3 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a35";
92 reg = <0x3>;
93 enable-method = "psci";
94 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
95 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
97 <&topckgen CLK_TOP_MAINPLL_D2>;
98 clock-names = "cpu", "intermediate", "armpll";
99 operating-points-v2 = <&cluster0_opp>;
100 };
101
102 idle-states {
103 entry-method = "psci";
104
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
106 compatible = "arm,idle-state";
107 entry-latency-us = <600>;
108 exit-latency-us = <600>;
109 min-residency-us = <1200>;
110 arm,psci-suspend-param = <0x0010000>;
111 };
112
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
114 compatible = "arm,idle-state";
115 entry-latency-us = <800>;
116 exit-latency-us = <1000>;
117 min-residency-us = <2000>;
118 arm,psci-suspend-param = <0x2010000>;
119 };
120 };
121 };
122
123 psci {
124 compatible = "arm,psci-1.0";
125 method = "smc";
126 };
127
128 clk26m: clk26m {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <26000000>;
132 clock-output-names = "clk26m";
133 };
134
135 clk32k: clk32k {
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <32000>;
139 clock-output-names = "clk32k";
140 };
141
142 reserved-memory {
143 #address-cells = <2>;
144 #size-cells = <2>;
145 ranges;
146
147 /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
148 bl31_secmon_reserved: secmon@43000000 {
149 no-map;
150 reg = <0 0x43000000 0 0x20000>;
151 };
152 };
153
154 timer {
155 compatible = "arm,armv8-timer";
156 interrupt-parent = <&gic>;
157 interrupts = <GIC_PPI 13
158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
159 <GIC_PPI 14
160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161 <GIC_PPI 11
162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163 <GIC_PPI 10
164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
165 };
166
167 pmu {
168 compatible = "arm,cortex-a35-pmu";
169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
174 };
175
176 soc {
177 #address-cells = <2>;
178 #size-cells = <2>;
179 compatible = "simple-bus";
180 ranges;
181
182 topckgen: topckgen@10000000 {
183 compatible = "mediatek,mt8516-topckgen", "syscon";
184 reg = <0 0x10000000 0 0x1000>;
185 #clock-cells = <1>;
186 };
187
188 infracfg: infracfg@10001000 {
189 compatible = "mediatek,mt8516-infracfg", "syscon";
190 reg = <0 0x10001000 0 0x1000>;
191 #clock-cells = <1>;
192 };
193
194 pericfg: pericfg@10003050 {
195 compatible = "mediatek,mt8516-pericfg", "syscon";
196 reg = <0 0x10003050 0 0x1000>;
197 };
198
199 apmixedsys: apmixedsys@10018000 {
200 compatible = "mediatek,mt8516-apmixedsys", "syscon";
201 reg = <0 0x10018000 0 0x710>;
202 #clock-cells = <1>;
203 };
204
205 watchdog@10007000 {
206 compatible = "mediatek,mt8516-wdt",
207 "mediatek,mt6589-wdt";
208 reg = <0 0x10007000 0 0x1000>;
209 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
210 #reset-cells = <1>;
211 };
212
213 timer: timer@10008000 {
214 compatible = "mediatek,mt8516-timer",
215 "mediatek,mt6577-timer";
216 reg = <0 0x10008000 0 0x1000>;
217 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
220 clock-names = "clk13m", "bus";
221 };
222
223 syscfg_pctl: syscfg-pctl@10005000 {
224 compatible = "syscon";
225 reg = <0 0x10005000 0 0x1000>;
226 };
227
228 pio: pinctrl@1000b000 {
229 compatible = "mediatek,mt8516-pinctrl";
230 reg = <0 0x1000b000 0 0x1000>;
231 mediatek,pctl-regmap = <&syscfg_pctl>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
237 };
238
239 efuse: efuse@10009000 {
240 compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
241 reg = <0 0x10009000 0 0x1000>;
242 #address-cells = <1>;
243 #size-cells = <1>;
244 };
245
246 pwrap: pwrap@1000f000 {
247 compatible = "mediatek,mt8516-pwrap";
248 reg = <0 0x1000f000 0 0x1000>;
249 reg-names = "pwrap";
250 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
253 clock-names = "spi", "wrap";
254 };
255
256 sysirq: interrupt-controller@10200620 {
257 compatible = "mediatek,mt8516-sysirq",
258 "mediatek,mt6577-sysirq";
259 interrupt-controller;
260 #interrupt-cells = <3>;
261 interrupt-parent = <&gic>;
262 reg = <0 0x10200620 0 0x20>;
263 };
264
265 gic: interrupt-controller@10310000 {
266 compatible = "arm,gic-400";
267 #interrupt-cells = <3>;
268 interrupt-parent = <&gic>;
269 interrupt-controller;
270 reg = <0 0x10310000 0 0x1000>,
271 <0 0x10320000 0 0x1000>,
272 <0 0x10340000 0 0x2000>,
273 <0 0x10360000 0 0x2000>;
274 interrupts = <GIC_PPI 9
275 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
276 };
277
278 apdma: dma-controller@11000480 {
279 compatible = "mediatek,mt8516-uart-dma",
280 "mediatek,mt6577-uart-dma";
281 reg = <0 0x11000480 0 0x80>,
282 <0 0x11000500 0 0x80>,
283 <0 0x11000580 0 0x80>,
284 <0 0x11000600 0 0x80>,
285 <0 0x11000980 0 0x80>,
286 <0 0x11000a00 0 0x80>;
287 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
288 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
289 <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
290 <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
291 <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
292 <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
293 dma-requests = <6>;
294 clocks = <&topckgen CLK_TOP_APDMA>;
295 clock-names = "apdma";
296 #dma-cells = <1>;
297 };
298
299 uart0: serial@11005000 {
300 compatible = "mediatek,mt8516-uart",
301 "mediatek,mt6577-uart";
302 reg = <0 0x11005000 0 0x1000>;
303 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
304 clocks = <&topckgen CLK_TOP_UART0_SEL>,
305 <&topckgen CLK_TOP_UART0>;
306 clock-names = "baud", "bus";
307 dmas = <&apdma 0
308 &apdma 1>;
309 dma-names = "tx", "rx";
310 status = "disabled";
311 };
312
313 uart1: serial@11006000 {
314 compatible = "mediatek,mt8516-uart",
315 "mediatek,mt6577-uart";
316 reg = <0 0x11006000 0 0x1000>;
317 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
318 clocks = <&topckgen CLK_TOP_UART1_SEL>,
319 <&topckgen CLK_TOP_UART1>;
320 clock-names = "baud", "bus";
321 dmas = <&apdma 2
322 &apdma 3>;
323 dma-names = "tx", "rx";
324 status = "disabled";
325 };
326
327 uart2: serial@11007000 {
328 compatible = "mediatek,mt8516-uart",
329 "mediatek,mt6577-uart";
330 reg = <0 0x11007000 0 0x1000>;
331 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
332 clocks = <&topckgen CLK_TOP_UART2_SEL>,
333 <&topckgen CLK_TOP_UART2>;
334 clock-names = "baud", "bus";
335 dmas = <&apdma 4
336 &apdma 5>;
337 dma-names = "tx", "rx";
338 status = "disabled";
339 };
340
341 i2c0: i2c@11009000 {
342 compatible = "mediatek,mt8516-i2c",
343 "mediatek,mt2712-i2c";
344 reg = <0 0x11009000 0 0x90>,
345 <0 0x11000180 0 0x80>;
346 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&topckgen CLK_TOP_I2C0>,
348 <&topckgen CLK_TOP_APDMA>;
349 clock-names = "main", "dma";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 status = "disabled";
353 };
354
355 i2c1: i2c@1100a000 {
356 compatible = "mediatek,mt8516-i2c",
357 "mediatek,mt2712-i2c";
358 reg = <0 0x1100a000 0 0x90>,
359 <0 0x11000200 0 0x80>;
360 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
361 clocks = <&topckgen CLK_TOP_I2C1>,
362 <&topckgen CLK_TOP_APDMA>;
363 clock-names = "main", "dma";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 status = "disabled";
367 };
368
369 i2c2: i2c@1100b000 {
370 compatible = "mediatek,mt8516-i2c",
371 "mediatek,mt2712-i2c";
372 reg = <0 0x1100b000 0 0x90>,
373 <0 0x11000280 0 0x80>;
374 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
375 clocks = <&topckgen CLK_TOP_I2C2>,
376 <&topckgen CLK_TOP_APDMA>;
377 clock-names = "main", "dma";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 spi: spi@1100c000 {
384 compatible = "mediatek,mt8516-spi",
385 "mediatek,mt2712-spi";
386 #address-cells = <1>;
387 #size-cells = <0>;
388 reg = <0 0x1100c000 0 0x1000>;
389 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
390 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
391 <&topckgen CLK_TOP_SPI_SEL>,
392 <&topckgen CLK_TOP_SPI>;
393 clock-names = "parent-clk", "sel-clk", "spi-clk";
394 status = "disabled";
395 };
396
397 mmc0: mmc@11120000 {
398 compatible = "mediatek,mt8516-mmc";
399 reg = <0 0x11120000 0 0x1000>;
400 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
401 clocks = <&topckgen CLK_TOP_MSDC0>,
402 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
403 <&topckgen CLK_TOP_MSDC0_INFRA>;
404 clock-names = "source", "hclk", "source_cg";
405 status = "disabled";
406 };
407
408 mmc1: mmc@11130000 {
409 compatible = "mediatek,mt8516-mmc";
410 reg = <0 0x11130000 0 0x1000>;
411 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
412 clocks = <&topckgen CLK_TOP_MSDC1>,
413 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
414 <&topckgen CLK_TOP_MSDC1_INFRA>;
415 clock-names = "source", "hclk", "source_cg";
416 status = "disabled";
417 };
418
419 mmc2: mmc@11170000 {
420 compatible = "mediatek,mt8516-mmc";
421 reg = <0 0x11170000 0 0x1000>;
422 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
423 clocks = <&topckgen CLK_TOP_MSDC2>,
424 <&topckgen CLK_TOP_RG_MSDC2>,
425 <&topckgen CLK_TOP_MSDC2_INFRA>;
426 clock-names = "source", "hclk", "source_cg";
427 status = "disabled";
428 };
429
430 ethernet: ethernet@11180000 {
431 compatible = "mediatek,mt8516-eth";
432 reg = <0 0x11180000 0 0x1000>;
433 mediatek,pericfg = <&pericfg>;
434 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
435 clocks = <&topckgen CLK_TOP_RG_ETH>,
436 <&topckgen CLK_TOP_66M_ETH>,
437 <&topckgen CLK_TOP_133M_ETH>;
438 clock-names = "core", "reg", "trans";
439 status = "disabled";
440 };
441
442 rng: rng@1020c000 {
443 compatible = "mediatek,mt8516-rng",
444 "mediatek,mt7623-rng";
445 reg = <0 0x1020c000 0 0x100>;
446 clocks = <&topckgen CLK_TOP_TRNG>;
447 clock-names = "rng";
448 };
449
450 pwm: pwm@11008000 {
451 compatible = "mediatek,mt8516-pwm";
452 reg = <0 0x11008000 0 0x1000>;
453 #pwm-cells = <2>;
454 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
455 clocks = <&topckgen CLK_TOP_PWM>,
456 <&topckgen CLK_TOP_PWM_B>,
457 <&topckgen CLK_TOP_PWM1_FB>,
458 <&topckgen CLK_TOP_PWM2_FB>,
459 <&topckgen CLK_TOP_PWM3_FB>,
460 <&topckgen CLK_TOP_PWM4_FB>,
461 <&topckgen CLK_TOP_PWM5_FB>;
462 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
463 "pwm4", "pwm5";
464 };
465
466 usb0: usb@11100000 {
467 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
468 reg = <0 0x11100000 0 0x1000>;
469 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
470 interrupt-names = "mc";
471 phys = <&usb0_port PHY_TYPE_USB2>;
472 clocks = <&topckgen CLK_TOP_USB>,
473 <&topckgen CLK_TOP_USBIF>,
474 <&topckgen CLK_TOP_USB_1P>;
475 clock-names = "main","mcu","univpll";
476 status = "disabled";
477 };
478
479 usb1: usb@11190000 {
480 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
481 reg = <0 0x11190000 0 0x1000>;
482 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
483 interrupt-names = "mc";
484 phys = <&usb1_port PHY_TYPE_USB2>;
485 clocks = <&topckgen CLK_TOP_USB>,
486 <&topckgen CLK_TOP_USBIF>,
487 <&topckgen CLK_TOP_USB_1P>;
488 clock-names = "main","mcu","univpll";
489 dr_mode = "host";
490 status = "disabled";
491 };
492
493 usb_phy: t-phy@11110000 {
494 compatible = "mediatek,mt8516-tphy",
495 "mediatek,generic-tphy-v1";
496 reg = <0 0x11110000 0 0x800>;
497 #address-cells = <2>;
498 #size-cells = <2>;
499 ranges;
500 status = "disabled";
501
502 usb0_port: usb-phy@11110800 {
503 reg = <0 0x11110800 0 0x100>;
504 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
505 clock-names = "ref";
506 #phy-cells = <1>;
507 };
508
509 usb1_port: usb-phy@11110900 {
510 reg = <0 0x11110900 0 0x100>;
511 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
512 clock-names = "ref";
513 #phy-cells = <1>;
514 };
515 };
516
517 auxadc: adc@11003000 {
518 compatible = "mediatek,mt8516-auxadc",
519 "mediatek,mt8173-auxadc";
520 reg = <0 0x11003000 0 0x1000>;
521 clocks = <&topckgen CLK_TOP_AUX_ADC>;
522 clock-names = "main";
523 #io-channel-cells = <1>;
524 status = "disabled";
525 };
526 };
527 };
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