1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12 / {
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 misc@100000 {
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
22 };
23
24 gpio: gpio@2200000 {
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
39 };
40
41 ethernet@2490000 {
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
62 reset-names = "eqos";
63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65 interconnect-names = "dma-mem", "write";
66 iommus = <&smmu TEGRA186_SID_EQOS>;
67 status = "disabled";
68
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
72 snps,txpbl = <32>;
73 snps,rxpbl = <8>;
74 };
75
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
78 reg = <0x0 0x2600000 0x0 0x210000>;
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80 reset-names = "gpcdma";
81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
113 #dma-cells = <1>;
114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
115 dma-coherent;
116 dma-channel-mask = <0xfffffffe>;
117 status = "okay";
118 };
119
120 aconnect@2900000 {
121 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210-aconnect";
123 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_APB2APE>;
125 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
130 status = "disabled";
131
132 tegra_ahub: ahub@2900800 {
133 compatible = "nvidia,tegra186-ahub";
134 reg = <0x02900800 0x800>;
135 clocks = <&bpmp TEGRA186_CLK_AHUB>;
136 clock-names = "ahub";
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
139 assigned-clock-rates = <81600000>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x02900800 0x02900800 0x11800>;
143 status = "disabled";
144
145 tegra_i2s1: i2s@2901000 {
146 compatible = "nvidia,tegra186-i2s",
147 "nvidia,tegra210-i2s";
148 reg = <0x2901000 0x100>;
149 clocks = <&bpmp TEGRA186_CLK_I2S1>,
150 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
151 clock-names = "i2s", "sync_input";
152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock-rates = <1536000>;
155 sound-name-prefix = "I2S1";
156 status = "disabled";
157 };
158
159 tegra_i2s2: i2s@2901100 {
160 compatible = "nvidia,tegra186-i2s",
161 "nvidia,tegra210-i2s";
162 reg = <0x2901100 0x100>;
163 clocks = <&bpmp TEGRA186_CLK_I2S2>,
164 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
165 clock-names = "i2s", "sync_input";
166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock-rates = <1536000>;
169 sound-name-prefix = "I2S2";
170 status = "disabled";
171 };
172
173 tegra_i2s3: i2s@2901200 {
174 compatible = "nvidia,tegra186-i2s",
175 "nvidia,tegra210-i2s";
176 reg = <0x2901200 0x100>;
177 clocks = <&bpmp TEGRA186_CLK_I2S3>,
178 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
179 clock-names = "i2s", "sync_input";
180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock-rates = <1536000>;
183 sound-name-prefix = "I2S3";
184 status = "disabled";
185 };
186
187 tegra_i2s4: i2s@2901300 {
188 compatible = "nvidia,tegra186-i2s",
189 "nvidia,tegra210-i2s";
190 reg = <0x2901300 0x100>;
191 clocks = <&bpmp TEGRA186_CLK_I2S4>,
192 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
193 clock-names = "i2s", "sync_input";
194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock-rates = <1536000>;
197 sound-name-prefix = "I2S4";
198 status = "disabled";
199 };
200
201 tegra_i2s5: i2s@2901400 {
202 compatible = "nvidia,tegra186-i2s",
203 "nvidia,tegra210-i2s";
204 reg = <0x2901400 0x100>;
205 clocks = <&bpmp TEGRA186_CLK_I2S5>,
206 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
207 clock-names = "i2s", "sync_input";
208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock-rates = <1536000>;
211 sound-name-prefix = "I2S5";
212 status = "disabled";
213 };
214
215 tegra_i2s6: i2s@2901500 {
216 compatible = "nvidia,tegra186-i2s",
217 "nvidia,tegra210-i2s";
218 reg = <0x2901500 0x100>;
219 clocks = <&bpmp TEGRA186_CLK_I2S6>,
220 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
221 clock-names = "i2s", "sync_input";
222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock-rates = <1536000>;
225 sound-name-prefix = "I2S6";
226 status = "disabled";
227 };
228
229 tegra_sfc1: sfc@2902000 {
230 compatible = "nvidia,tegra186-sfc",
231 "nvidia,tegra210-sfc";
232 reg = <0x2902000 0x200>;
233 sound-name-prefix = "SFC1";
234 status = "disabled";
235 };
236
237 tegra_sfc2: sfc@2902200 {
238 compatible = "nvidia,tegra186-sfc",
239 "nvidia,tegra210-sfc";
240 reg = <0x2902200 0x200>;
241 sound-name-prefix = "SFC2";
242 status = "disabled";
243 };
244
245 tegra_sfc3: sfc@2902400 {
246 compatible = "nvidia,tegra186-sfc",
247 "nvidia,tegra210-sfc";
248 reg = <0x2902400 0x200>;
249 sound-name-prefix = "SFC3";
250 status = "disabled";
251 };
252
253 tegra_sfc4: sfc@2902600 {
254 compatible = "nvidia,tegra186-sfc",
255 "nvidia,tegra210-sfc";
256 reg = <0x2902600 0x200>;
257 sound-name-prefix = "SFC4";
258 status = "disabled";
259 };
260
261 tegra_amx1: amx@2903000 {
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
264 reg = <0x2903000 0x100>;
265 sound-name-prefix = "AMX1";
266 status = "disabled";
267 };
268
269 tegra_amx2: amx@2903100 {
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
272 reg = <0x2903100 0x100>;
273 sound-name-prefix = "AMX2";
274 status = "disabled";
275 };
276
277 tegra_amx3: amx@2903200 {
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
280 reg = <0x2903200 0x100>;
281 sound-name-prefix = "AMX3";
282 status = "disabled";
283 };
284
285 tegra_amx4: amx@2903300 {
286 compatible = "nvidia,tegra186-amx",
287 "nvidia,tegra210-amx";
288 reg = <0x2903300 0x100>;
289 sound-name-prefix = "AMX4";
290 status = "disabled";
291 };
292
293 tegra_adx1: adx@2903800 {
294 compatible = "nvidia,tegra186-adx",
295 "nvidia,tegra210-adx";
296 reg = <0x2903800 0x100>;
297 sound-name-prefix = "ADX1";
298 status = "disabled";
299 };
300
301 tegra_adx2: adx@2903900 {
302 compatible = "nvidia,tegra186-adx",
303 "nvidia,tegra210-adx";
304 reg = <0x2903900 0x100>;
305 sound-name-prefix = "ADX2";
306 status = "disabled";
307 };
308
309 tegra_adx3: adx@2903a00 {
310 compatible = "nvidia,tegra186-adx",
311 "nvidia,tegra210-adx";
312 reg = <0x2903a00 0x100>;
313 sound-name-prefix = "ADX3";
314 status = "disabled";
315 };
316
317 tegra_adx4: adx@2903b00 {
318 compatible = "nvidia,tegra186-adx",
319 "nvidia,tegra210-adx";
320 reg = <0x2903b00 0x100>;
321 sound-name-prefix = "ADX4";
322 status = "disabled";
323 };
324
325 tegra_dmic1: dmic@2904000 {
326 compatible = "nvidia,tegra210-dmic";
327 reg = <0x2904000 0x100>;
328 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
329 clock-names = "dmic";
330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock-rates = <3072000>;
333 sound-name-prefix = "DMIC1";
334 status = "disabled";
335 };
336
337 tegra_dmic2: dmic@2904100 {
338 compatible = "nvidia,tegra210-dmic";
339 reg = <0x2904100 0x100>;
340 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
341 clock-names = "dmic";
342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock-rates = <3072000>;
345 sound-name-prefix = "DMIC2";
346 status = "disabled";
347 };
348
349 tegra_dmic3: dmic@2904200 {
350 compatible = "nvidia,tegra210-dmic";
351 reg = <0x2904200 0x100>;
352 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
353 clock-names = "dmic";
354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock-rates = <3072000>;
357 sound-name-prefix = "DMIC3";
358 status = "disabled";
359 };
360
361 tegra_dmic4: dmic@2904300 {
362 compatible = "nvidia,tegra210-dmic";
363 reg = <0x2904300 0x100>;
364 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
365 clock-names = "dmic";
366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock-rates = <3072000>;
369 sound-name-prefix = "DMIC4";
370 status = "disabled";
371 };
372
373 tegra_dspk1: dspk@2905000 {
374 compatible = "nvidia,tegra186-dspk";
375 reg = <0x2905000 0x100>;
376 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
377 clock-names = "dspk";
378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock-rates = <12288000>;
381 sound-name-prefix = "DSPK1";
382 status = "disabled";
383 };
384
385 tegra_dspk2: dspk@2905100 {
386 compatible = "nvidia,tegra186-dspk";
387 reg = <0x2905100 0x100>;
388 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
389 clock-names = "dspk";
390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock-rates = <12288000>;
393 sound-name-prefix = "DSPK2";
394 status = "disabled";
395 };
396
397 tegra_ope1: processing-engine@2908000 {
398 compatible = "nvidia,tegra186-ope",
399 "nvidia,tegra210-ope";
400 reg = <0x2908000 0x100>;
401 #address-cells = <1>;
402 #size-cells = <1>;
403 ranges;
404 sound-name-prefix = "OPE1";
405 status = "disabled";
406
407 equalizer@2908100 {
408 compatible = "nvidia,tegra186-peq",
409 "nvidia,tegra210-peq";
410 reg = <0x2908100 0x100>;
411 };
412
413 dynamic-range-compressor@2908200 {
414 compatible = "nvidia,tegra186-mbdrc",
415 "nvidia,tegra210-mbdrc";
416 reg = <0x2908200 0x200>;
417 };
418 };
419
420 tegra_mvc1: mvc@290a000 {
421 compatible = "nvidia,tegra186-mvc",
422 "nvidia,tegra210-mvc";
423 reg = <0x290a000 0x200>;
424 sound-name-prefix = "MVC1";
425 status = "disabled";
426 };
427
428 tegra_mvc2: mvc@290a200 {
429 compatible = "nvidia,tegra186-mvc",
430 "nvidia,tegra210-mvc";
431 reg = <0x290a200 0x200>;
432 sound-name-prefix = "MVC2";
433 status = "disabled";
434 };
435
436 tegra_amixer: amixer@290bb00 {
437 compatible = "nvidia,tegra186-amixer",
438 "nvidia,tegra210-amixer";
439 reg = <0x290bb00 0x800>;
440 sound-name-prefix = "MIXER1";
441 status = "disabled";
442 };
443
444 tegra_admaif: admaif@290f000 {
445 compatible = "nvidia,tegra186-admaif";
446 reg = <0x0290f000 0x1000>;
447 dmas = <&adma 1>, <&adma 1>,
448 <&adma 2>, <&adma 2>,
449 <&adma 3>, <&adma 3>,
450 <&adma 4>, <&adma 4>,
451 <&adma 5>, <&adma 5>,
452 <&adma 6>, <&adma 6>,
453 <&adma 7>, <&adma 7>,
454 <&adma 8>, <&adma 8>,
455 <&adma 9>, <&adma 9>,
456 <&adma 10>, <&adma 10>,
457 <&adma 11>, <&adma 11>,
458 <&adma 12>, <&adma 12>,
459 <&adma 13>, <&adma 13>,
460 <&adma 14>, <&adma 14>,
461 <&adma 15>, <&adma 15>,
462 <&adma 16>, <&adma 16>,
463 <&adma 17>, <&adma 17>,
464 <&adma 18>, <&adma 18>,
465 <&adma 19>, <&adma 19>,
466 <&adma 20>, <&adma 20>;
467 dma-names = "rx1", "tx1",
468 "rx2", "tx2",
469 "rx3", "tx3",
470 "rx4", "tx4",
471 "rx5", "tx5",
472 "rx6", "tx6",
473 "rx7", "tx7",
474 "rx8", "tx8",
475 "rx9", "tx9",
476 "rx10", "tx10",
477 "rx11", "tx11",
478 "rx12", "tx12",
479 "rx13", "tx13",
480 "rx14", "tx14",
481 "rx15", "tx15",
482 "rx16", "tx16",
483 "rx17", "tx17",
484 "rx18", "tx18",
485 "rx19", "tx19",
486 "rx20", "tx20";
487 status = "disabled";
488 };
489
490 tegra_asrc: asrc@2910000 {
491 compatible = "nvidia,tegra186-asrc";
492 reg = <0x2910000 0x2000>;
493 sound-name-prefix = "ASRC1";
494 status = "disabled";
495 };
496 };
497
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,tegra186-adma";
500 reg = <0x02930000 0x20000>;
501 interrupt-parent = <&agic>;
502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
534 #dma-cells = <1>;
535 clocks = <&bpmp TEGRA186_CLK_AHUB>;
536 clock-names = "d_audio";
537 status = "disabled";
538 };
539
540 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,tegra186-agic",
542 "nvidia,tegra210-agic";
543 #interrupt-cells = <3>;
544 interrupt-controller;
545 reg = <0x02a41000 0x1000>,
546 <0x02a42000 0x2000>;
547 interrupts = <GIC_SPI 145
548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
549 clocks = <&bpmp TEGRA186_CLK_APE>;
550 clock-names = "clk";
551 status = "disabled";
552 };
553 };
554
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
558 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
559 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
560 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
561 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
562 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
565 status = "disabled";
566
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
569 #size-cells = <2>;
570
571 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
572
573 /*
574 * Memory clients have access to all 40 bits that the memory
575 * controller can address.
576 */
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
578
579 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,tegra186-emc";
581 reg = <0x0 0x02c60000 0x0 0x50000>;
582 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&bpmp TEGRA186_CLK_EMC>;
584 clock-names = "emc";
585
586 #interconnect-cells = <0>;
587
588 nvidia,bpmp = <&bpmp>;
589 };
590 };
591
592 timer@3010000 {
593 compatible = "nvidia,tegra186-timer";
594 reg = <0x0 0x03010000 0x0 0x000e0000>;
595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
605 status = "okay";
606 };
607
608 uarta: serial@3100000 {
609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
610 reg = <0x0 0x03100000 0x0 0x40>;
611 reg-shift = <2>;
612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&bpmp TEGRA186_CLK_UARTA>;
614 resets = <&bpmp TEGRA186_RESET_UARTA>;
615 status = "disabled";
616 };
617
618 uartb: serial@3110000 {
619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620 reg = <0x0 0x03110000 0x0 0x40>;
621 reg-shift = <2>;
622 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&bpmp TEGRA186_CLK_UARTB>;
624 clock-names = "serial";
625 resets = <&bpmp TEGRA186_RESET_UARTB>;
626 reset-names = "serial";
627 status = "disabled";
628 };
629
630 uartd: serial@3130000 {
631 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632 reg = <0x0 0x03130000 0x0 0x40>;
633 reg-shift = <2>;
634 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&bpmp TEGRA186_CLK_UARTD>;
636 clock-names = "serial";
637 resets = <&bpmp TEGRA186_RESET_UARTD>;
638 reset-names = "serial";
639 status = "disabled";
640 };
641
642 uarte: serial@3140000 {
643 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
644 reg = <0x0 0x03140000 0x0 0x40>;
645 reg-shift = <2>;
646 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&bpmp TEGRA186_CLK_UARTE>;
648 clock-names = "serial";
649 resets = <&bpmp TEGRA186_RESET_UARTE>;
650 reset-names = "serial";
651 status = "disabled";
652 };
653
654 uartf: serial@3150000 {
655 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
656 reg = <0x0 0x03150000 0x0 0x40>;
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&bpmp TEGRA186_CLK_UARTF>;
660 clock-names = "serial";
661 resets = <&bpmp TEGRA186_RESET_UARTF>;
662 reset-names = "serial";
663 status = "disabled";
664 };
665
666 gen1_i2c: i2c@3160000 {
667 compatible = "nvidia,tegra186-i2c";
668 reg = <0x0 0x03160000 0x0 0x10000>;
669 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 clocks = <&bpmp TEGRA186_CLK_I2C1>;
673 clock-names = "div-clk";
674 resets = <&bpmp TEGRA186_RESET_I2C1>;
675 reset-names = "i2c";
676 dmas = <&gpcdma 21>, <&gpcdma 21>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 cam_i2c: i2c@3180000 {
682 compatible = "nvidia,tegra186-i2c";
683 reg = <0x0 0x03180000 0x0 0x10000>;
684 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clocks = <&bpmp TEGRA186_CLK_I2C3>;
688 clock-names = "div-clk";
689 resets = <&bpmp TEGRA186_RESET_I2C3>;
690 reset-names = "i2c";
691 dmas = <&gpcdma 23>, <&gpcdma 23>;
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
695
696 /* shares pads with dpaux1 */
697 dp_aux_ch1_i2c: i2c@3190000 {
698 compatible = "nvidia,tegra186-i2c";
699 reg = <0x0 0x03190000 0x0 0x10000>;
700 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>;
702 #size-cells = <0>;
703 clocks = <&bpmp TEGRA186_CLK_I2C4>;
704 clock-names = "div-clk";
705 resets = <&bpmp TEGRA186_RESET_I2C4>;
706 reset-names = "i2c";
707 pinctrl-names = "default", "idle";
708 pinctrl-0 = <&state_dpaux1_i2c>;
709 pinctrl-1 = <&state_dpaux1_off>;
710 dmas = <&gpcdma 26>, <&gpcdma 26>;
711 dma-names = "rx", "tx";
712 status = "disabled";
713 };
714
715 /* controlled by BPMP, should not be enabled */
716 pwr_i2c: i2c@31a0000 {
717 compatible = "nvidia,tegra186-i2c";
718 reg = <0x0 0x031a0000 0x0 0x10000>;
719 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>;
721 #size-cells = <0>;
722 clocks = <&bpmp TEGRA186_CLK_I2C5>;
723 clock-names = "div-clk";
724 resets = <&bpmp TEGRA186_RESET_I2C5>;
725 reset-names = "i2c";
726 status = "disabled";
727 };
728
729 /* shares pads with dpaux0 */
730 dp_aux_ch0_i2c: i2c@31b0000 {
731 compatible = "nvidia,tegra186-i2c";
732 reg = <0x0 0x031b0000 0x0 0x10000>;
733 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
734 #address-cells = <1>;
735 #size-cells = <0>;
736 clocks = <&bpmp TEGRA186_CLK_I2C6>;
737 clock-names = "div-clk";
738 resets = <&bpmp TEGRA186_RESET_I2C6>;
739 reset-names = "i2c";
740 pinctrl-names = "default", "idle";
741 pinctrl-0 = <&state_dpaux_i2c>;
742 pinctrl-1 = <&state_dpaux_off>;
743 dmas = <&gpcdma 30>, <&gpcdma 30>;
744 dma-names = "rx", "tx";
745 status = "disabled";
746 };
747
748 gen7_i2c: i2c@31c0000 {
749 compatible = "nvidia,tegra186-i2c";
750 reg = <0x0 0x031c0000 0x0 0x10000>;
751 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 clocks = <&bpmp TEGRA186_CLK_I2C7>;
755 clock-names = "div-clk";
756 resets = <&bpmp TEGRA186_RESET_I2C7>;
757 reset-names = "i2c";
758 dmas = <&gpcdma 27>, <&gpcdma 27>;
759 dma-names = "rx", "tx";
760 status = "disabled";
761 };
762
763 gen9_i2c: i2c@31e0000 {
764 compatible = "nvidia,tegra186-i2c";
765 reg = <0x0 0x031e0000 0x0 0x10000>;
766 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&bpmp TEGRA186_CLK_I2C9>;
770 clock-names = "div-clk";
771 resets = <&bpmp TEGRA186_RESET_I2C9>;
772 reset-names = "i2c";
773 dmas = <&gpcdma 31>, <&gpcdma 31>;
774 dma-names = "rx", "tx";
775 status = "disabled";
776 };
777
778 pwm1: pwm@3280000 {
779 compatible = "nvidia,tegra186-pwm";
780 reg = <0x0 0x3280000 0x0 0x10000>;
781 clocks = <&bpmp TEGRA186_CLK_PWM1>;
782 resets = <&bpmp TEGRA186_RESET_PWM1>;
783 reset-names = "pwm";
784 status = "disabled";
785 #pwm-cells = <2>;
786 };
787
788 pwm2: pwm@3290000 {
789 compatible = "nvidia,tegra186-pwm";
790 reg = <0x0 0x3290000 0x0 0x10000>;
791 clocks = <&bpmp TEGRA186_CLK_PWM2>;
792 resets = <&bpmp TEGRA186_RESET_PWM2>;
793 reset-names = "pwm";
794 status = "disabled";
795 #pwm-cells = <2>;
796 };
797
798 pwm3: pwm@32a0000 {
799 compatible = "nvidia,tegra186-pwm";
800 reg = <0x0 0x32a0000 0x0 0x10000>;
801 clocks = <&bpmp TEGRA186_CLK_PWM3>;
802 resets = <&bpmp TEGRA186_RESET_PWM3>;
803 reset-names = "pwm";
804 status = "disabled";
805 #pwm-cells = <2>;
806 };
807
808 pwm5: pwm@32c0000 {
809 compatible = "nvidia,tegra186-pwm";
810 reg = <0x0 0x32c0000 0x0 0x10000>;
811 clocks = <&bpmp TEGRA186_CLK_PWM5>;
812 resets = <&bpmp TEGRA186_RESET_PWM5>;
813 reset-names = "pwm";
814 status = "disabled";
815 #pwm-cells = <2>;
816 };
817
818 pwm6: pwm@32d0000 {
819 compatible = "nvidia,tegra186-pwm";
820 reg = <0x0 0x32d0000 0x0 0x10000>;
821 clocks = <&bpmp TEGRA186_CLK_PWM6>;
822 resets = <&bpmp TEGRA186_RESET_PWM6>;
823 reset-names = "pwm";
824 status = "disabled";
825 #pwm-cells = <2>;
826 };
827
828 pwm7: pwm@32e0000 {
829 compatible = "nvidia,tegra186-pwm";
830 reg = <0x0 0x32e0000 0x0 0x10000>;
831 clocks = <&bpmp TEGRA186_CLK_PWM7>;
832 resets = <&bpmp TEGRA186_RESET_PWM7>;
833 reset-names = "pwm";
834 status = "disabled";
835 #pwm-cells = <2>;
836 };
837
838 pwm8: pwm@32f0000 {
839 compatible = "nvidia,tegra186-pwm";
840 reg = <0x0 0x32f0000 0x0 0x10000>;
841 clocks = <&bpmp TEGRA186_CLK_PWM8>;
842 resets = <&bpmp TEGRA186_RESET_PWM8>;
843 reset-names = "pwm";
844 status = "disabled";
845 #pwm-cells = <2>;
846 };
847
848 sdmmc1: mmc@3400000 {
849 compatible = "nvidia,tegra186-sdhci";
850 reg = <0x0 0x03400000 0x0 0x10000>;
851 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
853 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
854 clock-names = "sdhci", "tmclk";
855 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
856 reset-names = "sdhci";
857 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
858 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
859 interconnect-names = "dma-mem", "write";
860 iommus = <&smmu TEGRA186_SID_SDMMC1>;
861 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
862 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
873 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
875 status = "disabled";
876 };
877
878 sdmmc2: mmc@3420000 {
879 compatible = "nvidia,tegra186-sdhci";
880 reg = <0x0 0x03420000 0x0 0x10000>;
881 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
883 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
884 clock-names = "sdhci", "tmclk";
885 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
886 reset-names = "sdhci";
887 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
888 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
889 interconnect-names = "dma-mem", "write";
890 iommus = <&smmu TEGRA186_SID_SDMMC2>;
891 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
892 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>;
900 status = "disabled";
901 };
902
903 sdmmc3: mmc@3440000 {
904 compatible = "nvidia,tegra186-sdhci";
905 reg = <0x0 0x03440000 0x0 0x10000>;
906 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
908 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
909 clock-names = "sdhci", "tmclk";
910 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
911 reset-names = "sdhci";
912 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
913 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
914 interconnect-names = "dma-mem", "write";
915 iommus = <&smmu TEGRA186_SID_SDMMC3>;
916 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
917 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>;
927 status = "disabled";
928 };
929
930 sdmmc4: mmc@3460000 {
931 compatible = "nvidia,tegra186-sdhci";
932 reg = <0x0 0x03460000 0x0 0x10000>;
933 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
935 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
936 clock-names = "sdhci", "tmclk";
937 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
938 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
939 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
941 reset-names = "sdhci";
942 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
943 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
944 interconnect-names = "dma-mem", "write";
945 iommus = <&smmu TEGRA186_SID_SDMMC4>;
946 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>;
955 mmc-hs400-1_8v;
956 supports-cqe;
957 status = "disabled";
958 };
959
960 sata@3507000 {
961 compatible = "nvidia,tegra186-ahci";
962 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
963 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
964 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
965 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
966
967 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
968 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
969 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
970 interconnect-names = "dma-mem", "write";
971 iommus = <&smmu TEGRA186_SID_SATA>;
972
973 clocks = <&bpmp TEGRA186_CLK_SATA>,
974 <&bpmp TEGRA186_CLK_SATA_OOB>;
975 clock-names = "sata", "sata-oob";
976 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
977 <&bpmp TEGRA186_CLK_SATA_OOB>;
978 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
979 <&bpmp TEGRA186_CLK_PLLP>;
980 assigned-clock-rates = <102000000>,
981 <204000000>;
982 resets = <&bpmp TEGRA186_RESET_SATA>,
983 <&bpmp TEGRA186_RESET_SATACOLD>;
984 reset-names = "sata", "sata-cold";
985 status = "disabled";
986 };
987
988 hda@3510000 {
989 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
990 reg = <0x0 0x03510000 0x0 0x10000>;
991 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&bpmp TEGRA186_CLK_HDA>,
993 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
994 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
995 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
996 resets = <&bpmp TEGRA186_RESET_HDA>,
997 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
998 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
999 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1001 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
1002 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
1003 interconnect-names = "dma-mem", "write";
1004 iommus = <&smmu TEGRA186_SID_HDA>;
1005 status = "disabled";
1006 };
1007
1008 padctl: padctl@3520000 {
1009 compatible = "nvidia,tegra186-xusb-padctl";
1010 reg = <0x0 0x03520000 0x0 0x1000>,
1011 <0x0 0x03540000 0x0 0x1000>;
1012 reg-names = "padctl", "ao";
1013 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1014
1015 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1016 reset-names = "padctl";
1017
1018 status = "disabled";
1019
1020 pads {
1021 usb2 {
1022 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1023 clock-names = "trk";
1024 status = "disabled";
1025
1026 lanes {
1027 usb2-0 {
1028 status = "disabled";
1029 #phy-cells = <0>;
1030 };
1031
1032 usb2-1 {
1033 status = "disabled";
1034 #phy-cells = <0>;
1035 };
1036
1037 usb2-2 {
1038 status = "disabled";
1039 #phy-cells = <0>;
1040 };
1041 };
1042 };
1043
1044 hsic {
1045 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1046 clock-names = "trk";
1047 status = "disabled";
1048
1049 lanes {
1050 hsic-0 {
1051 status = "disabled";
1052 #phy-cells = <0>;
1053 };
1054 };
1055 };
1056
1057 usb3 {
1058 status = "disabled";
1059
1060 lanes {
1061 usb3-0 {
1062 status = "disabled";
1063 #phy-cells = <0>;
1064 };
1065
1066 usb3-1 {
1067 status = "disabled";
1068 #phy-cells = <0>;
1069 };
1070
1071 usb3-2 {
1072 status = "disabled";
1073 #phy-cells = <0>;
1074 };
1075 };
1076 };
1077 };
1078
1079 ports {
1080 usb2-0 {
1081 status = "disabled";
1082 };
1083
1084 usb2-1 {
1085 status = "disabled";
1086 };
1087
1088 usb2-2 {
1089 status = "disabled";
1090 };
1091
1092 hsic-0 {
1093 status = "disabled";
1094 };
1095
1096 usb3-0 {
1097 status = "disabled";
1098 };
1099
1100 usb3-1 {
1101 status = "disabled";
1102 };
1103
1104 usb3-2 {
1105 status = "disabled";
1106 };
1107 };
1108 };
1109
1110 usb@3530000 {
1111 compatible = "nvidia,tegra186-xusb";
1112 reg = <0x0 0x03530000 0x0 0x8000>,
1113 <0x0 0x03538000 0x0 0x1000>;
1114 reg-names = "hcd", "fpci";
1115 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1118 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1119 <&bpmp TEGRA186_CLK_XUSB_SS>,
1120 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1121 <&bpmp TEGRA186_CLK_CLK_M>,
1122 <&bpmp TEGRA186_CLK_XUSB_FS>,
1123 <&bpmp TEGRA186_CLK_PLLU>,
1124 <&bpmp TEGRA186_CLK_CLK_M>,
1125 <&bpmp TEGRA186_CLK_PLLE>;
1126 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1127 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1128 "pll_u_480m", "clk_m", "pll_e";
1129 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1130 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1131 power-domain-names = "xusb_host", "xusb_ss";
1132 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1133 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1134 interconnect-names = "dma-mem", "write";
1135 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 status = "disabled";
1139
1140 nvidia,xusb-padctl = <&padctl>;
1141 };
1142
1143 usb@3550000 {
1144 compatible = "nvidia,tegra186-xudc";
1145 reg = <0x0 0x03550000 0x0 0x8000>,
1146 <0x0 0x03558000 0x0 0x1000>;
1147 reg-names = "base", "fpci";
1148 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1150 <&bpmp TEGRA186_CLK_XUSB_SS>,
1151 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1152 <&bpmp TEGRA186_CLK_XUSB_FS>;
1153 clock-names = "dev", "ss", "ss_src", "fs_src";
1154 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1155 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1156 interconnect-names = "dma-mem", "write";
1157 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1159 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1160 power-domain-names = "dev", "ss";
1161 nvidia,xusb-padctl = <&padctl>;
1162 status = "disabled";
1163 };
1164
1165 fuse@3820000 {
1166 compatible = "nvidia,tegra186-efuse";
1167 reg = <0x0 0x03820000 0x0 0x10000>;
1168 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1169 clock-names = "fuse";
1170 };
1171
1172 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>;
1175 interrupt-controller;
1176 reg = <0x0 0x03881000 0x0 0x1000>,
1177 <0x0 0x03882000 0x0 0x2000>,
1178 <0x0 0x03884000 0x0 0x2000>,
1179 <0x0 0x03886000 0x0 0x2000>;
1180 interrupts = <GIC_PPI 9
1181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1182 interrupt-parent = <&gic>;
1183 };
1184
1185 cec@3960000 {
1186 compatible = "nvidia,tegra186-cec";
1187 reg = <0x0 0x03960000 0x0 0x10000>;
1188 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&bpmp TEGRA186_CLK_CEC>;
1190 clock-names = "cec";
1191 status = "disabled";
1192 };
1193
1194 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186-hsp";
1196 reg = <0x0 0x03c00000 0x0 0xa0000>;
1197 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "doorbell";
1199 #mbox-cells = <2>;
1200 status = "disabled";
1201 };
1202
1203 gen2_i2c: i2c@c240000 {
1204 compatible = "nvidia,tegra186-i2c";
1205 reg = <0x0 0x0c240000 0x0 0x10000>;
1206 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1210 clock-names = "div-clk";
1211 resets = <&bpmp TEGRA186_RESET_I2C2>;
1212 reset-names = "i2c";
1213 dmas = <&gpcdma 22>, <&gpcdma 22>;
1214 dma-names = "rx", "tx";
1215 status = "disabled";
1216 };
1217
1218 gen8_i2c: i2c@c250000 {
1219 compatible = "nvidia,tegra186-i2c";
1220 reg = <0x0 0x0c250000 0x0 0x10000>;
1221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1225 clock-names = "div-clk";
1226 resets = <&bpmp TEGRA186_RESET_I2C8>;
1227 reset-names = "i2c";
1228 dmas = <&gpcdma 0>, <&gpcdma 0>;
1229 dma-names = "rx", "tx";
1230 status = "disabled";
1231 };
1232
1233 uartc: serial@c280000 {
1234 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1235 reg = <0x0 0x0c280000 0x0 0x40>;
1236 reg-shift = <2>;
1237 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1239 clock-names = "serial";
1240 resets = <&bpmp TEGRA186_RESET_UARTC>;
1241 reset-names = "serial";
1242 status = "disabled";
1243 };
1244
1245 uartg: serial@c290000 {
1246 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1247 reg = <0x0 0x0c290000 0x0 0x40>;
1248 reg-shift = <2>;
1249 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1251 clock-names = "serial";
1252 resets = <&bpmp TEGRA186_RESET_UARTG>;
1253 reset-names = "serial";
1254 status = "disabled";
1255 };
1256
1257 rtc: rtc@c2a0000 {
1258 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1259 reg = <0 0x0c2a0000 0 0x10000>;
1260 interrupt-parent = <&pmc>;
1261 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1263 clock-names = "rtc";
1264 status = "disabled";
1265 };
1266
1267 gpio_aon: gpio@c2f0000 {
1268 compatible = "nvidia,tegra186-gpio-aon";
1269 reg-names = "security", "gpio";
1270 reg = <0x0 0xc2f0000 0x0 0x1000>,
1271 <0x0 0xc2f1000 0x0 0x1000>;
1272 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1273 gpio-controller;
1274 #gpio-cells = <2>;
1275 interrupt-controller;
1276 #interrupt-cells = <2>;
1277 };
1278
1279 pwm4: pwm@c340000 {
1280 compatible = "nvidia,tegra186-pwm";
1281 reg = <0x0 0xc340000 0x0 0x10000>;
1282 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1283 resets = <&bpmp TEGRA186_RESET_PWM4>;
1284 reset-names = "pwm";
1285 status = "disabled";
1286 #pwm-cells = <2>;
1287 };
1288
1289 pmc: pmc@c360000 {
1290 compatible = "nvidia,tegra186-pmc";
1291 reg = <0 0x0c360000 0 0x10000>,
1292 <0 0x0c370000 0 0x10000>,
1293 <0 0x0c380000 0 0x10000>,
1294 <0 0x0c390000 0 0x10000>;
1295 reg-names = "pmc", "wake", "aotag", "scratch";
1296
1297 #interrupt-cells = <2>;
1298 interrupt-controller;
1299
1300 sdmmc1_1v8: sdmmc1-1v8 {
1301 pins = "sdmmc1-hv";
1302 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1303 };
1304
1305 sdmmc1_3v3: sdmmc1-3v3 {
1306 pins = "sdmmc1-hv";
1307 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1308 };
1309
1310 sdmmc2_1v8: sdmmc2-1v8 {
1311 pins = "sdmmc2-hv";
1312 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1313 };
1314
1315 sdmmc2_3v3: sdmmc2-3v3 {
1316 pins = "sdmmc2-hv";
1317 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1318 };
1319
1320 sdmmc3_1v8: sdmmc3-1v8 {
1321 pins = "sdmmc3-hv";
1322 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1323 };
1324
1325 sdmmc3_3v3: sdmmc3-3v3 {
1326 pins = "sdmmc3-hv";
1327 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1328 };
1329 };
1330
1331 ccplex@e000000 {
1332 compatible = "nvidia,tegra186-ccplex-cluster";
1333 reg = <0x0 0x0e000000 0x0 0x400000>;
1334
1335 nvidia,bpmp = <&bpmp>;
1336 };
1337
1338 pcie@10003000 {
1339 compatible = "nvidia,tegra186-pcie";
1340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1341 device_type = "pci";
1342 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1343 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1344 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1345 reg-names = "pads", "afi", "cs";
1346
1347 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1348 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1349 interrupt-names = "intr", "msi";
1350
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1354
1355 bus-range = <0x00 0xff>;
1356 #address-cells = <3>;
1357 #size-cells = <2>;
1358
1359 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1360 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1361 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1362 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1363 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1364 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1365
1366 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1367 <&bpmp TEGRA186_CLK_AFI>,
1368 <&bpmp TEGRA186_CLK_PLLE>;
1369 clock-names = "pex", "afi", "pll_e";
1370
1371 resets = <&bpmp TEGRA186_RESET_PCIE>,
1372 <&bpmp TEGRA186_RESET_AFI>,
1373 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1374 reset-names = "pex", "afi", "pcie_x";
1375
1376 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1377 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1378 interconnect-names = "dma-mem", "write";
1379
1380 iommus = <&smmu TEGRA186_SID_AFI>;
1381 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>;
1383
1384 status = "disabled";
1385
1386 pci@1,0 {
1387 device_type = "pci";
1388 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1389 reg = <0x000800 0 0 0 0>;
1390 status = "disabled";
1391
1392 #address-cells = <3>;
1393 #size-cells = <2>;
1394 ranges;
1395
1396 nvidia,num-lanes = <2>;
1397 };
1398
1399 pci@2,0 {
1400 device_type = "pci";
1401 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1402 reg = <0x001000 0 0 0 0>;
1403 status = "disabled";
1404
1405 #address-cells = <3>;
1406 #size-cells = <2>;
1407 ranges;
1408
1409 nvidia,num-lanes = <1>;
1410 };
1411
1412 pci@3,0 {
1413 device_type = "pci";
1414 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1415 reg = <0x001800 0 0 0 0>;
1416 status = "disabled";
1417
1418 #address-cells = <3>;
1419 #size-cells = <2>;
1420 ranges;
1421
1422 nvidia,num-lanes = <1>;
1423 };
1424 };
1425
1426 smmu: iommu@12000000 {
1427 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1428 reg = <0 0x12000000 0 0x800000>;
1429 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1494 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>;
1496 #iommu-cells = <1>;
1497
1498 nvidia,memory-controller = <&mc>;
1499 };
1500
1501 host1x@13e00000 {
1502 compatible = "nvidia,tegra186-host1x";
1503 reg = <0x0 0x13e00000 0x0 0x10000>,
1504 <0x0 0x13e10000 0x0 0x10000>;
1505 reg-names = "hypervisor", "vm";
1506 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-names = "syncpt", "host1x";
1509 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1510 clock-names = "host1x";
1511 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1512 reset-names = "host1x";
1513
1514 #address-cells = <1>;
1515 #size-cells = <1>;
1516
1517 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1518
1519 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1520 interconnect-names = "dma-mem";
1521
1522 iommus = <&smmu TEGRA186_SID_HOST1X>;
1523
1524 /* Context isolation domains */
1525 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1526 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
1527 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
1528 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
1529 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
1530 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
1531 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
1532 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
1533
1534 dpaux1: dpaux@15040000 {
1535 compatible = "nvidia,tegra186-dpaux";
1536 reg = <0x15040000 0x10000>;
1537 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1538 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1539 <&bpmp TEGRA186_CLK_PLLDP>;
1540 clock-names = "dpaux", "parent";
1541 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1542 reset-names = "dpaux";
1543 status = "disabled";
1544
1545 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1546
1547 state_dpaux1_aux: pinmux-aux {
1548 groups = "dpaux-io";
1549 function = "aux";
1550 };
1551
1552 state_dpaux1_i2c: pinmux-i2c {
1553 groups = "dpaux-io";
1554 function = "i2c";
1555 };
1556
1557 state_dpaux1_off: pinmux-off {
1558 groups = "dpaux-io";
1559 function = "off";
1560 };
1561
1562 i2c-bus {
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1565 };
1566 };
1567
1568 display-hub@15200000 {
1569 compatible = "nvidia,tegra186-display";
1570 reg = <0x15200000 0x00040000>;
1571 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1572 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1573 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1577 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1578 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1579 "wgrp3", "wgrp4", "wgrp5";
1580 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1581 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1582 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1583 clock-names = "disp", "dsc", "hub";
1584 status = "disabled";
1585
1586 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1587
1588 #address-cells = <1>;
1589 #size-cells = <1>;
1590
1591 ranges = <0x15200000 0x15200000 0x40000>;
1592
1593 display@15200000 {
1594 compatible = "nvidia,tegra186-dc";
1595 reg = <0x15200000 0x10000>;
1596 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1598 clock-names = "dc";
1599 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1600 reset-names = "dc";
1601
1602 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1603 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1604 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1605 interconnect-names = "dma-mem", "read-1";
1606 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1607
1608 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1609 nvidia,head = <0>;
1610 };
1611
1612 display@15210000 {
1613 compatible = "nvidia,tegra186-dc";
1614 reg = <0x15210000 0x10000>;
1615 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1617 clock-names = "dc";
1618 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1619 reset-names = "dc";
1620
1621 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1622 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1623 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1624 interconnect-names = "dma-mem", "read-1";
1625 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1626
1627 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1628 nvidia,head = <1>;
1629 };
1630
1631 display@15220000 {
1632 compatible = "nvidia,tegra186-dc";
1633 reg = <0x15220000 0x10000>;
1634 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1636 clock-names = "dc";
1637 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1638 reset-names = "dc";
1639
1640 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1641 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1642 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1643 interconnect-names = "dma-mem", "read-1";
1644 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1645
1646 nvidia,outputs = <&sor0 &sor1>;
1647 nvidia,head = <2>;
1648 };
1649 };
1650
1651 dsia: dsi@15300000 {
1652 compatible = "nvidia,tegra186-dsi";
1653 reg = <0x15300000 0x10000>;
1654 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&bpmp TEGRA186_CLK_DSI>,
1656 <&bpmp TEGRA186_CLK_DSIA_LP>,
1657 <&bpmp TEGRA186_CLK_PLLD>;
1658 clock-names = "dsi", "lp", "parent";
1659 resets = <&bpmp TEGRA186_RESET_DSI>;
1660 reset-names = "dsi";
1661 status = "disabled";
1662
1663 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1664 };
1665
1666 vic@15340000 {
1667 compatible = "nvidia,tegra186-vic";
1668 reg = <0x15340000 0x40000>;
1669 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1670 clocks = <&bpmp TEGRA186_CLK_VIC>;
1671 clock-names = "vic";
1672 resets = <&bpmp TEGRA186_RESET_VIC>;
1673 reset-names = "vic";
1674
1675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1676 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1677 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1678 interconnect-names = "dma-mem", "write";
1679 iommus = <&smmu TEGRA186_SID_VIC>;
1680 };
1681
1682 nvjpg@15380000 {
1683 compatible = "nvidia,tegra186-nvjpg";
1684 reg = <0x15380000 0x40000>;
1685 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1686 clock-names = "nvjpg";
1687 resets = <&bpmp TEGRA186_RESET_NVJPG>;
1688 reset-names = "nvjpg";
1689
1690 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1691 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1692 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1693 interconnect-names = "dma-mem", "write";
1694 iommus = <&smmu TEGRA186_SID_NVJPG>;
1695 };
1696
1697 dsib: dsi@15400000 {
1698 compatible = "nvidia,tegra186-dsi";
1699 reg = <0x15400000 0x10000>;
1700 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1702 <&bpmp TEGRA186_CLK_DSIB_LP>,
1703 <&bpmp TEGRA186_CLK_PLLD>;
1704 clock-names = "dsi", "lp", "parent";
1705 resets = <&bpmp TEGRA186_RESET_DSIB>;
1706 reset-names = "dsi";
1707 status = "disabled";
1708
1709 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1710 };
1711
1712 nvdec@15480000 {
1713 compatible = "nvidia,tegra186-nvdec";
1714 reg = <0x15480000 0x40000>;
1715 clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1716 clock-names = "nvdec";
1717 resets = <&bpmp TEGRA186_RESET_NVDEC>;
1718 reset-names = "nvdec";
1719
1720 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1721 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1722 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1723 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1724 interconnect-names = "dma-mem", "read-1", "write";
1725 iommus = <&smmu TEGRA186_SID_NVDEC>;
1726 };
1727
1728 nvenc@154c0000 {
1729 compatible = "nvidia,tegra186-nvenc";
1730 reg = <0x154c0000 0x40000>;
1731 clocks = <&bpmp TEGRA186_CLK_NVENC>;
1732 clock-names = "nvenc";
1733 resets = <&bpmp TEGRA186_RESET_NVENC>;
1734 reset-names = "nvenc";
1735
1736 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1737 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1738 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1739 interconnect-names = "dma-mem", "write";
1740 iommus = <&smmu TEGRA186_SID_NVENC>;
1741 };
1742
1743 sor0: sor@15540000 {
1744 compatible = "nvidia,tegra186-sor";
1745 reg = <0x15540000 0x10000>;
1746 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1747 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1748 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1749 <&bpmp TEGRA186_CLK_PLLD2>,
1750 <&bpmp TEGRA186_CLK_PLLDP>,
1751 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1752 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1753 clock-names = "sor", "out", "parent", "dp", "safe",
1754 "pad";
1755 resets = <&bpmp TEGRA186_RESET_SOR0>;
1756 reset-names = "sor";
1757 pinctrl-0 = <&state_dpaux_aux>;
1758 pinctrl-1 = <&state_dpaux_i2c>;
1759 pinctrl-2 = <&state_dpaux_off>;
1760 pinctrl-names = "aux", "i2c", "off";
1761 status = "disabled";
1762
1763 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1764 nvidia,interface = <0>;
1765 };
1766
1767 sor1: sor@15580000 {
1768 compatible = "nvidia,tegra186-sor";
1769 reg = <0x15580000 0x10000>;
1770 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1771 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1772 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1773 <&bpmp TEGRA186_CLK_PLLD3>,
1774 <&bpmp TEGRA186_CLK_PLLDP>,
1775 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1776 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1777 clock-names = "sor", "out", "parent", "dp", "safe",
1778 "pad";
1779 resets = <&bpmp TEGRA186_RESET_SOR1>;
1780 reset-names = "sor";
1781 pinctrl-0 = <&state_dpaux1_aux>;
1782 pinctrl-1 = <&state_dpaux1_i2c>;
1783 pinctrl-2 = <&state_dpaux1_off>;
1784 pinctrl-names = "aux", "i2c", "off";
1785 status = "disabled";
1786
1787 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1788 nvidia,interface = <1>;
1789 };
1790
1791 dpaux: dpaux@155c0000 {
1792 compatible = "nvidia,tegra186-dpaux";
1793 reg = <0x155c0000 0x10000>;
1794 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1796 <&bpmp TEGRA186_CLK_PLLDP>;
1797 clock-names = "dpaux", "parent";
1798 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1799 reset-names = "dpaux";
1800 status = "disabled";
1801
1802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1803
1804 state_dpaux_aux: pinmux-aux {
1805 groups = "dpaux-io";
1806 function = "aux";
1807 };
1808
1809 state_dpaux_i2c: pinmux-i2c {
1810 groups = "dpaux-io";
1811 function = "i2c";
1812 };
1813
1814 state_dpaux_off: pinmux-off {
1815 groups = "dpaux-io";
1816 function = "off";
1817 };
1818
1819 i2c-bus {
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1822 };
1823 };
1824
1825 padctl@15880000 {
1826 compatible = "nvidia,tegra186-dsi-padctl";
1827 reg = <0x15880000 0x10000>;
1828 resets = <&bpmp TEGRA186_RESET_DSI>;
1829 reset-names = "dsi";
1830 status = "disabled";
1831 };
1832
1833 dsic: dsi@15900000 {
1834 compatible = "nvidia,tegra186-dsi";
1835 reg = <0x15900000 0x10000>;
1836 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1838 <&bpmp TEGRA186_CLK_DSIC_LP>,
1839 <&bpmp TEGRA186_CLK_PLLD>;
1840 clock-names = "dsi", "lp", "parent";
1841 resets = <&bpmp TEGRA186_RESET_DSIC>;
1842 reset-names = "dsi";
1843 status = "disabled";
1844
1845 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1846 };
1847
1848 dsid: dsi@15940000 {
1849 compatible = "nvidia,tegra186-dsi";
1850 reg = <0x15940000 0x10000>;
1851 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&bpmp TEGRA186_CLK_DSID>,
1853 <&bpmp TEGRA186_CLK_DSID_LP>,
1854 <&bpmp TEGRA186_CLK_PLLD>;
1855 clock-names = "dsi", "lp", "parent";
1856 resets = <&bpmp TEGRA186_RESET_DSID>;
1857 reset-names = "dsi";
1858 status = "disabled";
1859
1860 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1861 };
1862 };
1863
1864 gpu@17000000 {
1865 compatible = "nvidia,gp10b";
1866 reg = <0x0 0x17000000 0x0 0x1000000>,
1867 <0x0 0x18000000 0x0 0x1000000>;
1868 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1870 interrupt-names = "stall", "nonstall";
1871
1872 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1873 <&bpmp TEGRA186_CLK_GPU>;
1874 clock-names = "gpu", "pwr";
1875 resets = <&bpmp TEGRA186_RESET_GPU>;
1876 reset-names = "gpu";
1877 status = "disabled";
1878
1879 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1880 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1881 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1882 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1883 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1884 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1885 };
1886
1887 sram@30000000 {
1888 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1889 reg = <0x0 0x30000000 0x0 0x50000>;
1890 #address-cells = <1>;
1891 #size-cells = <1>;
1892 ranges = <0x0 0x0 0x30000000 0x50000>;
1893 no-memory-wc;
1894
1895 cpu_bpmp_tx: sram@4e000 {
1896 reg = <0x4e000 0x1000>;
1897 label = "cpu-bpmp-tx";
1898 pool;
1899 };
1900
1901 cpu_bpmp_rx: sram@4f000 {
1902 reg = <0x4f000 0x1000>;
1903 label = "cpu-bpmp-rx";
1904 pool;
1905 };
1906 };
1907
1908 bpmp: bpmp {
1909 compatible = "nvidia,tegra186-bpmp";
1910 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1911 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1912 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1913 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1914 interconnect-names = "read", "write", "dma-mem", "dma-write";
1915 iommus = <&smmu TEGRA186_SID_BPMP>;
1916 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1917 TEGRA_HSP_DB_MASTER_BPMP>;
1918 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1919 #clock-cells = <1>;
1920 #reset-cells = <1>;
1921 #power-domain-cells = <1>;
1922
1923 bpmp_i2c: i2c {
1924 compatible = "nvidia,tegra186-bpmp-i2c";
1925 nvidia,bpmp-bus-id = <5>;
1926 #address-cells = <1>;
1927 #size-cells = <0>;
1928 status = "disabled";
1929 };
1930
1931 bpmp_thermal: thermal {
1932 compatible = "nvidia,tegra186-bpmp-thermal";
1933 #thermal-sensor-cells = <1>;
1934 };
1935 };
1936
1937 cpus {
1938 #address-cells = <1>;
1939 #size-cells = <0>;
1940
1941 denver_0: cpu@0 {
1942 compatible = "nvidia,tegra186-denver";
1943 device_type = "cpu";
1944 i-cache-size = <0x20000>;
1945 i-cache-line-size = <64>;
1946 i-cache-sets = <512>;
1947 d-cache-size = <0x10000>;
1948 d-cache-line-size = <64>;
1949 d-cache-sets = <256>;
1950 next-level-cache = <&L2_DENVER>;
1951 reg = <0x000>;
1952 };
1953
1954 denver_1: cpu@1 {
1955 compatible = "nvidia,tegra186-denver";
1956 device_type = "cpu";
1957 i-cache-size = <0x20000>;
1958 i-cache-line-size = <64>;
1959 i-cache-sets = <512>;
1960 d-cache-size = <0x10000>;
1961 d-cache-line-size = <64>;
1962 d-cache-sets = <256>;
1963 next-level-cache = <&L2_DENVER>;
1964 reg = <0x001>;
1965 };
1966
1967 ca57_0: cpu@2 {
1968 compatible = "arm,cortex-a57";
1969 device_type = "cpu";
1970 i-cache-size = <0xC000>;
1971 i-cache-line-size = <64>;
1972 i-cache-sets = <256>;
1973 d-cache-size = <0x8000>;
1974 d-cache-line-size = <64>;
1975 d-cache-sets = <256>;
1976 next-level-cache = <&L2_A57>;
1977 reg = <0x100>;
1978 };
1979
1980 ca57_1: cpu@3 {
1981 compatible = "arm,cortex-a57";
1982 device_type = "cpu";
1983 i-cache-size = <0xC000>;
1984 i-cache-line-size = <64>;
1985 i-cache-sets = <256>;
1986 d-cache-size = <0x8000>;
1987 d-cache-line-size = <64>;
1988 d-cache-sets = <256>;
1989 next-level-cache = <&L2_A57>;
1990 reg = <0x101>;
1991 };
1992
1993 ca57_2: cpu@4 {
1994 compatible = "arm,cortex-a57";
1995 device_type = "cpu";
1996 i-cache-size = <0xC000>;
1997 i-cache-line-size = <64>;
1998 i-cache-sets = <256>;
1999 d-cache-size = <0x8000>;
2000 d-cache-line-size = <64>;
2001 d-cache-sets = <256>;
2002 next-level-cache = <&L2_A57>;
2003 reg = <0x102>;
2004 };
2005
2006 ca57_3: cpu@5 {
2007 compatible = "arm,cortex-a57";
2008 device_type = "cpu";
2009 i-cache-size = <0xC000>;
2010 i-cache-line-size = <64>;
2011 i-cache-sets = <256>;
2012 d-cache-size = <0x8000>;
2013 d-cache-line-size = <64>;
2014 d-cache-sets = <256>;
2015 next-level-cache = <&L2_A57>;
2016 reg = <0x103>;
2017 };
2018
2019 L2_DENVER: l2-cache0 {
2020 compatible = "cache";
2021 cache-unified;
2022 cache-level = <2>;
2023 cache-size = <0x200000>;
2024 cache-line-size = <64>;
2025 cache-sets = <2048>;
2026 };
2027
2028 L2_A57: l2-cache1 {
2029 compatible = "cache";
2030 cache-unified;
2031 cache-level = <2>;
2032 cache-size = <0x200000>;
2033 cache-line-size = <64>;
2034 cache-sets = <2048>;
2035 };
2036 };
2037
2038 pmu-a57 {
2039 compatible = "arm,cortex-a57-pmu";
2040 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2044 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2045 };
2046
2047 pmu-denver {
2048 compatible = "nvidia,denver-pmu";
2049 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2051 interrupt-affinity = <&denver_0 &denver_1>;
2052 };
2053
2054 sound {
2055 status = "disabled";
2056
2057 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2058 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2059 clock-names = "pll_a", "plla_out0";
2060 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2061 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2062 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2063 assigned-clock-parents = <0>,
2064 <&bpmp TEGRA186_CLK_PLLA>,
2065 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2066 /*
2067 * PLLA supports dynamic ramp. Below initial rate is chosen
2068 * for this to work and oscillate between base rates required
2069 * for 8x and 11.025x sample rate streams.
2070 */
2071 assigned-clock-rates = <258000000>;
2072
2073 iommus = <&smmu TEGRA186_SID_APE>;
2074 };
2075
2076 thermal-zones {
2077 /* Cortex-A57 cluster */
2078 cpu-thermal {
2079 polling-delay = <0>;
2080 polling-delay-passive = <1000>;
2081
2082 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2083
2084 trips {
2085 critical {
2086 temperature = <101000>;
2087 hysteresis = <0>;
2088 type = "critical";
2089 };
2090 };
2091
2092 cooling-maps {
2093 };
2094 };
2095
2096 /* Denver cluster */
2097 aux-thermal {
2098 polling-delay = <0>;
2099 polling-delay-passive = <1000>;
2100
2101 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2102
2103 trips {
2104 critical {
2105 temperature = <101000>;
2106 hysteresis = <0>;
2107 type = "critical";
2108 };
2109 };
2110
2111 cooling-maps {
2112 };
2113 };
2114
2115 gpu-thermal {
2116 polling-delay = <0>;
2117 polling-delay-passive = <1000>;
2118
2119 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2120
2121 trips {
2122 critical {
2123 temperature = <101000>;
2124 hysteresis = <0>;
2125 type = "critical";
2126 };
2127 };
2128
2129 cooling-maps {
2130 };
2131 };
2132
2133 pll-thermal {
2134 polling-delay = <0>;
2135 polling-delay-passive = <1000>;
2136
2137 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2138
2139 trips {
2140 critical {
2141 temperature = <101000>;
2142 hysteresis = <0>;
2143 type = "critical";
2144 };
2145 };
2146
2147 cooling-maps {
2148 };
2149 };
2150
2151 ao-thermal {
2152 polling-delay = <0>;
2153 polling-delay-passive = <1000>;
2154
2155 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2156
2157 trips {
2158 critical {
2159 temperature = <101000>;
2160 hysteresis = <0>;
2161 type = "critical";
2162 };
2163 };
2164
2165 cooling-maps {
2166 };
2167 };
2168 };
2169
2170 timer {
2171 compatible = "arm,armv8-timer";
2172 interrupts = <GIC_PPI 13
2173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2174 <GIC_PPI 14
2175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2176 <GIC_PPI 11
2177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2178 <GIC_PPI 10
2179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2180 interrupt-parent = <&gic>;
2181 always-on;
2182 };
2183 };
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