1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/mfd/max77620.h> 3 4 #include "tegra210.dtsi" 5 6 / { 7 model = "NVIDIA Jetson TX1"; 8 compatible = "nvidia,p2180", "nvidia,tegra210"; 9 10 aliases { 11 rtc0 = "/i2c@7000d000/pmic@3c"; 12 rtc1 = "/rtc@7000e000"; 13 serial0 = &uarta; 14 }; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 memory@80000000 { 21 device_type = "memory"; 22 reg = <0x0 0x80000000 0x1 0x0>; 23 }; 24 25 gpu@57000000 { 26 vdd-supply = <&vdd_gpu>; 27 }; 28 29 /* debug port */ 30 serial@70006000 { 31 /delete-property/ dmas; 32 /delete-property/ dma-names; 33 status = "okay"; 34 }; 35 36 serial@70006300 { 37 /delete-property/ reg-shift; 38 status = "okay"; 39 compatible = "nvidia,tegra30-hsuart"; 40 reset-names = "serial"; 41 42 bluetooth { 43 compatible = "brcm,bcm43540-bt"; 44 device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; 45 shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; 46 interrupt-parent = <&gpio>; 47 interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW>; 48 interrupt-names = "host-wakeup"; 49 }; 50 }; 51 52 i2c@7000c400 { 53 status = "okay"; 54 55 power-sensor@40 { 56 compatible = "ti,ina3221"; 57 reg = <0x40>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 input@0 { 62 reg = <0x0>; 63 label = "VDD_IN"; 64 shunt-resistor-micro-ohms = <20000>; 65 }; 66 67 input@1 { 68 reg = <0x1>; 69 label = "VDD_GPU"; 70 shunt-resistor-micro-ohms = <10000>; 71 }; 72 73 input@2 { 74 reg = <0x2>; 75 label = "VDD_CPU"; 76 shunt-resistor-micro-ohms = <10000>; 77 }; 78 }; 79 }; 80 81 i2c@7000c500 { 82 status = "okay"; 83 84 /* module ID EEPROM */ 85 eeprom@50 { 86 compatible = "atmel,24c02"; 87 reg = <0x50>; 88 89 label = "module"; 90 vcc-supply = <&vdd_1v8>; 91 address-width = <8>; 92 pagesize = <8>; 93 size = <256>; 94 read-only; 95 }; 96 }; 97 98 i2c@7000d000 { 99 status = "okay"; 100 clock-frequency = <400000>; 101 102 pmic: pmic@3c { 103 compatible = "maxim,max77620"; 104 reg = <0x3c>; 105 interrupt-parent = <&tegra_pmc>; 106 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 107 108 #interrupt-cells = <2>; 109 interrupt-controller; 110 111 #gpio-cells = <2>; 112 gpio-controller; 113 114 pinctrl-names = "default"; 115 pinctrl-0 = <&max77620_default>; 116 117 fps { 118 fps0 { 119 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 120 maxim,suspend-fps-time-period-us = <1280>; 121 }; 122 123 fps1 { 124 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 125 maxim,suspend-fps-time-period-us = <1280>; 126 }; 127 128 fps2 { 129 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 130 }; 131 }; 132 133 max77620_default: pinmux { 134 gpio0 { 135 pins = "gpio0"; 136 function = "gpio"; 137 }; 138 139 gpio1 { 140 pins = "gpio1"; 141 function = "fps-out"; 142 drive-push-pull = <1>; 143 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 144 maxim,active-fps-power-up-slot = <7>; 145 maxim,active-fps-power-down-slot = <0>; 146 }; 147 148 gpio2_3 { 149 pins = "gpio2", "gpio3"; 150 function = "fps-out"; 151 drive-open-drain = <1>; 152 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 153 }; 154 155 gpio4 { 156 pins = "gpio4"; 157 function = "32k-out1"; 158 }; 159 160 gpio5_6_7 { 161 pins = "gpio5", "gpio6", "gpio7"; 162 function = "gpio"; 163 drive-push-pull = <1>; 164 }; 165 }; 166 167 regulators { 168 in-ldo0-1-supply = <&vdd_pre>; 169 in-ldo7-8-supply = <&vdd_pre>; 170 in-sd3-supply = <&vdd_5v0_sys>; 171 172 vdd_soc: sd0 { 173 regulator-name = "VDD_SOC"; 174 regulator-min-microvolt = <600000>; 175 regulator-max-microvolt = <1400000>; 176 regulator-always-on; 177 regulator-boot-on; 178 179 regulator-enable-ramp-delay = <146>; 180 regulator-ramp-delay = <27500>; 181 182 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 183 }; 184 185 vdd_ddr: sd1 { 186 regulator-name = "VDD_DDR_1V1_PMIC"; 187 regulator-always-on; 188 regulator-boot-on; 189 190 regulator-enable-ramp-delay = <130>; 191 regulator-ramp-delay = <27500>; 192 193 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 194 }; 195 196 vdd_pre: sd2 { 197 regulator-name = "VDD_PRE_REG_1V35"; 198 regulator-min-microvolt = <1350000>; 199 regulator-max-microvolt = <1350000>; 200 201 regulator-enable-ramp-delay = <176>; 202 regulator-ramp-delay = <27500>; 203 204 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 205 }; 206 207 vdd_1v8: sd3 { 208 regulator-name = "VDD_1V8"; 209 regulator-min-microvolt = <1800000>; 210 regulator-max-microvolt = <1800000>; 211 regulator-always-on; 212 regulator-boot-on; 213 214 regulator-enable-ramp-delay = <242>; 215 regulator-ramp-delay = <27500>; 216 217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 218 }; 219 220 vdd_sys_1v2: ldo0 { 221 regulator-name = "AVDD_SYS_1V2"; 222 regulator-min-microvolt = <1200000>; 223 regulator-max-microvolt = <1200000>; 224 regulator-always-on; 225 regulator-boot-on; 226 227 regulator-enable-ramp-delay = <26>; 228 regulator-ramp-delay = <100000>; 229 230 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 231 }; 232 233 vdd_pex_1v05: ldo1 { 234 regulator-name = "VDD_PEX_1V05"; 235 regulator-min-microvolt = <1050000>; 236 regulator-max-microvolt = <1050000>; 237 238 regulator-enable-ramp-delay = <22>; 239 regulator-ramp-delay = <100000>; 240 241 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 242 }; 243 244 vddio_sdmmc: ldo2 { 245 regulator-name = "VDDIO_SDMMC"; 246 regulator-min-microvolt = <1800000>; 247 regulator-max-microvolt = <3300000>; 248 regulator-always-on; 249 regulator-boot-on; 250 251 regulator-enable-ramp-delay = <62>; 252 regulator-ramp-delay = <100000>; 253 254 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 255 }; 256 257 vdd_cam_hv: ldo3 { 258 regulator-name = "VDD_CAM_HV"; 259 regulator-min-microvolt = <2800000>; 260 regulator-max-microvolt = <2800000>; 261 262 regulator-enable-ramp-delay = <50>; 263 regulator-ramp-delay = <100000>; 264 265 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 266 }; 267 268 vdd_rtc: ldo4 { 269 regulator-name = "VDD_RTC"; 270 regulator-min-microvolt = <850000>; 271 regulator-max-microvolt = <850000>; 272 regulator-always-on; 273 regulator-boot-on; 274 275 regulator-enable-ramp-delay = <22>; 276 regulator-ramp-delay = <100000>; 277 278 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 279 }; 280 281 vdd_ts_hv: ldo5 { 282 regulator-name = "VDD_TS_HV"; 283 regulator-min-microvolt = <3300000>; 284 regulator-max-microvolt = <3300000>; 285 286 regulator-enable-ramp-delay = <62>; 287 regulator-ramp-delay = <100000>; 288 289 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 290 }; 291 292 vdd_ts: ldo6 { 293 regulator-name = "VDD_TS_1V8"; 294 regulator-min-microvolt = <1800000>; 295 regulator-max-microvolt = <1800000>; 296 297 regulator-enable-ramp-delay = <36>; 298 regulator-ramp-delay = <100000>; 299 300 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 301 maxim,active-fps-power-up-slot = <7>; 302 maxim,active-fps-power-down-slot = <0>; 303 }; 304 305 avdd_1v05_pll: ldo7 { 306 regulator-name = "AVDD_1V05_PLL"; 307 regulator-min-microvolt = <1050000>; 308 regulator-max-microvolt = <1050000>; 309 regulator-always-on; 310 regulator-boot-on; 311 312 regulator-enable-ramp-delay = <24>; 313 regulator-ramp-delay = <100000>; 314 315 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 316 }; 317 318 avdd_1v05: ldo8 { 319 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 320 regulator-min-microvolt = <1050000>; 321 regulator-max-microvolt = <1050000>; 322 323 regulator-enable-ramp-delay = <22>; 324 regulator-ramp-delay = <100000>; 325 326 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 327 }; 328 }; 329 }; 330 }; 331 332 pmc@7000e400 { 333 nvidia,invert-interrupt; 334 nvidia,suspend-mode = <0>; 335 nvidia,cpu-pwr-good-time = <0>; 336 nvidia,cpu-pwr-off-time = <0>; 337 nvidia,core-pwr-good-time = <4587 3876>; 338 nvidia,core-pwr-off-time = <39065>; 339 nvidia,core-power-req-active-high; 340 nvidia,sys-clock-req-active-high; 341 }; 342 343 mmc@700b0200 { 344 status = "okay"; 345 bus-width = <4>; 346 non-removable; 347 power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 348 vqmmc-supply = <&vdd_1v8>; 349 vmmc-supply = <&vdd_3v3_sys>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 wifi@1 { 354 compatible = "brcm,bcm4354-fmac"; 355 reg = <1>; 356 interrupt-parent = <&gpio>; 357 interrupts = <TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-names = "host-wake"; 359 }; 360 }; 361 362 /* eMMC */ 363 mmc@700b0600 { 364 status = "okay"; 365 bus-width = <8>; 366 non-removable; 367 vqmmc-supply = <&vdd_1v8>; 368 }; 369 370 clk32k_in: clock-32k { 371 compatible = "fixed-clock"; 372 clock-frequency = <32768>; 373 #clock-cells = <0>; 374 }; 375 376 cpus { 377 cpu@0 { 378 enable-method = "psci"; 379 }; 380 381 cpu@1 { 382 enable-method = "psci"; 383 }; 384 385 cpu@2 { 386 enable-method = "psci"; 387 }; 388 389 cpu@3 { 390 enable-method = "psci"; 391 }; 392 393 idle-states { 394 cpu-sleep { 395 status = "okay"; 396 }; 397 }; 398 }; 399 400 psci { 401 compatible = "arm,psci-0.2"; 402 method = "smc"; 403 }; 404 405 vdd_gpu: regulator-vdd-gpu { 406 compatible = "pwm-regulator"; 407 pwms = <&pwm 1 8000>; 408 regulator-name = "VDD_GPU"; 409 regulator-min-microvolt = <710000>; 410 regulator-max-microvolt = <1320000>; 411 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 412 regulator-ramp-delay = <80>; 413 regulator-enable-ramp-delay = <2000>; 414 regulator-settling-time-us = <160>; 415 }; 416 };
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