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Linux/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts

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  1 // SPDX-License-Identifier: BSD-3-Clause
  2 /*
  3  * IPQ5332 RDP442 board device tree source
  4  *
  5  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  6  */
  7 
  8 /dts-v1/;
  9 
 10 #include "ipq5332-rdp-common.dtsi"
 11 
 12 / {
 13         model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
 14         compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
 15 };
 16 
 17 &blsp1_i2c1 {
 18         clock-frequency = <400000>;
 19         pinctrl-0 = <&i2c_1_pins>;
 20         pinctrl-names = "default";
 21         status = "okay";
 22 };
 23 
 24 &blsp1_spi0 {
 25         pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
 26         pinctrl-names = "default";
 27         status = "okay";
 28 
 29         flash@0 {
 30                 compatible = "micron,n25q128a11", "jedec,spi-nor";
 31                 reg = <0>;
 32                 #address-cells = <1>;
 33                 #size-cells = <1>;
 34                 spi-max-frequency = <50000000>;
 35         };
 36 };
 37 
 38 &sdhc {
 39         bus-width = <4>;
 40         max-frequency = <192000000>;
 41         mmc-ddr-1_8v;
 42         mmc-hs200-1_8v;
 43         non-removable;
 44         pinctrl-0 = <&sdc_default_state>;
 45         pinctrl-names = "default";
 46         status = "okay";
 47 };
 48 
 49 &tlmm {
 50         i2c_1_pins: i2c-1-state {
 51                 pins = "gpio29", "gpio30";
 52                 function = "blsp1_i2c0";
 53                 drive-strength = <8>;
 54                 bias-pull-up;
 55         };
 56 
 57         sdc_default_state: sdc-default-state {
 58                 clk-pins {
 59                         pins = "gpio13";
 60                         function = "sdc_clk";
 61                         drive-strength = <8>;
 62                         bias-disable;
 63                 };
 64 
 65                 cmd-pins {
 66                         pins = "gpio12";
 67                         function = "sdc_cmd";
 68                         drive-strength = <8>;
 69                         bias-pull-up;
 70                 };
 71 
 72                 data-pins {
 73                         pins = "gpio8", "gpio9", "gpio10", "gpio11";
 74                         function = "sdc_data";
 75                         drive-strength = <8>;
 76                         bias-pull-up;
 77                 };
 78         };
 79 
 80         spi_0_data_clk_pins: spi-0-data-clk-state {
 81                 pins = "gpio14", "gpio15", "gpio16";
 82                 function = "blsp0_spi";
 83                 drive-strength = <2>;
 84                 bias-pull-down;
 85         };
 86 
 87         spi_0_cs_pins: spi-0-cs-state {
 88                 pins = "gpio17";
 89                 function = "blsp0_spi";
 90                 drive-strength = <2>;
 91                 bias-pull-up;
 92         };
 93 };

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