1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * IPQ5332 device tree source
4 *
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11
12 / {
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 clocks {
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 };
22
23 xo_board: xo-board-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 };
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 CPU0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53";
36 reg = <0x0>;
37 enable-method = "psci";
38 next-level-cache = <&L2_0>;
39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
40 operating-points-v2 = <&cpu_opp_table>;
41 };
42
43 CPU1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a53";
46 reg = <0x1>;
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
50 operating-points-v2 = <&cpu_opp_table>;
51 };
52
53 CPU2: cpu@2 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a53";
56 reg = <0x2>;
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
60 operating-points-v2 = <&cpu_opp_table>;
61 };
62
63 CPU3: cpu@3 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 reg = <0x3>;
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 operating-points-v2 = <&cpu_opp_table>;
71 };
72
73 L2_0: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 cache-unified;
77 };
78 };
79
80 firmware {
81 scm {
82 compatible = "qcom,scm-ipq5332", "qcom,scm";
83 qcom,dload-mode = <&tcsr 0x6100>;
84 };
85 };
86
87 memory@40000000 {
88 device_type = "memory";
89 /* We expect the bootloader to fill in the size */
90 reg = <0x0 0x40000000 0x0 0x0>;
91 };
92
93 cpu_opp_table: opp-table-cpu {
94 compatible = "operating-points-v2-kryo-cpu";
95 opp-shared;
96 nvmem-cells = <&cpu_speed_bin>;
97
98 opp-1100000000 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-supported-hw = <0x7>;
101 clock-latency-ns = <200000>;
102 };
103
104 opp-1500000000 {
105 opp-hz = /bits/ 64 <1500000000>;
106 opp-supported-hw = <0x3>;
107 clock-latency-ns = <200000>;
108 };
109 };
110
111 pmu {
112 compatible = "arm,cortex-a53-pmu";
113 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
114 };
115
116 psci {
117 compatible = "arm,psci-1.0";
118 method = "smc";
119 };
120
121 reserved-memory {
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
125
126 bootloader@4a100000 {
127 reg = <0x0 0x4a100000 0x0 0x400000>;
128 no-map;
129 };
130
131 sbl@4a500000 {
132 reg = <0x0 0x4a500000 0x0 0x100000>;
133 no-map;
134 };
135
136 tz_mem: tz@4a600000 {
137 reg = <0x0 0x4a600000 0x0 0x200000>;
138 no-map;
139 };
140
141 smem@4a800000 {
142 compatible = "qcom,smem";
143 reg = <0x0 0x4a800000 0x0 0x100000>;
144 no-map;
145
146 hwlocks = <&tcsr_mutex 3>;
147 };
148 };
149
150 soc@0 {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0 0 0 0xffffffff>;
155
156 usbphy0: phy@7b000 {
157 compatible = "qcom,ipq5332-usb-hsphy";
158 reg = <0x0007b000 0x12c>;
159
160 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
161
162 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
163
164 #phy-cells = <0>;
165
166 status = "disabled";
167 };
168
169 qfprom: efuse@a4000 {
170 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
171 reg = <0x000a4000 0x721>;
172 #address-cells = <1>;
173 #size-cells = <1>;
174
175 cpu_speed_bin: cpu-speed-bin@1d {
176 reg = <0x1d 0x2>;
177 bits = <7 2>;
178 };
179 };
180
181 rng: rng@e3000 {
182 compatible = "qcom,prng-ee";
183 reg = <0x000e3000 0x1000>;
184 clocks = <&gcc GCC_PRNG_AHB_CLK>;
185 clock-names = "core";
186 };
187
188 tlmm: pinctrl@1000000 {
189 compatible = "qcom,ipq5332-tlmm";
190 reg = <0x01000000 0x300000>;
191 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
192 gpio-controller;
193 #gpio-cells = <2>;
194 gpio-ranges = <&tlmm 0 0 53>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197
198 serial_0_pins: serial0-state {
199 pins = "gpio18", "gpio19";
200 function = "blsp0_uart0";
201 drive-strength = <8>;
202 bias-pull-up;
203 };
204 };
205
206 gcc: clock-controller@1800000 {
207 compatible = "qcom,ipq5332-gcc";
208 reg = <0x01800000 0x80000>;
209 #clock-cells = <1>;
210 #reset-cells = <1>;
211 clocks = <&xo_board>,
212 <&sleep_clk>,
213 <0>,
214 <0>,
215 <0>;
216 };
217
218 tcsr_mutex: hwlock@1905000 {
219 compatible = "qcom,tcsr-mutex";
220 reg = <0x01905000 0x20000>;
221 #hwlock-cells = <1>;
222 };
223
224 tcsr: syscon@1937000 {
225 compatible = "qcom,tcsr-ipq5332", "syscon";
226 reg = <0x01937000 0x21000>;
227 };
228
229 sdhc: mmc@7804000 {
230 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
231 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
232
233 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "hc_irq", "pwr_irq";
236
237 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
238 <&gcc GCC_SDCC1_APPS_CLK>,
239 <&xo_board>;
240 clock-names = "iface", "core", "xo";
241 status = "disabled";
242 };
243
244 blsp_dma: dma-controller@7884000 {
245 compatible = "qcom,bam-v1.7.0";
246 reg = <0x07884000 0x1d000>;
247 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
249 clock-names = "bam_clk";
250 #dma-cells = <1>;
251 qcom,ee = <0>;
252 };
253
254 blsp1_uart0: serial@78af000 {
255 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
256 reg = <0x078af000 0x200>;
257 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
259 <&gcc GCC_BLSP1_AHB_CLK>;
260 clock-names = "core", "iface";
261 status = "disabled";
262 };
263
264 blsp1_uart1: serial@78b0000 {
265 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
266 reg = <0x078b0000 0x200>;
267 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
269 <&gcc GCC_BLSP1_AHB_CLK>;
270 clock-names = "core", "iface";
271 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
272 dma-names = "tx", "rx";
273 status = "disabled";
274 };
275
276 blsp1_spi0: spi@78b5000 {
277 compatible = "qcom,spi-qup-v2.2.1";
278 reg = <0x078b5000 0x600>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
283 <&gcc GCC_BLSP1_AHB_CLK>;
284 clock-names = "core", "iface";
285 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
286 dma-names = "tx", "rx";
287 status = "disabled";
288 };
289
290 blsp1_i2c1: i2c@78b6000 {
291 compatible = "qcom,i2c-qup-v2.2.1";
292 reg = <0x078b6000 0x600>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
297 <&gcc GCC_BLSP1_AHB_CLK>;
298 clock-names = "core", "iface";
299 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
300 dma-names = "tx", "rx";
301 status = "disabled";
302 };
303
304 blsp1_spi2: spi@78b7000 {
305 compatible = "qcom,spi-qup-v2.2.1";
306 reg = <0x078b7000 0x600>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
311 <&gcc GCC_BLSP1_AHB_CLK>;
312 clock-names = "core", "iface";
313 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
314 dma-names = "tx", "rx";
315 status = "disabled";
316 };
317
318 usb: usb@8af8800 {
319 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
320 reg = <0x08af8800 0x400>;
321
322 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "pwr_event",
326 "dp_hs_phy_irq",
327 "dm_hs_phy_irq";
328
329 clocks = <&gcc GCC_USB0_MASTER_CLK>,
330 <&gcc GCC_SNOC_USB_CLK>,
331 <&gcc GCC_USB0_SLEEP_CLK>,
332 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
333 clock-names = "core",
334 "iface",
335 "sleep",
336 "mock_utmi";
337
338 resets = <&gcc GCC_USB_BCR>;
339
340 qcom,select-utmi-as-pipe-clk;
341
342 #address-cells = <1>;
343 #size-cells = <1>;
344 ranges;
345
346 status = "disabled";
347
348 usb_dwc: usb@8a00000 {
349 compatible = "snps,dwc3";
350 reg = <0x08a00000 0xe000>;
351 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
352 clock-names = "ref";
353 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
354 phy-names = "usb2-phy";
355 phys = <&usbphy0>;
356 tx-fifo-resize;
357 snps,is-utmi-l1-suspend;
358 snps,hird-threshold = /bits/ 8 <0x0>;
359 snps,dis_u2_susphy_quirk;
360 snps,dis_u3_susphy_quirk;
361 };
362 };
363
364 intc: interrupt-controller@b000000 {
365 compatible = "qcom,msm-qgic2";
366 reg = <0x0b000000 0x1000>, /* GICD */
367 <0x0b002000 0x1000>, /* GICC */
368 <0x0b001000 0x1000>, /* GICH */
369 <0x0b004000 0x1000>; /* GICV */
370 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <3>;
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges = <0 0x0b00c000 0x3000>;
376
377 v2m0: v2m@0 {
378 compatible = "arm,gic-v2m-frame";
379 reg = <0x00000000 0xffd>;
380 msi-controller;
381 };
382
383 v2m1: v2m@1000 {
384 compatible = "arm,gic-v2m-frame";
385 reg = <0x00001000 0xffd>;
386 msi-controller;
387 };
388
389 v2m2: v2m@2000 {
390 compatible = "arm,gic-v2m-frame";
391 reg = <0x00002000 0xffd>;
392 msi-controller;
393 };
394 };
395
396 watchdog: watchdog@b017000 {
397 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
398 reg = <0x0b017000 0x1000>;
399 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
400 clocks = <&sleep_clk>;
401 timeout-sec = <30>;
402 };
403
404 apcs_glb: mailbox@b111000 {
405 compatible = "qcom,ipq5332-apcs-apps-global",
406 "qcom,ipq6018-apcs-apps-global";
407 reg = <0x0b111000 0x1000>;
408 #clock-cells = <1>;
409 clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
410 clock-names = "pll", "xo", "gpll0";
411 #mbox-cells = <1>;
412 };
413
414 a53pll: clock@b116000 {
415 compatible = "qcom,ipq5332-a53pll";
416 reg = <0x0b116000 0x40>;
417 #clock-cells = <0>;
418 clocks = <&xo_board>;
419 clock-names = "xo";
420 };
421
422 timer@b120000 {
423 compatible = "arm,armv7-timer-mem";
424 reg = <0x0b120000 0x1000>;
425 #address-cells = <1>;
426 #size-cells = <1>;
427 ranges;
428
429 frame@b120000 {
430 reg = <0x0b121000 0x1000>,
431 <0x0b122000 0x1000>;
432 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
434 frame-number = <0>;
435 };
436
437 frame@b123000 {
438 reg = <0x0b123000 0x1000>;
439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
440 frame-number = <1>;
441 status = "disabled";
442 };
443
444 frame@b124000 {
445 reg = <0x0b124000 0x1000>;
446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
447 frame-number = <2>;
448 status = "disabled";
449 };
450
451 frame@b125000 {
452 reg = <0x0b125000 0x1000>;
453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
454 frame-number = <3>;
455 status = "disabled";
456 };
457
458 frame@b126000 {
459 reg = <0x0b126000 0x1000>;
460 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
461 frame-number = <4>;
462 status = "disabled";
463 };
464
465 frame@b127000 {
466 reg = <0x0b127000 0x1000>;
467 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
468 frame-number = <5>;
469 status = "disabled";
470 };
471
472 frame@b128000 {
473 reg = <0x0b128000 0x1000>;
474 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
475 frame-number = <6>;
476 status = "disabled";
477 };
478 };
479 };
480
481 timer {
482 compatible = "arm,armv8-timer";
483 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
484 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
485 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
486 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
487 };
488 };
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