1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
8
9 / {
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>;
16
17 clocks {
18 sleep_clk: sleep_clk {
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
22 };
23
24 xo: xo {
25 compatible = "fixed-clock";
26 clock-frequency = <19200000>;
27 #clock-cells = <0>;
28 };
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 CPU0: cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
38 reg = <0x0>;
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
41 };
42
43 CPU1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a53";
46 enable-method = "psci";
47 reg = <0x1>;
48 next-level-cache = <&L2_0>;
49 };
50
51 CPU2: cpu@2 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 reg = <0x2>;
56 next-level-cache = <&L2_0>;
57 };
58
59 CPU3: cpu@3 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 reg = <0x3>;
64 next-level-cache = <&L2_0>;
65 };
66
67 L2_0: l2-cache {
68 compatible = "cache";
69 cache-level = <2>;
70 cache-unified;
71 };
72 };
73
74 pmu {
75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 };
78
79 psci {
80 compatible = "arm,psci-1.0";
81 method = "smc";
82 };
83
84 reserved-memory {
85 #address-cells = <2>;
86 #size-cells = <2>;
87 ranges;
88
89 bootloader@4a600000 {
90 reg = <0x0 0x4a600000 0x0 0x400000>;
91 no-map;
92 };
93
94 sbl@4aa00000 {
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
96 no-map;
97 };
98
99 smem@4ab00000 {
100 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 0x0 0x100000>;
102 no-map;
103
104 hwlocks = <&tcsr_mutex 3>;
105 };
106
107 memory@4ac00000 {
108 reg = <0x0 0x4ac00000 0x0 0x400000>;
109 no-map;
110 };
111 };
112
113 firmware {
114 scm {
115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tcsr 0x6100>;
117 };
118 };
119
120 soc: soc@0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus";
125
126 ssphy_1: phy@58000 {
127 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x1000>;
129
130 clocks = <&gcc GCC_USB1_AUX_CLK>,
131 <&xo>,
132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB1_PIPE_CLK>;
134 clock-names = "aux",
135 "ref",
136 "cfg_ahb",
137 "pipe";
138 clock-output-names = "usb3phy_1_cc_pipe_clk";
139 #clock-cells = <0>;
140 #phy-cells = <0>;
141
142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy",
145 "phy_phy";
146
147 status = "disabled";
148 };
149
150 qusb_phy_1: phy@59000 {
151 compatible = "qcom,ipq8074-qusb2-phy";
152 reg = <0x00059000 0x180>;
153 #phy-cells = <0>;
154
155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
156 <&xo>;
157 clock-names = "cfg_ahb", "ref";
158
159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
160 status = "disabled";
161 };
162
163 ssphy_0: phy@78000 {
164 compatible = "qcom,ipq8074-qmp-usb3-phy";
165 reg = <0x00078000 0x1000>;
166
167 clocks = <&gcc GCC_USB0_AUX_CLK>,
168 <&xo>,
169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
170 <&gcc GCC_USB0_PIPE_CLK>;
171 clock-names = "aux",
172 "ref",
173 "cfg_ahb",
174 "pipe";
175 clock-output-names = "usb3phy_0_cc_pipe_clk";
176 #clock-cells = <0>;
177 #phy-cells = <0>;
178
179 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy",
182 "phy_phy";
183
184 status = "disabled";
185 };
186
187 qusb_phy_0: phy@79000 {
188 compatible = "qcom,ipq8074-qusb2-phy";
189 reg = <0x00079000 0x180>;
190 #phy-cells = <0>;
191
192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
193 <&xo>;
194 clock-names = "cfg_ahb", "ref";
195
196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
197 status = "disabled";
198 };
199
200 pcie_qmp0: phy@84000 {
201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
202 reg = <0x00084000 0x1000>;
203
204 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCIE0_PIPE_CLK>;
207 clock-names = "aux",
208 "cfg_ahb",
209 "pipe";
210
211 clock-output-names = "pcie20_phy0_pipe_clk";
212 #clock-cells = <0>;
213
214 #phy-cells = <0>;
215
216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy",
219 "common";
220 status = "disabled";
221 };
222
223 pcie_qmp1: phy@8e000 {
224 compatible = "qcom,ipq8074-qmp-pcie-phy";
225 reg = <0x0008e000 0x1000>;
226
227 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCIE1_PIPE_CLK>;
230 clock-names = "aux",
231 "cfg_ahb",
232 "pipe";
233
234 clock-output-names = "pcie20_phy1_pipe_clk";
235 #clock-cells = <0>;
236
237 #phy-cells = <0>;
238
239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy",
242 "common";
243 status = "disabled";
244 };
245
246 mdio: mdio@90000 {
247 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
248 reg = <0x00090000 0x64>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251
252 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdio_ahb_clk";
254
255 clock-frequency = <6250000>;
256
257 status = "disabled";
258 };
259
260 qfprom: efuse@a4000 {
261 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
262 reg = <0x000a4000 0x2000>;
263 #address-cells = <1>;
264 #size-cells = <1>;
265 };
266
267 prng: rng@e3000 {
268 compatible = "qcom,prng-ee";
269 reg = <0x000e3000 0x1000>;
270 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core";
272 status = "disabled";
273 };
274
275 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq8074-tsens";
277 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000>; /* SROT */
279 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "combined";
281 #qcom,sensors = <16>;
282 #thermal-sensor-cells = <1>;
283 };
284
285 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam-v1.7.0";
287 reg = <0x00704000 0x20000>;
288 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk";
291 #dma-cells = <1>;
292 qcom,ee = <1>;
293 qcom,controlled-remotely;
294 status = "disabled";
295 };
296
297 crypto: crypto@73a000 {
298 compatible = "qcom,crypto-v5.1";
299 reg = <0x0073a000 0x6000>;
300 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", "bus", "core";
304 dmas = <&cryptobam 2>, <&cryptobam 3>;
305 dma-names = "rx", "tx";
306 status = "disabled";
307 };
308
309 tlmm: pinctrl@1000000 {
310 compatible = "qcom,ipq8074-pinctrl";
311 reg = <0x01000000 0x300000>;
312 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller;
314 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318
319 serial_4_pins: serial4-state {
320 pins = "gpio23", "gpio24";
321 function = "blsp4_uart1";
322 drive-strength = <8>;
323 bias-disable;
324 };
325
326 serial_5_pins: serial5-state {
327 pins = "gpio9", "gpio16";
328 function = "blsp5_uart";
329 drive-strength = <8>;
330 bias-disable;
331 };
332
333 i2c_0_pins: i2c-0-state {
334 pins = "gpio42", "gpio43";
335 function = "blsp1_i2c";
336 drive-strength = <8>;
337 bias-disable;
338 };
339
340 spi_0_pins: spi-0-state {
341 pins = "gpio38", "gpio39", "gpio40", "gpio41";
342 function = "blsp0_spi";
343 drive-strength = <8>;
344 bias-disable;
345 };
346
347 hsuart_pins: hsuart-state {
348 pins = "gpio46", "gpio47", "gpio48", "gpio49";
349 function = "blsp2_uart";
350 drive-strength = <8>;
351 bias-disable;
352 };
353
354 qpic_pins: qpic-state {
355 pins = "gpio1", "gpio3", "gpio4",
356 "gpio5", "gpio6", "gpio7",
357 "gpio8", "gpio10", "gpio11",
358 "gpio12", "gpio13", "gpio14",
359 "gpio15", "gpio17";
360 function = "qpic";
361 drive-strength = <8>;
362 bias-disable;
363 };
364 };
365
366 gcc: clock-controller@1800000 {
367 compatible = "qcom,gcc-ipq8074";
368 reg = <0x01800000 0x80000>;
369 clocks = <&xo>,
370 <&sleep_clk>,
371 <&pcie_qmp0>,
372 <&pcie_qmp1>;
373 clock-names = "xo",
374 "sleep_clk",
375 "pcie0_pipe",
376 "pcie1_pipe";
377 #clock-cells = <1>;
378 #power-domain-cells = <1>;
379 #reset-cells = <1>;
380 };
381
382 tcsr_mutex: hwlock@1905000 {
383 compatible = "qcom,tcsr-mutex";
384 reg = <0x01905000 0x20000>;
385 #hwlock-cells = <1>;
386 };
387
388 tcsr: syscon@1937000 {
389 compatible = "qcom,tcsr-ipq8074", "syscon";
390 reg = <0x01937000 0x21000>;
391 };
392
393 spmi_bus: spmi@200f000 {
394 compatible = "qcom,spmi-pmic-arb";
395 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x800000>,
397 <0x02c00000 0x800000>,
398 <0x03800000 0x200000>,
399 <0x0200a000 0x000700>;
400 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
401 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "periph_irq";
403 qcom,ee = <0>;
404 qcom,channel = <0>;
405 #address-cells = <2>;
406 #size-cells = <0>;
407 interrupt-controller;
408 #interrupt-cells = <4>;
409 };
410
411 sdhc_1: mmc@7824900 {
412 compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
413 reg = <0x7824900 0x500>, <0x7824000 0x800>;
414 reg-names = "hc", "core";
415
416 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "hc_irq", "pwr_irq";
419
420 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDCC1_APPS_CLK>,
422 <&xo>;
423 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <384000000>;
426 mmc-ddr-1_8v;
427 mmc-hs200-1_8v;
428 mmc-hs400-1_8v;
429 bus-width = <8>;
430
431 status = "disabled";
432 };
433
434 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam-v1.7.0";
436 reg = <0x07884000 0x2b000>;
437 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk";
440 #dma-cells = <1>;
441 qcom,ee = <0>;
442 };
443
444 blsp1_uart1: serial@78af000 {
445 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
446 reg = <0x078af000 0x200>;
447 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", "iface";
451 status = "disabled";
452 };
453
454 blsp1_uart3: serial@78b1000 {
455 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 reg = <0x078b1000 0x200>;
457 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", "iface";
461 dmas = <&blsp_dma 4>,
462 <&blsp_dma 5>;
463 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "default";
466 status = "disabled";
467 };
468
469 blsp1_uart5: serial@78b3000 {
470 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
471 reg = <0x078b3000 0x200>;
472 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "default";
478 status = "disabled";
479 };
480
481 blsp1_uart6: serial@78b4000 {
482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
483 reg = <0x078b4000 0x200>;
484 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
486 <&gcc GCC_BLSP1_AHB_CLK>;
487 clock-names = "core", "iface";
488 pinctrl-0 = <&serial_5_pins>;
489 pinctrl-names = "default";
490 status = "disabled";
491 };
492
493 blsp1_spi1: spi@78b5000 {
494 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 reg = <0x078b5000 0x600>;
498 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", "iface";
502 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
503 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "default";
506 status = "disabled";
507 };
508
509 blsp1_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <0x078b6000 0x600>;
514 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", "iface";
518 clock-frequency = <400000>;
519 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
520 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "default";
523 status = "disabled";
524 };
525
526 blsp1_i2c3: i2c@78b7000 {
527 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <0x078b7000 0x600>;
531 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", "iface";
535 clock-frequency = <100000>;
536 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
537 dma-names = "tx", "rx";
538 status = "disabled";
539 };
540
541 blsp1_spi4: spi@78b8000 {
542 compatible = "qcom,spi-qup-v2.2.1";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 reg = <0x78b8000 0x600>;
546 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
550 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
551 dma-names = "tx", "rx";
552 status = "disabled";
553 };
554
555 blsp1_i2c5: i2c@78b9000 {
556 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>;
558 #size-cells = <0>;
559 reg = <0x78b9000 0x600>;
560 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", "iface";
564 clock-frequency = <400000>;
565 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
566 dma-names = "tx", "rx";
567 status = "disabled";
568 };
569
570 blsp1_spi5: spi@78b9000 {
571 compatible = "qcom,spi-qup-v2.2.1";
572 #address-cells = <1>;
573 #size-cells = <0>;
574 reg = <0x78b9000 0x600>;
575 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", "iface";
579 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
580 dma-names = "tx", "rx";
581 status = "disabled";
582 };
583
584 blsp1_i2c6: i2c@78ba000 {
585 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 reg = <0x078ba000 0x600>;
589 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", "iface";
593 clock-frequency = <100000>;
594 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
595 dma-names = "tx", "rx";
596 status = "disabled";
597 };
598
599 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam-v1.7.0";
601 reg = <0x07984000 0x1a000>;
602 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk";
605 #dma-cells = <1>;
606 qcom,ee = <0>;
607 status = "disabled";
608 };
609
610 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq8074-nand";
612 reg = <0x079b0000 0x10000>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", "aon";
618
619 dmas = <&qpic_bam 0>,
620 <&qpic_bam 1>,
621 <&qpic_bam 2>;
622 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "default";
625 status = "disabled";
626 };
627
628 usb_0: usb@8af8800 {
629 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
630 reg = <0x08af8800 0x400>;
631 #address-cells = <1>;
632 #size-cells = <1>;
633 ranges;
634
635 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc",
640 "core",
641 "sleep",
642 "mock_utmi";
643
644 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = <133330000>,
648 <133330000>,
649 <19200000>;
650
651 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-names = "pwr_event",
655 "qusb2_phy",
656 "ss_phy_irq";
657
658 power-domains = <&gcc USB0_GDSC>;
659
660 resets = <&gcc GCC_USB0_BCR>;
661 status = "disabled";
662
663 dwc_0: usb@8a00000 {
664 compatible = "snps,dwc3";
665 reg = <0x8a00000 0xcd00>;
666 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
667 phys = <&qusb_phy_0>, <&ssphy_0>;
668 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode-disable-ss-quirk;
670 snps,is-utmi-l1-suspend;
671 snps,hird-threshold = /bits/ 8 <0x0>;
672 snps,dis_u2_susphy_quirk;
673 snps,dis_u3_susphy_quirk;
674 dr_mode = "host";
675 };
676 };
677
678 usb_1: usb@8cf8800 {
679 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
680 reg = <0x08cf8800 0x400>;
681 #address-cells = <1>;
682 #size-cells = <1>;
683 ranges;
684
685 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc",
690 "core",
691 "sleep",
692 "mock_utmi";
693
694 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = <133330000>,
698 <133330000>,
699 <19200000>;
700
701 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "pwr_event",
705 "qusb2_phy",
706 "ss_phy_irq";
707
708 power-domains = <&gcc USB1_GDSC>;
709
710 resets = <&gcc GCC_USB1_BCR>;
711 status = "disabled";
712
713 dwc_1: usb@8c00000 {
714 compatible = "snps,dwc3";
715 reg = <0x8c00000 0xcd00>;
716 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
717 phys = <&qusb_phy_1>, <&ssphy_1>;
718 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode-disable-ss-quirk;
720 snps,is-utmi-l1-suspend;
721 snps,hird-threshold = /bits/ 8 <0x0>;
722 snps,dis_u2_susphy_quirk;
723 snps,dis_u3_susphy_quirk;
724 dr_mode = "host";
725 };
726 };
727
728 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>;
731 #size-cells = <1>;
732 interrupt-controller;
733 #interrupt-cells = <3>;
734 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 0xffd>;
736
737 v2m@0 {
738 compatible = "arm,gic-v2m-frame";
739 msi-controller;
740 reg = <0x0 0xffd>;
741 };
742 };
743
744 watchdog: watchdog@b017000 {
745 compatible = "qcom,kpss-wdt";
746 reg = <0xb017000 0x1000>;
747 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
748 clocks = <&sleep_clk>;
749 timeout-sec = <30>;
750 };
751
752 apcs_glb: mailbox@b111000 {
753 compatible = "qcom,ipq8074-apcs-apps-global",
754 "qcom,ipq6018-apcs-apps-global";
755 reg = <0x0b111000 0x1000>;
756 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
757 clock-names = "pll", "xo", "gpll0";
758
759 #clock-cells = <1>;
760 #mbox-cells = <1>;
761 };
762
763 a53pll: clock@b116000 {
764 compatible = "qcom,ipq8074-a53pll";
765 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>;
767 clocks = <&xo>;
768 clock-names = "xo";
769 };
770
771 timer@b120000 {
772 #address-cells = <1>;
773 #size-cells = <1>;
774 ranges;
775 compatible = "arm,armv7-timer-mem";
776 reg = <0x0b120000 0x1000>;
777
778 frame@b120000 {
779 frame-number = <0>;
780 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
782 reg = <0x0b121000 0x1000>,
783 <0x0b122000 0x1000>;
784 };
785
786 frame@b123000 {
787 frame-number = <1>;
788 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
789 reg = <0x0b123000 0x1000>;
790 status = "disabled";
791 };
792
793 frame@b124000 {
794 frame-number = <2>;
795 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x0b124000 0x1000>;
797 status = "disabled";
798 };
799
800 frame@b125000 {
801 frame-number = <3>;
802 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0x0b125000 0x1000>;
804 status = "disabled";
805 };
806
807 frame@b126000 {
808 frame-number = <4>;
809 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x0b126000 0x1000>;
811 status = "disabled";
812 };
813
814 frame@b127000 {
815 frame-number = <5>;
816 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
817 reg = <0x0b127000 0x1000>;
818 status = "disabled";
819 };
820
821 frame@b128000 {
822 frame-number = <6>;
823 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x0b128000 0x1000>;
825 status = "disabled";
826 };
827 };
828
829 pcie1: pcie@10000000 {
830 compatible = "qcom,pcie-ipq8074";
831 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8>,
833 <0x00088000 0x2000>,
834 <0x10100000 0x1000>;
835 reg-names = "dbi", "elbi", "parf", "config";
836 device_type = "pci";
837 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff>;
839 num-lanes = <1>;
840 max-link-speed = <2>;
841 #address-cells = <3>;
842 #size-cells = <2>;
843
844 phys = <&pcie_qmp1>;
845 phy-names = "pciephy";
846
847 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
849
850 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "msi";
852 #interrupt-cells = <1>;
853 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 1 &intc 0 0 142
855 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
856 <0 0 0 2 &intc 0 0 143
857 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
858 <0 0 0 3 &intc 0 0 144
859 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
860 <0 0 0 4 &intc 0 0 145
861 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
862
863 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface",
869 "axi_m",
870 "axi_s",
871 "ahb",
872 "aux";
873 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe",
881 "sleep",
882 "sticky",
883 "axi_m",
884 "axi_s",
885 "ahb",
886 "axi_m_sticky";
887 status = "disabled";
888
889 pcie@0 {
890 device_type = "pci";
891 reg = <0x0 0x0 0x0 0x0 0x0>;
892 bus-range = <0x01 0xff>;
893
894 #address-cells = <3>;
895 #size-cells = <2>;
896 ranges;
897 };
898 };
899
900 pcie0: pcie@20000000 {
901 compatible = "qcom,pcie-ipq8074-gen3";
902 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8>,
904 <0x20001000 0x1000>,
905 <0x00080000 0x4000>,
906 <0x20100000 0x1000>;
907 reg-names = "dbi", "elbi", "atu", "parf", "config";
908 device_type = "pci";
909 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff>;
911 num-lanes = <1>;
912 max-link-speed = <3>;
913 #address-cells = <3>;
914 #size-cells = <2>;
915
916 phys = <&pcie_qmp0>;
917 phy-names = "pciephy";
918
919 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
921
922 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
923 interrupt-names = "msi";
924 #interrupt-cells = <1>;
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 75
927 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
928 <0 0 0 2 &intc 0 0 78
929 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
930 <0 0 0 3 &intc 0 0 79
931 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
932 <0 0 0 4 &intc 0 0 83
933 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
934
935 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface",
941 "axi_m",
942 "axi_s",
943 "axi_bridge",
944 "rchng";
945
946 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe",
955 "sleep",
956 "sticky",
957 "axi_m",
958 "axi_s",
959 "ahb",
960 "axi_m_sticky",
961 "axi_s_sticky";
962 status = "disabled";
963
964 pcie@0 {
965 device_type = "pci";
966 reg = <0x0 0x0 0x0 0x0 0x0>;
967 bus-range = <0x01 0xff>;
968
969 #address-cells = <3>;
970 #size-cells = <2>;
971 ranges;
972 };
973 };
974 };
975
976 timer {
977 compatible = "arm,armv8-timer";
978 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
981 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
982 };
983
984 thermal-zones {
985 nss-top-thermal {
986 polling-delay-passive = <250>;
987
988 thermal-sensors = <&tsens 4>;
989
990 trips {
991 nss-top-crit {
992 temperature = <110000>;
993 hysteresis = <1000>;
994 type = "critical";
995 };
996 };
997 };
998
999 nss0-thermal {
1000 polling-delay-passive = <250>;
1001
1002 thermal-sensors = <&tsens 5>;
1003
1004 trips {
1005 nss-0-crit {
1006 temperature = <110000>;
1007 hysteresis = <1000>;
1008 type = "critical";
1009 };
1010 };
1011 };
1012
1013 nss1-thermal {
1014 polling-delay-passive = <250>;
1015
1016 thermal-sensors = <&tsens 6>;
1017
1018 trips {
1019 nss-1-crit {
1020 temperature = <110000>;
1021 hysteresis = <1000>;
1022 type = "critical";
1023 };
1024 };
1025 };
1026
1027 wcss-phya0-thermal {
1028 polling-delay-passive = <250>;
1029
1030 thermal-sensors = <&tsens 7>;
1031
1032 trips {
1033 wcss-phya0-crit {
1034 temperature = <110000>;
1035 hysteresis = <1000>;
1036 type = "critical";
1037 };
1038 };
1039 };
1040
1041 wcss-phya1-thermal {
1042 polling-delay-passive = <250>;
1043
1044 thermal-sensors = <&tsens 8>;
1045
1046 trips {
1047 wcss-phya1-crit {
1048 temperature = <110000>;
1049 hysteresis = <1000>;
1050 type = "critical";
1051 };
1052 };
1053 };
1054
1055 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive = <250>;
1057
1058 thermal-sensors = <&tsens 9>;
1059
1060 trips {
1061 cpu0-crit {
1062 temperature = <110000>;
1063 hysteresis = <1000>;
1064 type = "critical";
1065 };
1066 };
1067 };
1068
1069 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive = <250>;
1071
1072 thermal-sensors = <&tsens 10>;
1073
1074 trips {
1075 cpu1-crit {
1076 temperature = <110000>;
1077 hysteresis = <1000>;
1078 type = "critical";
1079 };
1080 };
1081 };
1082
1083 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive = <250>;
1085
1086 thermal-sensors = <&tsens 11>;
1087
1088 trips {
1089 cpu2-crit {
1090 temperature = <110000>;
1091 hysteresis = <1000>;
1092 type = "critical";
1093 };
1094 };
1095 };
1096
1097 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive = <250>;
1099
1100 thermal-sensors = <&tsens 12>;
1101
1102 trips {
1103 cpu3-crit {
1104 temperature = <110000>;
1105 hysteresis = <1000>;
1106 type = "critical";
1107 };
1108 };
1109 };
1110
1111 cluster_thermal: cluster-thermal {
1112 polling-delay-passive = <250>;
1113
1114 thermal-sensors = <&tsens 13>;
1115
1116 trips {
1117 cluster-crit {
1118 temperature = <110000>;
1119 hysteresis = <1000>;
1120 type = "critical";
1121 };
1122 };
1123 };
1124
1125 wcss-phyb0-thermal {
1126 polling-delay-passive = <250>;
1127
1128 thermal-sensors = <&tsens 14>;
1129
1130 trips {
1131 wcss-phyb0-crit {
1132 temperature = <110000>;
1133 hysteresis = <1000>;
1134 type = "critical";
1135 };
1136 };
1137 };
1138
1139 wcss-phyb1-thermal {
1140 polling-delay-passive = <250>;
1141
1142 thermal-sensors = <&tsens 15>;
1143
1144 trips {
1145 wcss-phyb1-crit {
1146 temperature = <110000>;
1147 hysteresis = <1000>;
1148 type = "critical";
1149 };
1150 };
1151 };
1152 };
1153 };
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