1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
5 */
6
7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8939.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&intc>;
18
19 /*
20 * Stock LK wants address-cells/size-cells = 2
21 * A number of our drivers want address/size cells = 1
22 * hence the disparity between top-level and /soc below.
23 */
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <19200000>;
32 };
33
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
38 };
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 CPU0: cpu@100 {
46 compatible = "arm,cortex-a53";
47 device_type = "cpu";
48 enable-method = "spin-table";
49 reg = <0x100>;
50 next-level-cache = <&L2_1>;
51 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
54 clocks = <&apcs1_mbox>;
55 #cooling-cells = <2>;
56 L2_1: l2-cache {
57 compatible = "cache";
58 cache-level = <2>;
59 cache-unified;
60 };
61 };
62
63 CPU1: cpu@101 {
64 compatible = "arm,cortex-a53";
65 device_type = "cpu";
66 enable-method = "spin-table";
67 reg = <0x101>;
68 next-level-cache = <&L2_1>;
69 qcom,acc = <&acc1>;
70 qcom,saw = <&saw1>;
71 cpu-idle-states = <&CPU_SLEEP_0>;
72 clocks = <&apcs1_mbox>;
73 #cooling-cells = <2>;
74 };
75
76 CPU2: cpu@102 {
77 compatible = "arm,cortex-a53";
78 device_type = "cpu";
79 enable-method = "spin-table";
80 reg = <0x102>;
81 next-level-cache = <&L2_1>;
82 qcom,acc = <&acc2>;
83 qcom,saw = <&saw2>;
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 clocks = <&apcs1_mbox>;
86 #cooling-cells = <2>;
87 };
88
89 CPU3: cpu@103 {
90 compatible = "arm,cortex-a53";
91 device_type = "cpu";
92 enable-method = "spin-table";
93 reg = <0x103>;
94 next-level-cache = <&L2_1>;
95 qcom,acc = <&acc3>;
96 qcom,saw = <&saw3>;
97 cpu-idle-states = <&CPU_SLEEP_0>;
98 clocks = <&apcs1_mbox>;
99 #cooling-cells = <2>;
100 };
101
102 CPU4: cpu@0 {
103 compatible = "arm,cortex-a53";
104 device_type = "cpu";
105 enable-method = "spin-table";
106 reg = <0x0>;
107 qcom,acc = <&acc4>;
108 qcom,saw = <&saw4>;
109 cpu-idle-states = <&CPU_SLEEP_0>;
110 clocks = <&apcs0_mbox>;
111 #cooling-cells = <2>;
112 next-level-cache = <&L2_0>;
113 L2_0: l2-cache {
114 compatible = "cache";
115 cache-level = <2>;
116 cache-unified;
117 };
118 };
119
120 CPU5: cpu@1 {
121 compatible = "arm,cortex-a53";
122 device_type = "cpu";
123 enable-method = "spin-table";
124 reg = <0x1>;
125 next-level-cache = <&L2_0>;
126 qcom,acc = <&acc5>;
127 qcom,saw = <&saw5>;
128 cpu-idle-states = <&CPU_SLEEP_0>;
129 clocks = <&apcs0_mbox>;
130 #cooling-cells = <2>;
131 };
132
133 CPU6: cpu@2 {
134 compatible = "arm,cortex-a53";
135 device_type = "cpu";
136 enable-method = "spin-table";
137 reg = <0x2>;
138 next-level-cache = <&L2_0>;
139 qcom,acc = <&acc6>;
140 qcom,saw = <&saw6>;
141 cpu-idle-states = <&CPU_SLEEP_0>;
142 clocks = <&apcs0_mbox>;
143 #cooling-cells = <2>;
144 };
145
146 CPU7: cpu@3 {
147 compatible = "arm,cortex-a53";
148 device_type = "cpu";
149 enable-method = "spin-table";
150 reg = <0x3>;
151 next-level-cache = <&L2_0>;
152 qcom,acc = <&acc7>;
153 qcom,saw = <&saw7>;
154 cpu-idle-states = <&CPU_SLEEP_0>;
155 clocks = <&apcs0_mbox>;
156 #cooling-cells = <2>;
157 };
158
159 idle-states {
160 CPU_SLEEP_0: cpu-sleep-0 {
161 compatible = "arm,idle-state";
162 entry-latency-us = <130>;
163 exit-latency-us = <150>;
164 min-residency-us = <2000>;
165 local-timer-stop;
166 };
167 };
168 };
169
170 /*
171 * MSM8939 has a big.LITTLE heterogeneous computing architecture,
172 * consisting of two clusters of four ARM Cortex-A53s each. The
173 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
174 * at 1.5-1.7GHz.
175 *
176 * The enable method used here is spin-table which presupposes use
177 * of a 2nd stage boot shim such as lk2nd to have installed a
178 * spin-table, the downstream non-psci/non-spin-table method that
179 * default msm8916/msm8936/msm8939 will not be supported upstream.
180 */
181 cpu-map {
182 /* LITTLE (efficiency) cluster */
183 cluster0 {
184 core0 {
185 cpu = <&CPU4>;
186 };
187
188 core1 {
189 cpu = <&CPU5>;
190 };
191
192 core2 {
193 cpu = <&CPU6>;
194 };
195
196 core3 {
197 cpu = <&CPU7>;
198 };
199 };
200
201 /* big (performance) cluster */
202 /* Boot CPU is cluster 1 core 0 */
203 cluster1 {
204 core0 {
205 cpu = <&CPU0>;
206 };
207
208 core1 {
209 cpu = <&CPU1>;
210 };
211
212 core2 {
213 cpu = <&CPU2>;
214 };
215
216 core3 {
217 cpu = <&CPU3>;
218 };
219 };
220 };
221
222 firmware {
223 scm: scm {
224 compatible = "qcom,scm-msm8916", "qcom,scm";
225 clocks = <&gcc GCC_CRYPTO_CLK>,
226 <&gcc GCC_CRYPTO_AXI_CLK>,
227 <&gcc GCC_CRYPTO_AHB_CLK>;
228 clock-names = "core", "bus", "iface";
229 #reset-cells = <1>;
230
231 qcom,dload-mode = <&tcsr 0x6100>;
232 };
233 };
234
235 memory@80000000 {
236 device_type = "memory";
237 /* We expect the bootloader to fill in the reg */
238 reg = <0x0 0x80000000 0x0 0x0>;
239 };
240
241 pmu {
242 compatible = "arm,cortex-a53-pmu";
243 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
244 };
245
246 rpm: remoteproc {
247 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
248
249 smd-edge {
250 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
251 qcom,ipc = <&apcs1_mbox 8 0>;
252 qcom,smd-edge = <15>;
253
254 rpm_requests: rpm-requests {
255 compatible = "qcom,rpm-msm8936", "qcom,smd-rpm";
256 qcom,smd-channels = "rpm_requests";
257
258 rpmcc: clock-controller {
259 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
260 #clock-cells = <1>;
261 clock-names = "xo";
262 clocks = <&xo_board>;
263 };
264
265 rpmpd: power-controller {
266 compatible = "qcom,msm8939-rpmpd";
267 #power-domain-cells = <1>;
268 operating-points-v2 = <&rpmpd_opp_table>;
269
270 rpmpd_opp_table: opp-table {
271 compatible = "operating-points-v2";
272
273 rpmpd_opp_ret: opp1 {
274 opp-level = <1>;
275 };
276
277 rpmpd_opp_svs_krait: opp2 {
278 opp-level = <2>;
279 };
280
281 rpmpd_opp_svs_soc: opp3 {
282 opp-level = <3>;
283 };
284
285 rpmpd_opp_nom: opp4 {
286 opp-level = <4>;
287 };
288
289 rpmpd_opp_turbo: opp5 {
290 opp-level = <5>;
291 };
292
293 rpmpd_opp_super_turbo: opp6 {
294 opp-level = <6>;
295 };
296 };
297 };
298 };
299 };
300 };
301
302 reserved-memory {
303 #address-cells = <2>;
304 #size-cells = <2>;
305 ranges;
306
307 tz-apps@86000000 {
308 reg = <0x0 0x86000000 0x0 0x300000>;
309 no-map;
310 };
311
312 smem@86300000 {
313 compatible = "qcom,smem";
314 reg = <0x0 0x86300000 0x0 0x100000>;
315 no-map;
316
317 hwlocks = <&tcsr_mutex 3>;
318 qcom,rpm-msg-ram = <&rpm_msg_ram>;
319 };
320
321 hypervisor@86400000 {
322 reg = <0x0 0x86400000 0x0 0x100000>;
323 no-map;
324 };
325
326 tz@86500000 {
327 reg = <0x0 0x86500000 0x0 0x180000>;
328 no-map;
329 };
330
331 reserved@86680000 {
332 reg = <0x0 0x86680000 0x0 0x80000>;
333 no-map;
334 };
335
336 rmtfs@86700000 {
337 compatible = "qcom,rmtfs-mem";
338 reg = <0x0 0x86700000 0x0 0xe0000>;
339 no-map;
340
341 qcom,client-id = <1>;
342 };
343
344 rfsa@867e0000 {
345 reg = <0x0 0x867e0000 0x0 0x20000>;
346 no-map;
347 };
348
349 mpss_mem: mpss@86800000 {
350 /*
351 * The memory region for the mpss firmware is generally
352 * relocatable and could be allocated dynamically.
353 * However, many firmware versions tend to fail when
354 * loaded to some special addresses, so it is hard to
355 * define reliable alloc-ranges.
356 *
357 * alignment = <0x0 0x400000>;
358 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
359 */
360 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
361 no-map;
362 status = "disabled";
363 };
364
365 wcnss_mem: wcnss {
366 size = <0x0 0x600000>;
367 alignment = <0x0 0x100000>;
368 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
369 no-map;
370 status = "disabled";
371 };
372
373 venus_mem: venus {
374 size = <0x0 0x500000>;
375 alignment = <0x0 0x100000>;
376 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
377 no-map;
378 status = "disabled";
379 };
380
381 mba_mem: mba {
382 size = <0x0 0x100000>;
383 alignment = <0x0 0x100000>;
384 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
385 no-map;
386 status = "disabled";
387 };
388 };
389
390 smp2p-hexagon {
391 compatible = "qcom,smp2p";
392 qcom,smem = <435>, <428>;
393
394 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
395
396 mboxes = <&apcs1_mbox 14>;
397
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <1>;
400
401 hexagon_smp2p_out: master-kernel {
402 qcom,entry-name = "master-kernel";
403
404 #qcom,smem-state-cells = <1>;
405 };
406
407 hexagon_smp2p_in: slave-kernel {
408 qcom,entry-name = "slave-kernel";
409
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 };
413 };
414
415 smp2p-wcnss {
416 compatible = "qcom,smp2p";
417 qcom,smem = <451>, <431>;
418
419 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
420
421 mboxes = <&apcs1_mbox 18>;
422
423 qcom,local-pid = <0>;
424 qcom,remote-pid = <4>;
425
426 wcnss_smp2p_in: slave-kernel {
427 qcom,entry-name = "slave-kernel";
428
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 };
432
433 wcnss_smp2p_out: master-kernel {
434 qcom,entry-name = "master-kernel";
435
436 #qcom,smem-state-cells = <1>;
437 };
438 };
439
440 smsm {
441 compatible = "qcom,smsm";
442
443 #address-cells = <1>;
444 #size-cells = <0>;
445
446 mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>;
447
448 apps_smsm: apps@0 {
449 reg = <0>;
450
451 #qcom,smem-state-cells = <1>;
452 };
453
454 hexagon_smsm: hexagon@1 {
455 reg = <1>;
456 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
457
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 };
461
462 wcnss_smsm: wcnss@6 {
463 reg = <6>;
464 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
465
466 interrupt-controller;
467 #interrupt-cells = <2>;
468 };
469 };
470
471 soc: soc@0 {
472 compatible = "simple-bus";
473 #address-cells = <1>;
474 #size-cells = <1>;
475 ranges = <0 0 0 0xffffffff>;
476
477 rng@22000 {
478 compatible = "qcom,prng";
479 reg = <0x00022000 0x200>;
480 clocks = <&gcc GCC_PRNG_AHB_CLK>;
481 clock-names = "core";
482 };
483
484 qfprom: qfprom@5c000 {
485 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
486 reg = <0x0005c000 0x1000>;
487 #address-cells = <1>;
488 #size-cells = <1>;
489
490 tsens_base1: base1@a0 {
491 reg = <0xa0 0x1>;
492 bits = <0 8>;
493 };
494
495 tsens_s6_p1: s6-p1@a1 {
496 reg = <0xa1 0x1>;
497 bits = <0 6>;
498 };
499
500 tsens_s6_p2: s6-p2@a1 {
501 reg = <0xa1 0x2>;
502 bits = <6 6>;
503 };
504
505 tsens_s7_p1: s7-p1@a2 {
506 reg = <0xa2 0x2>;
507 bits = <4 6>;
508 };
509
510 tsens_s7_p2: s7-p2@a3 {
511 reg = <0xa3 0x1>;
512 bits = <2 6>;
513 };
514
515 tsens_s8_p1: s8-p1@a4 {
516 reg = <0xa4 0x1>;
517 bits = <0 6>;
518 };
519
520 tsens_s8_p2: s8-p2@a4 {
521 reg = <0xa4 0x2>;
522 bits = <6 6>;
523 };
524
525 tsens_s9_p1: s9-p1@a5 {
526 reg = <0xa5 0x2>;
527 bits = <4 6>;
528 };
529
530 tsens_s9_p2: s9-p2@a6 {
531 reg = <0xa6 0x1>;
532 bits = <2 6>;
533 };
534
535 tsens_base2: base2@a7 {
536 reg = <0xa7 0x1>;
537 bits = <0 8>;
538 };
539
540 tsens_mode: mode@d0 {
541 reg = <0xd0 0x1>;
542 bits = <0 3>;
543 };
544
545 tsens_s0_p1: s0-p1@d0 {
546 reg = <0xd0 0x2>;
547 bits = <3 6>;
548 };
549
550 tsens_s0_p2: s0-p1@d1 {
551 reg = <0xd1 0x1>;
552 bits = <1 6>;
553 };
554
555 tsens_s1_p1: s1-p1@d1 {
556 reg = <0xd1 0x2>;
557 bits = <7 6>;
558 };
559
560 tsens_s1_p2: s1-p2@d2 {
561 reg = <0xd2 0x2>;
562 bits = <5 6>;
563 };
564
565 tsens_s2_p1: s2-p1@d3 {
566 reg = <0xd3 0x2>;
567 bits = <3 6>;
568 };
569
570 tsens_s2_p2: s2-p2@d4 {
571 reg = <0xd4 0x1>;
572 bits = <1 6>;
573 };
574
575 tsens_s3_p1: s3-p1@d4 {
576 reg = <0xd4 0x2>;
577 bits = <7 6>;
578 };
579
580 tsens_s3_p2: s3-p2@d5 {
581 reg = <0xd5 0x2>;
582 bits = <5 6>;
583 };
584
585 tsens_s5_p1: s5-p1@d6 {
586 reg = <0xd6 0x2>;
587 bits = <3 6>;
588 };
589
590 tsens_s5_p2: s5-p2@d7 {
591 reg = <0xd7 0x1>;
592 bits = <1 6>;
593 };
594 };
595
596 rpm_msg_ram: sram@60000 {
597 compatible = "qcom,rpm-msg-ram";
598 reg = <0x00060000 0x8000>;
599 };
600
601 bimc: interconnect@400000 {
602 compatible = "qcom,msm8939-bimc";
603 reg = <0x00400000 0x62000>;
604 #interconnect-cells = <1>;
605 };
606
607 tsens: thermal-sensor@4a9000 {
608 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
609 reg = <0x004a9000 0x1000>, /* TM */
610 <0x004a8000 0x1000>; /* SROT */
611 nvmem-cells = <&tsens_mode>,
612 <&tsens_base1>, <&tsens_base2>,
613 <&tsens_s0_p1>, <&tsens_s0_p2>,
614 <&tsens_s1_p1>, <&tsens_s1_p2>,
615 <&tsens_s2_p1>, <&tsens_s2_p2>,
616 <&tsens_s3_p1>, <&tsens_s3_p2>,
617 <&tsens_s5_p1>, <&tsens_s5_p2>,
618 <&tsens_s6_p1>, <&tsens_s6_p2>,
619 <&tsens_s7_p1>, <&tsens_s7_p2>,
620 <&tsens_s8_p1>, <&tsens_s8_p2>,
621 <&tsens_s9_p1>, <&tsens_s9_p2>;
622 nvmem-cell-names = "mode",
623 "base1", "base2",
624 "s0_p1", "s0_p2",
625 "s1_p1", "s1_p2",
626 "s2_p1", "s2_p2",
627 "s3_p1", "s3_p2",
628 "s5_p1", "s5_p2",
629 "s6_p1", "s6_p2",
630 "s7_p1", "s7_p2",
631 "s8_p1", "s8_p2",
632 "s9_p1", "s9_p2";
633 #qcom,sensors = <9>;
634 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "uplow";
636 #thermal-sensor-cells = <1>;
637 };
638
639 restart@4ab000 {
640 compatible = "qcom,pshold";
641 reg = <0x004ab000 0x4>;
642 };
643
644 pcnoc: interconnect@500000 {
645 compatible = "qcom,msm8939-pcnoc";
646 reg = <0x00500000 0x11000>;
647 #interconnect-cells = <1>;
648 };
649
650 snoc: interconnect@580000 {
651 compatible = "qcom,msm8939-snoc";
652 reg = <0x00580000 0x14080>;
653 #interconnect-cells = <1>;
654
655 snoc_mm: interconnect-snoc {
656 compatible = "qcom,msm8939-snoc-mm";
657 #interconnect-cells = <1>;
658 };
659 };
660
661 tlmm: pinctrl@1000000 {
662 compatible = "qcom,msm8916-pinctrl";
663 reg = <0x01000000 0x300000>;
664 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
665 gpio-controller;
666 gpio-ranges = <&tlmm 0 0 122>;
667 #gpio-cells = <2>;
668 interrupt-controller;
669 #interrupt-cells = <2>;
670
671 blsp_i2c1_default: blsp-i2c1-default-state {
672 pins = "gpio2", "gpio3";
673 function = "blsp_i2c1";
674 drive-strength = <2>;
675 bias-disable;
676 };
677
678 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
679 pins = "gpio2", "gpio3";
680 function = "gpio";
681 drive-strength = <2>;
682 bias-disable;
683 };
684
685 blsp_i2c2_default: blsp-i2c2-default-state {
686 pins = "gpio6", "gpio7";
687 function = "blsp_i2c2";
688 drive-strength = <2>;
689 bias-disable;
690 };
691
692 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
693 pins = "gpio6", "gpio7";
694 function = "gpio";
695 drive-strength = <2>;
696 bias-disable;
697 };
698
699 blsp_i2c3_default: blsp-i2c3-default-state {
700 pins = "gpio10", "gpio11";
701 function = "blsp_i2c3";
702 drive-strength = <2>;
703 bias-disable;
704 };
705
706 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
707 pins = "gpio10", "gpio11";
708 function = "gpio";
709 drive-strength = <2>;
710 bias-disable;
711 };
712
713 blsp_i2c4_default: blsp-i2c4-default-state {
714 pins = "gpio14", "gpio15";
715 function = "blsp_i2c4";
716 drive-strength = <2>;
717 bias-disable;
718 };
719
720 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
721 pins = "gpio14", "gpio15";
722 function = "gpio";
723 drive-strength = <2>;
724 bias-disable;
725 };
726
727 blsp_i2c5_default: blsp-i2c5-default-state {
728 pins = "gpio18", "gpio19";
729 function = "blsp_i2c5";
730 drive-strength = <2>;
731 bias-disable;
732 };
733
734 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
735 pins = "gpio18", "gpio19";
736 function = "gpio";
737 drive-strength = <2>;
738 bias-disable;
739 };
740
741 blsp_i2c6_default: blsp-i2c6-default-state {
742 pins = "gpio22", "gpio23";
743 function = "blsp_i2c6";
744 drive-strength = <2>;
745 bias-disable;
746 };
747
748 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
749 pins = "gpio22", "gpio23";
750 function = "gpio";
751 drive-strength = <2>;
752 bias-disable;
753 };
754
755 blsp_spi1_default: blsp-spi1-default-state {
756 spi-pins {
757 pins = "gpio0", "gpio1", "gpio3";
758 function = "blsp_spi1";
759 drive-strength = <12>;
760 bias-disable;
761 };
762
763 cs-pins {
764 pins = "gpio2";
765 function = "gpio";
766 drive-strength = <16>;
767 bias-disable;
768 output-high;
769 };
770 };
771
772 blsp_spi1_sleep: blsp-spi1-sleep-state {
773 pins = "gpio0", "gpio1", "gpio2", "gpio3";
774 function = "gpio";
775 drive-strength = <2>;
776 bias-pull-down;
777 };
778
779 blsp_spi2_default: blsp-spi2-default-state {
780 spi-pins {
781 pins = "gpio4", "gpio5", "gpio7";
782 function = "blsp_spi2";
783 drive-strength = <12>;
784 bias-disable;
785 };
786
787 cs-pins {
788 pins = "gpio6";
789 function = "gpio";
790 drive-strength = <16>;
791 bias-disable;
792 output-high;
793 };
794 };
795
796 blsp_spi2_sleep: blsp-spi2-sleep-state {
797 pins = "gpio4", "gpio5", "gpio6", "gpio7";
798 function = "gpio";
799 drive-strength = <2>;
800 bias-pull-down;
801 };
802
803 blsp_spi3_default: blsp-spi3-default-state {
804 spi-pins {
805 pins = "gpio8", "gpio9", "gpio11";
806 function = "blsp_spi3";
807 drive-strength = <12>;
808 bias-disable;
809 };
810
811 cs-pins {
812 pins = "gpio10";
813 function = "gpio";
814 drive-strength = <16>;
815 bias-disable;
816 output-high;
817 };
818 };
819
820 blsp_spi3_sleep: blsp-spi3-sleep-state {
821 pins = "gpio8", "gpio9", "gpio10", "gpio11";
822 function = "gpio";
823 drive-strength = <2>;
824 bias-pull-down;
825 };
826
827 blsp_spi4_default: blsp-spi4-default-state {
828 spi-pins {
829 pins = "gpio12", "gpio13", "gpio15";
830 function = "blsp_spi4";
831 drive-strength = <12>;
832 bias-disable;
833 };
834
835 cs-pins {
836 pins = "gpio14";
837 function = "gpio";
838 drive-strength = <16>;
839 bias-disable;
840 output-high;
841 };
842 };
843
844 blsp_spi4_sleep: blsp-spi4-sleep-state {
845 pins = "gpio12", "gpio13", "gpio14", "gpio15";
846 function = "gpio";
847 drive-strength = <2>;
848 bias-pull-down;
849 };
850
851 blsp_spi5_default: blsp-spi5-default-state {
852 spi-pins {
853 pins = "gpio16", "gpio17", "gpio19";
854 function = "blsp_spi5";
855 drive-strength = <12>;
856 bias-disable;
857 };
858
859 cs-pins {
860 pins = "gpio18";
861 function = "gpio";
862 drive-strength = <16>;
863 bias-disable;
864 output-high;
865 };
866 };
867
868 blsp_spi5_sleep: blsp-spi5-sleep-state {
869 pins = "gpio16", "gpio17", "gpio18", "gpio19";
870 function = "gpio";
871 drive-strength = <2>;
872 bias-pull-down;
873 };
874
875 blsp_spi6_default: blsp-spi6-default-state {
876 spi-pins {
877 pins = "gpio20", "gpio21", "gpio23";
878 function = "blsp_spi6";
879 drive-strength = <12>;
880 bias-disable;
881 };
882
883 cs-pins {
884 pins = "gpio22";
885 function = "gpio";
886 drive-strength = <16>;
887 bias-disable;
888 output-high;
889 };
890 };
891
892 blsp_spi6_sleep: blsp-spi6-sleep-state {
893 pins = "gpio20", "gpio21", "gpio22", "gpio23";
894 function = "gpio";
895 drive-strength = <2>;
896 bias-pull-down;
897 };
898
899 blsp_uart1_default: blsp-uart1-default-state {
900 pins = "gpio0", "gpio1", "gpio2", "gpio3";
901 function = "blsp_uart1";
902 drive-strength = <16>;
903 bias-disable;
904 };
905
906 blsp_uart1_sleep: blsp-uart1-sleep-state {
907 pins = "gpio0", "gpio1", "gpio2", "gpio3";
908 function = "gpio";
909 drive-strength = <2>;
910 bias-pull-down;
911 };
912
913 blsp_uart2_default: blsp-uart2-default-state {
914 pins = "gpio4", "gpio5";
915 function = "blsp_uart2";
916 drive-strength = <16>;
917 bias-disable;
918 };
919
920 blsp_uart2_sleep: blsp-uart2-sleep-state {
921 pins = "gpio4", "gpio5";
922 function = "gpio";
923 drive-strength = <2>;
924 bias-pull-down;
925 };
926
927 camera_front_default: camera-front-default-state {
928 pwdn-pins {
929 pins = "gpio33";
930 function = "gpio";
931 drive-strength = <16>;
932 bias-disable;
933 };
934
935 rst-pins {
936 pins = "gpio28";
937 function = "gpio";
938 drive-strength = <16>;
939 bias-disable;
940 };
941
942 mclk1-pins {
943 pins = "gpio27";
944 function = "cam_mclk1";
945 drive-strength = <16>;
946 bias-disable;
947 };
948 };
949
950 camera_rear_default: camera-rear-default-state {
951 pwdn-pins {
952 pins = "gpio34";
953 function = "gpio";
954 drive-strength = <16>;
955 bias-disable;
956 };
957
958 rst-pins {
959 pins = "gpio35";
960 function = "gpio";
961 drive-strength = <16>;
962 bias-disable;
963 };
964
965 mclk0-pins {
966 pins = "gpio26";
967 function = "cam_mclk0";
968 drive-strength = <16>;
969 bias-disable;
970 };
971 };
972
973 cci0_default: cci0-default-state {
974 pins = "gpio29", "gpio30";
975 function = "cci_i2c";
976 drive-strength = <16>;
977 bias-disable;
978 };
979
980 cdc_dmic_default: cdc-dmic-default-state {
981 clk-pins {
982 pins = "gpio0";
983 function = "dmic0_clk";
984 drive-strength = <8>;
985 };
986
987 data-pins {
988 pins = "gpio1";
989 function = "dmic0_data";
990 drive-strength = <8>;
991 };
992 };
993
994 cdc_dmic_sleep: cdc-dmic-sleep-state {
995 clk-pins {
996 pins = "gpio0";
997 function = "dmic0_clk";
998 drive-strength = <2>;
999 bias-disable;
1000 };
1001
1002 data-pins {
1003 pins = "gpio1";
1004 function = "dmic0_data";
1005 drive-strength = <2>;
1006 bias-disable;
1007 };
1008 };
1009
1010 cdc_pdm_default: cdc-pdm-default-state {
1011 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1012 "gpio67", "gpio68";
1013 function = "cdc_pdm0";
1014 drive-strength = <8>;
1015 bias-disable;
1016 };
1017
1018 cdc_pdm_sleep: cdc-pdm-sleep-state {
1019 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1020 "gpio67", "gpio68";
1021 function = "cdc_pdm0";
1022 drive-strength = <2>;
1023 bias-pull-down;
1024 };
1025
1026 pri_mi2s_default: mi2s-pri-default-state {
1027 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1028 function = "pri_mi2s";
1029 drive-strength = <8>;
1030 bias-disable;
1031 };
1032
1033 pri_mi2s_sleep: mi2s-pri-sleep-state {
1034 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1035 function = "pri_mi2s";
1036 drive-strength = <2>;
1037 bias-disable;
1038 };
1039
1040 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1041 pins = "gpio116";
1042 function = "pri_mi2s";
1043 drive-strength = <8>;
1044 bias-disable;
1045 };
1046
1047 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1048 pins = "gpio116";
1049 function = "pri_mi2s";
1050 drive-strength = <2>;
1051 bias-disable;
1052 };
1053
1054 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1055 pins = "gpio110";
1056 function = "pri_mi2s_ws";
1057 drive-strength = <8>;
1058 bias-disable;
1059 };
1060
1061 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1062 pins = "gpio110";
1063 function = "pri_mi2s_ws";
1064 drive-strength = <2>;
1065 bias-disable;
1066 };
1067
1068 sec_mi2s_default: mi2s-sec-default-state {
1069 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1070 function = "sec_mi2s";
1071 drive-strength = <8>;
1072 bias-disable;
1073 };
1074
1075 sec_mi2s_sleep: mi2s-sec-sleep-state {
1076 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1077 function = "sec_mi2s";
1078 drive-strength = <2>;
1079 bias-disable;
1080 };
1081
1082 sdc1_default: sdc1-default-state {
1083 clk-pins {
1084 pins = "sdc1_clk";
1085 bias-disable;
1086 drive-strength = <16>;
1087 };
1088
1089 cmd-pins {
1090 pins = "sdc1_cmd";
1091 bias-pull-up;
1092 drive-strength = <10>;
1093 };
1094
1095 data-pins {
1096 pins = "sdc1_data";
1097 bias-pull-up;
1098 drive-strength = <10>;
1099 };
1100 };
1101
1102 sdc1_sleep: sdc1-sleep-state {
1103 clk-pins {
1104 pins = "sdc1_clk";
1105 bias-disable;
1106 drive-strength = <2>;
1107 };
1108
1109 cmd-pins {
1110 pins = "sdc1_cmd";
1111 bias-pull-up;
1112 drive-strength = <2>;
1113 };
1114
1115 data-pins {
1116 pins = "sdc1_data";
1117 bias-pull-up;
1118 drive-strength = <2>;
1119 };
1120 };
1121
1122 sdc2_default: sdc2-default-state {
1123 clk-pins {
1124 pins = "sdc2_clk";
1125 bias-disable;
1126 drive-strength = <16>;
1127 };
1128
1129 cmd-pins {
1130 pins = "sdc2_cmd";
1131 bias-pull-up;
1132 drive-strength = <10>;
1133 };
1134
1135 data-pins {
1136 pins = "sdc2_data";
1137 bias-pull-up;
1138 drive-strength = <10>;
1139 };
1140 };
1141
1142 sdc2_sleep: sdc2-sleep-state {
1143 clk-pins {
1144 pins = "sdc2_clk";
1145 bias-disable;
1146 drive-strength = <2>;
1147 };
1148
1149 cmd-pins {
1150 pins = "sdc2_cmd";
1151 bias-pull-up;
1152 drive-strength = <2>;
1153 };
1154
1155 data-pins {
1156 pins = "sdc2_data";
1157 bias-pull-up;
1158 drive-strength = <2>;
1159 };
1160 };
1161
1162 wcss_wlan_default: wcss-wlan-default-state {
1163 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1164 function = "wcss_wlan";
1165 drive-strength = <6>;
1166 bias-pull-up;
1167 };
1168 };
1169
1170 gcc: clock-controller@1800000 {
1171 compatible = "qcom,gcc-msm8939";
1172 reg = <0x01800000 0x80000>;
1173 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1174 <&sleep_clk>,
1175 <&mdss_dsi0_phy 1>,
1176 <&mdss_dsi0_phy 0>,
1177 <0>,
1178 <0>,
1179 <0>;
1180 clock-names = "xo",
1181 "sleep_clk",
1182 "dsi0pll",
1183 "dsi0pllbyte",
1184 "ext_mclk",
1185 "ext_pri_i2s",
1186 "ext_sec_i2s";
1187 #clock-cells = <1>;
1188 #reset-cells = <1>;
1189 #power-domain-cells = <1>;
1190 };
1191
1192 tcsr_mutex: hwlock@1905000 {
1193 compatible = "qcom,tcsr-mutex";
1194 reg = <0x01905000 0x20000>;
1195 #hwlock-cells = <1>;
1196 };
1197
1198 tcsr: syscon@1937000 {
1199 compatible = "qcom,tcsr-msm8916", "syscon";
1200 reg = <0x01937000 0x30000>;
1201 };
1202
1203 mdss: display-subsystem@1a00000 {
1204 compatible = "qcom,mdss";
1205 reg = <0x01a00000 0x1000>,
1206 <0x01ac8000 0x3000>;
1207 reg-names = "mdss_phys", "vbif_phys";
1208
1209 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1210 interrupt-controller;
1211
1212 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1213 <&gcc GCC_MDSS_AXI_CLK>,
1214 <&gcc GCC_MDSS_VSYNC_CLK>;
1215 clock-names = "iface",
1216 "bus",
1217 "vsync";
1218
1219 power-domains = <&gcc MDSS_GDSC>;
1220
1221 #address-cells = <1>;
1222 #size-cells = <1>;
1223 #interrupt-cells = <1>;
1224 ranges;
1225
1226 status = "disabled";
1227
1228 mdss_mdp: display-controller@1a01000 {
1229 compatible = "qcom,mdp5";
1230 reg = <0x01a01000 0x89000>;
1231 reg-names = "mdp_phys";
1232
1233 interrupt-parent = <&mdss>;
1234 interrupts = <0>;
1235
1236 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1237 <&gcc GCC_MDSS_AXI_CLK>,
1238 <&gcc GCC_MDSS_MDP_CLK>,
1239 <&gcc GCC_MDSS_VSYNC_CLK>;
1240 clock-names = "iface",
1241 "bus",
1242 "core",
1243 "vsync";
1244
1245 iommus = <&apps_iommu 4>;
1246
1247 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1248 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1249 interconnect-names = "mdp0-mem", "mdp1-mem";
1250
1251 ports {
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254
1255 port@0 {
1256 reg = <0>;
1257 mdss_mdp_intf1_out: endpoint {
1258 remote-endpoint = <&mdss_dsi0_in>;
1259 };
1260 };
1261
1262 port@1 {
1263 reg = <1>;
1264 mdss_mdp_intf2_out: endpoint {
1265 remote-endpoint = <&mdss_dsi1_in>;
1266 };
1267 };
1268 };
1269 };
1270
1271 mdss_dsi0: dsi@1a98000 {
1272 compatible = "qcom,msm8916-dsi-ctrl",
1273 "qcom,mdss-dsi-ctrl";
1274 reg = <0x01a98000 0x25c>;
1275 reg-names = "dsi_ctrl";
1276
1277 interrupt-parent = <&mdss>;
1278 interrupts = <4>;
1279
1280 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1281 <&gcc GCC_MDSS_AHB_CLK>,
1282 <&gcc GCC_MDSS_AXI_CLK>,
1283 <&gcc GCC_MDSS_BYTE0_CLK>,
1284 <&gcc GCC_MDSS_PCLK0_CLK>,
1285 <&gcc GCC_MDSS_ESC0_CLK>;
1286 clock-names = "mdp_core",
1287 "iface",
1288 "bus",
1289 "byte",
1290 "pixel",
1291 "core";
1292 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1293 <&gcc PCLK0_CLK_SRC>;
1294 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1295 <&mdss_dsi0_phy 1>;
1296
1297 phys = <&mdss_dsi0_phy>;
1298 status = "disabled";
1299
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302
1303 ports {
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306
1307 port@0 {
1308 reg = <0>;
1309 mdss_dsi0_in: endpoint {
1310 remote-endpoint = <&mdss_mdp_intf1_out>;
1311 };
1312 };
1313
1314 port@1 {
1315 reg = <1>;
1316 mdss_dsi0_out: endpoint {
1317 };
1318 };
1319 };
1320 };
1321
1322 mdss_dsi0_phy: phy@1a98300 {
1323 compatible = "qcom,dsi-phy-28nm-lp";
1324 reg = <0x01a98300 0xd4>,
1325 <0x01a98500 0x280>,
1326 <0x01a98780 0x30>;
1327 reg-names = "dsi_pll",
1328 "dsi_phy",
1329 "dsi_phy_regulator";
1330
1331 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1332 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1333 clock-names = "iface", "ref";
1334
1335 #clock-cells = <1>;
1336 #phy-cells = <0>;
1337 status = "disabled";
1338 };
1339
1340 mdss_dsi1: dsi@1aa0000 {
1341 compatible = "qcom,msm8916-dsi-ctrl",
1342 "qcom,mdss-dsi-ctrl";
1343 reg = <0x01aa0000 0x25c>;
1344 reg-names = "dsi_ctrl";
1345
1346 interrupt-parent = <&mdss>;
1347 interrupts = <5>;
1348
1349 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1350 <&gcc GCC_MDSS_AHB_CLK>,
1351 <&gcc GCC_MDSS_AXI_CLK>,
1352 <&gcc GCC_MDSS_BYTE1_CLK>,
1353 <&gcc GCC_MDSS_PCLK1_CLK>,
1354 <&gcc GCC_MDSS_ESC1_CLK>;
1355 clock-names = "mdp_core",
1356 "iface",
1357 "bus",
1358 "byte",
1359 "pixel",
1360 "core";
1361 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1362 <&gcc PCLK1_CLK_SRC>;
1363 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1364 <&mdss_dsi0_phy 1>;
1365 phys = <&mdss_dsi1_phy>;
1366 status = "disabled";
1367
1368 ports {
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1371
1372 port@0 {
1373 reg = <0>;
1374 mdss_dsi1_in: endpoint {
1375 remote-endpoint = <&mdss_mdp_intf2_out>;
1376 };
1377 };
1378
1379 port@1 {
1380 reg = <1>;
1381 mdss_dsi1_out: endpoint {
1382 };
1383 };
1384 };
1385 };
1386
1387 mdss_dsi1_phy: phy@1aa0300 {
1388 compatible = "qcom,dsi-phy-28nm-lp";
1389 reg = <0x01aa0300 0xd4>,
1390 <0x01aa0500 0x280>,
1391 <0x01aa0780 0x30>;
1392 reg-names = "dsi_pll",
1393 "dsi_phy",
1394 "dsi_phy_regulator";
1395
1396 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1397 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1398 clock-names = "iface", "ref";
1399
1400 #clock-cells = <1>;
1401 #phy-cells = <0>;
1402 status = "disabled";
1403 };
1404 };
1405
1406 gpu: gpu@1c00000 {
1407 compatible = "qcom,adreno-405.0", "qcom,adreno";
1408 reg = <0x01c00000 0x10000>;
1409 reg-names = "kgsl_3d0_reg_memory";
1410 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1411 interrupt-names = "kgsl_3d0_irq";
1412 clock-names = "core",
1413 "iface",
1414 "mem",
1415 "mem_iface",
1416 "alt_mem_iface",
1417 "gfx3d",
1418 "rbbmtimer";
1419 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1420 <&gcc GCC_OXILI_AHB_CLK>,
1421 <&gcc GCC_OXILI_GMEM_CLK>,
1422 <&gcc GCC_BIMC_GFX_CLK>,
1423 <&gcc GCC_BIMC_GPU_CLK>,
1424 <&gcc GFX3D_CLK_SRC>,
1425 <&gcc GCC_OXILI_TIMER_CLK>;
1426 power-domains = <&gcc OXILI_GDSC>;
1427 operating-points-v2 = <&opp_table>;
1428 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1429 #cooling-cells = <2>;
1430
1431 status = "disabled";
1432
1433 opp_table: opp-table {
1434 compatible = "operating-points-v2";
1435
1436 opp-550000000 {
1437 opp-hz = /bits/ 64 <550000000>;
1438 };
1439
1440 opp-465000000 {
1441 opp-hz = /bits/ 64 <465000000>;
1442 };
1443
1444 opp-400000000 {
1445 opp-hz = /bits/ 64 <400000000>;
1446 };
1447
1448 opp-220000000 {
1449 opp-hz = /bits/ 64 <220000000>;
1450 };
1451
1452 opp-19200000 {
1453 opp-hz = /bits/ 64 <19200000>;
1454 };
1455 };
1456 };
1457
1458 apps_iommu: iommu@1ef0000 {
1459 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1460 reg = <0x01ef0000 0x3000>;
1461 ranges = <0 0x01e20000 0x20000>;
1462 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1463 <&gcc GCC_APSS_TCU_CLK>;
1464 clock-names = "iface", "bus";
1465 #address-cells = <1>;
1466 #size-cells = <1>;
1467 #iommu-cells = <1>;
1468 qcom,iommu-secure-id = <17>;
1469
1470 /* mdp_0: */
1471 iommu-ctx@4000 {
1472 compatible = "qcom,msm-iommu-v1-ns";
1473 reg = <0x4000 0x1000>;
1474 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1475 };
1476
1477 /* venus_ns: */
1478 iommu-ctx@5000 {
1479 compatible = "qcom,msm-iommu-v1-sec";
1480 reg = <0x5000 0x1000>;
1481 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1482 };
1483 };
1484
1485 gpu_iommu: iommu@1f08000 {
1486 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1487 ranges = <0 0x1f08000 0x10000>;
1488 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1489 <&gcc GCC_GFX_TCU_CLK>,
1490 <&gcc GCC_GFX_TBU_CLK>;
1491 clock-names = "iface", "bus", "tbu";
1492 #address-cells = <1>;
1493 #size-cells = <1>;
1494 #iommu-cells = <1>;
1495 qcom,iommu-secure-id = <18>;
1496
1497 /* gfx3d_user: */
1498 iommu-ctx@1000 {
1499 compatible = "qcom,msm-iommu-v1-ns";
1500 reg = <0x1000 0x1000>;
1501 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1502 };
1503
1504 /* gfx3d_priv: */
1505 iommu-ctx@2000 {
1506 compatible = "qcom,msm-iommu-v1-ns";
1507 reg = <0x2000 0x1000>;
1508 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1509 };
1510 };
1511
1512 spmi_bus: spmi@200f000 {
1513 compatible = "qcom,spmi-pmic-arb";
1514 reg = <0x0200f000 0x001000>,
1515 <0x02400000 0x400000>,
1516 <0x02c00000 0x400000>,
1517 <0x03800000 0x200000>,
1518 <0x0200a000 0x002100>;
1519 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1520 interrupt-names = "periph_irq";
1521 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1522 qcom,ee = <0>;
1523 qcom,channel = <0>;
1524 #address-cells = <2>;
1525 #size-cells = <0>;
1526 interrupt-controller;
1527 #interrupt-cells = <4>;
1528 };
1529
1530 bam_dmux_dma: dma-controller@4044000 {
1531 compatible = "qcom,bam-v1.7.0";
1532 reg = <0x04044000 0x19000>;
1533 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1534 #dma-cells = <1>;
1535 qcom,ee = <0>;
1536
1537 num-channels = <6>;
1538 qcom,num-ees = <1>;
1539 qcom,powered-remotely;
1540
1541 status = "disabled";
1542 };
1543
1544 mpss: remoteproc@4080000 {
1545 compatible = "qcom,msm8916-mss-pil";
1546 reg = <0x04080000 0x100>, <0x04020000 0x040>;
1547 reg-names = "qdsp6", "rmb";
1548 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1549 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1551 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1552 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wdog",
1554 "fatal",
1555 "ready",
1556 "handover",
1557 "stop-ack";
1558 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1559 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1560 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1561 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1562 clock-names = "iface",
1563 "bus",
1564 "mem",
1565 "xo";
1566 power-domains = <&rpmpd MSM8939_VDDMDCX>,
1567 <&rpmpd MSM8939_VDDMX>;
1568 power-domain-names = "cx", "mx";
1569 qcom,smem-states = <&hexagon_smp2p_out 0>;
1570 qcom,smem-state-names = "stop";
1571 resets = <&scm 0>;
1572 reset-names = "mss_restart";
1573 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1574 status = "disabled";
1575
1576 bam_dmux: bam-dmux {
1577 compatible = "qcom,bam-dmux";
1578
1579 interrupt-parent = <&hexagon_smsm>;
1580 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1581 interrupt-names = "pc", "pc-ack";
1582
1583 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1584 qcom,smem-state-names = "pc", "pc-ack";
1585
1586 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1587 dma-names = "tx", "rx";
1588
1589 status = "disabled";
1590 };
1591
1592 mba {
1593 memory-region = <&mba_mem>;
1594 };
1595
1596 mpss {
1597 memory-region = <&mpss_mem>;
1598 };
1599
1600 smd-edge {
1601 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1602
1603 qcom,smd-edge = <0>;
1604 mboxes = <&apcs1_mbox 12>;
1605 qcom,remote-pid = <1>;
1606
1607 label = "hexagon";
1608
1609 apr: apr {
1610 compatible = "qcom,apr-v2";
1611 qcom,smd-channels = "apr_audio_svc";
1612 qcom,domain = <APR_DOMAIN_ADSP>;
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 status = "disabled";
1616
1617 q6core: service@3 {
1618 compatible = "qcom,q6core";
1619 reg = <APR_SVC_ADSP_CORE>;
1620 };
1621
1622 q6afe: service@4 {
1623 compatible = "qcom,q6afe";
1624 reg = <APR_SVC_AFE>;
1625
1626 q6afedai: dais {
1627 compatible = "qcom,q6afe-dais";
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1630 #sound-dai-cells = <1>;
1631 };
1632 };
1633
1634 q6asm: service@7 {
1635 compatible = "qcom,q6asm";
1636 reg = <APR_SVC_ASM>;
1637
1638 q6asmdai: dais {
1639 compatible = "qcom,q6asm-dais";
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642 #sound-dai-cells = <1>;
1643 };
1644 };
1645
1646 q6adm: service@8 {
1647 compatible = "qcom,q6adm";
1648 reg = <APR_SVC_ADM>;
1649
1650 q6routing: routing {
1651 compatible = "qcom,q6adm-routing";
1652 #sound-dai-cells = <0>;
1653 };
1654 };
1655 };
1656 };
1657 };
1658
1659 sound: sound@7702000 {
1660 compatible = "qcom,apq8016-sbc-sndcard";
1661 reg = <0x07702000 0x4>,
1662 <0x07702004 0x4>;
1663 reg-names = "mic-iomux", "spkr-iomux";
1664 status = "disabled";
1665 };
1666
1667 lpass: audio-controller@7708000 {
1668 compatible = "qcom,apq8016-lpass-cpu";
1669 reg = <0x07708000 0x10000>;
1670 reg-names = "lpass-lpaif";
1671 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-names = "lpass-irq-lpaif";
1673 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1674 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1675 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1676 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1677 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1678 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1679 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1680 clock-names = "ahbix-clk",
1681 "mi2s-bit-clk0",
1682 "mi2s-bit-clk1",
1683 "mi2s-bit-clk2",
1684 "mi2s-bit-clk3",
1685 "pcnoc-mport-clk",
1686 "pcnoc-sway-clk";
1687 #sound-dai-cells = <1>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1690 status = "disabled";
1691 };
1692
1693 lpass_codec: audio-codec@771c000 {
1694 compatible = "qcom,msm8916-wcd-digital-codec";
1695 reg = <0x0771c000 0x400>;
1696 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1697 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1698 clock-names = "ahbix-clk", "mclk";
1699 #sound-dai-cells = <1>;
1700 status = "disabled";
1701 };
1702
1703 sdhc_1: mmc@7824900 {
1704 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1705 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1706 reg-names = "hc", "core";
1707
1708 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 interrupt-names = "hc_irq", "pwr_irq";
1711 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1712 <&gcc GCC_SDCC1_APPS_CLK>,
1713 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1714 clock-names = "iface", "core", "xo";
1715 resets = <&gcc GCC_SDCC1_BCR>;
1716 pinctrl-0 = <&sdc1_default>;
1717 pinctrl-1 = <&sdc1_sleep>;
1718 pinctrl-names = "default", "sleep";
1719 mmc-ddr-1_8v;
1720 bus-width = <8>;
1721 non-removable;
1722 status = "disabled";
1723 };
1724
1725 sdhc_2: mmc@7864900 {
1726 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1727 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1728 reg-names = "hc", "core";
1729
1730 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1732 interrupt-names = "hc_irq", "pwr_irq";
1733 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1734 <&gcc GCC_SDCC2_APPS_CLK>,
1735 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1736 clock-names = "iface", "core", "xo";
1737 resets = <&gcc GCC_SDCC2_BCR>;
1738 pinctrl-0 = <&sdc2_default>;
1739 pinctrl-1 = <&sdc2_sleep>;
1740 pinctrl-names = "default", "sleep";
1741 bus-width = <4>;
1742 status = "disabled";
1743 };
1744
1745 blsp_dma: dma-controller@7884000 {
1746 compatible = "qcom,bam-v1.7.0";
1747 reg = <0x07884000 0x23000>;
1748 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "bam_clk";
1751 #dma-cells = <1>;
1752 qcom,ee = <0>;
1753 qcom,controlled-remotely;
1754 };
1755
1756 blsp_uart1: serial@78af000 {
1757 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1758 reg = <0x078af000 0x200>;
1759 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1761 clock-names = "core", "iface";
1762 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1763 dma-names = "tx", "rx";
1764 pinctrl-0 = <&blsp_uart1_default>;
1765 pinctrl-1 = <&blsp_uart1_sleep>;
1766 pinctrl-names = "default", "sleep";
1767 status = "disabled";
1768 };
1769
1770 blsp_uart2: serial@78b0000 {
1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1772 reg = <0x078b0000 0x200>;
1773 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", "iface";
1776 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1777 dma-names = "tx", "rx";
1778 pinctrl-0 = <&blsp_uart2_default>;
1779 pinctrl-1 = <&blsp_uart2_sleep>;
1780 pinctrl-names = "default", "sleep";
1781 status = "disabled";
1782 };
1783
1784 blsp_i2c1: i2c@78b5000 {
1785 compatible = "qcom,i2c-qup-v2.2.1";
1786 reg = <0x078b5000 0x500>;
1787 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1788 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1789 <&gcc GCC_BLSP1_AHB_CLK>;
1790 clock-names = "core", "iface";
1791 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1792 dma-names = "tx", "rx";
1793 pinctrl-0 = <&blsp_i2c1_default>;
1794 pinctrl-1 = <&blsp_i2c1_sleep>;
1795 pinctrl-names = "default", "sleep";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 status = "disabled";
1799 };
1800
1801 blsp_spi1: spi@78b5000 {
1802 compatible = "qcom,spi-qup-v2.2.1";
1803 reg = <0x078b5000 0x500>;
1804 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1805 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1806 <&gcc GCC_BLSP1_AHB_CLK>;
1807 clock-names = "core", "iface";
1808 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1809 dma-names = "tx", "rx";
1810 pinctrl-0 = <&blsp_spi1_default>;
1811 pinctrl-1 = <&blsp_spi1_sleep>;
1812 pinctrl-names = "default", "sleep";
1813 #address-cells = <1>;
1814 #size-cells = <0>;
1815 status = "disabled";
1816 };
1817
1818 blsp_i2c2: i2c@78b6000 {
1819 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x078b6000 0x500>;
1821 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1823 <&gcc GCC_BLSP1_AHB_CLK>;
1824 clock-names = "core", "iface";
1825 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1826 dma-names = "tx", "rx";
1827 pinctrl-0 = <&blsp_i2c2_default>;
1828 pinctrl-1 = <&blsp_i2c2_sleep>;
1829 pinctrl-names = "default", "sleep";
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1832 status = "disabled";
1833 };
1834
1835 blsp_spi2: spi@78b6000 {
1836 compatible = "qcom,spi-qup-v2.2.1";
1837 reg = <0x078b6000 0x500>;
1838 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1840 <&gcc GCC_BLSP1_AHB_CLK>;
1841 clock-names = "core", "iface";
1842 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1843 dma-names = "tx", "rx";
1844 pinctrl-0 = <&blsp_spi2_default>;
1845 pinctrl-1 = <&blsp_spi2_sleep>;
1846 pinctrl-names = "default", "sleep";
1847 #address-cells = <1>;
1848 #size-cells = <0>;
1849 status = "disabled";
1850 };
1851
1852 blsp_i2c3: i2c@78b7000 {
1853 compatible = "qcom,i2c-qup-v2.2.1";
1854 reg = <0x078b7000 0x500>;
1855 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1856 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1857 <&gcc GCC_BLSP1_AHB_CLK>;
1858 clock-names = "core", "iface";
1859 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1860 dma-names = "tx", "rx";
1861 pinctrl-0 = <&blsp_i2c3_default>;
1862 pinctrl-1 = <&blsp_i2c3_sleep>;
1863 pinctrl-names = "default", "sleep";
1864 #address-cells = <1>;
1865 #size-cells = <0>;
1866 status = "disabled";
1867 };
1868
1869 blsp_spi3: spi@78b7000 {
1870 compatible = "qcom,spi-qup-v2.2.1";
1871 reg = <0x078b7000 0x500>;
1872 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1873 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1874 <&gcc GCC_BLSP1_AHB_CLK>;
1875 clock-names = "core", "iface";
1876 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1877 dma-names = "tx", "rx";
1878 pinctrl-0 = <&blsp_spi3_default>;
1879 pinctrl-1 = <&blsp_spi3_sleep>;
1880 pinctrl-names = "default", "sleep";
1881 #address-cells = <1>;
1882 #size-cells = <0>;
1883 status = "disabled";
1884 };
1885
1886 blsp_i2c4: i2c@78b8000 {
1887 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x078b8000 0x500>;
1889 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1890 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1891 <&gcc GCC_BLSP1_AHB_CLK>;
1892 clock-names = "core", "iface";
1893 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1894 dma-names = "tx", "rx";
1895 pinctrl-0 = <&blsp_i2c4_default>;
1896 pinctrl-1 = <&blsp_i2c4_sleep>;
1897 pinctrl-names = "default", "sleep";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1900 status = "disabled";
1901 };
1902
1903 blsp_spi4: spi@78b8000 {
1904 compatible = "qcom,spi-qup-v2.2.1";
1905 reg = <0x078b8000 0x500>;
1906 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1907 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1908 <&gcc GCC_BLSP1_AHB_CLK>;
1909 clock-names = "core", "iface";
1910 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1911 dma-names = "tx", "rx";
1912 pinctrl-0 = <&blsp_spi4_default>;
1913 pinctrl-1 = <&blsp_spi4_sleep>;
1914 pinctrl-names = "default", "sleep";
1915 #address-cells = <1>;
1916 #size-cells = <0>;
1917 status = "disabled";
1918 };
1919
1920 blsp_i2c5: i2c@78b9000 {
1921 compatible = "qcom,i2c-qup-v2.2.1";
1922 reg = <0x078b9000 0x500>;
1923 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1924 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1925 <&gcc GCC_BLSP1_AHB_CLK>;
1926 clock-names = "core", "iface";
1927 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1928 dma-names = "tx", "rx";
1929 pinctrl-0 = <&blsp_i2c5_default>;
1930 pinctrl-1 = <&blsp_i2c5_sleep>;
1931 pinctrl-names = "default", "sleep";
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 status = "disabled";
1935 };
1936
1937 blsp_spi5: spi@78b9000 {
1938 compatible = "qcom,spi-qup-v2.2.1";
1939 reg = <0x078b9000 0x500>;
1940 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1941 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1942 <&gcc GCC_BLSP1_AHB_CLK>;
1943 clock-names = "core", "iface";
1944 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1945 dma-names = "tx", "rx";
1946 pinctrl-0 = <&blsp_spi5_default>;
1947 pinctrl-1 = <&blsp_spi5_sleep>;
1948 pinctrl-names = "default", "sleep";
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1951 status = "disabled";
1952 };
1953
1954 blsp_i2c6: i2c@78ba000 {
1955 compatible = "qcom,i2c-qup-v2.2.1";
1956 reg = <0x078ba000 0x500>;
1957 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1959 <&gcc GCC_BLSP1_AHB_CLK>;
1960 clock-names = "core", "iface";
1961 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1962 dma-names = "tx", "rx";
1963 pinctrl-0 = <&blsp_i2c6_default>;
1964 pinctrl-1 = <&blsp_i2c6_sleep>;
1965 pinctrl-names = "default", "sleep";
1966 #address-cells = <1>;
1967 #size-cells = <0>;
1968 status = "disabled";
1969 };
1970
1971 blsp_spi6: spi@78ba000 {
1972 compatible = "qcom,spi-qup-v2.2.1";
1973 reg = <0x078ba000 0x500>;
1974 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1975 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1976 <&gcc GCC_BLSP1_AHB_CLK>;
1977 clock-names = "core", "iface";
1978 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1979 dma-names = "tx", "rx";
1980 pinctrl-0 = <&blsp_spi6_default>;
1981 pinctrl-1 = <&blsp_spi6_sleep>;
1982 pinctrl-names = "default", "sleep";
1983 #address-cells = <1>;
1984 #size-cells = <0>;
1985 status = "disabled";
1986 };
1987
1988 usb: usb@78d9000 {
1989 compatible = "qcom,ci-hdrc";
1990 reg = <0x078d9000 0x200>,
1991 <0x078d9200 0x200>;
1992 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1994 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1995 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1996 clock-names = "iface", "core";
1997 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1998 assigned-clock-rates = <80000000>;
1999 resets = <&gcc GCC_USB_HS_BCR>;
2000 reset-names = "core";
2001 #reset-cells = <1>;
2002 phy_type = "ulpi";
2003 dr_mode = "otg";
2004 adp-disable;
2005 hnp-disable;
2006 srp-disable;
2007 ahb-burst-config = <0>;
2008 phy-names = "usb-phy";
2009 phys = <&usb_hs_phy>;
2010 status = "disabled";
2011
2012 ulpi {
2013 usb_hs_phy: phy {
2014 compatible = "qcom,usb-hs-phy-msm8916",
2015 "qcom,usb-hs-phy";
2016 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2017 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2018 clock-names = "ref", "sleep";
2019 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2020 reset-names = "phy", "por";
2021 #phy-cells = <0>;
2022 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2023 <0x1 0x6b>,
2024 <0x2 0x24>,
2025 <0x3 0x13>;
2026 };
2027 };
2028 };
2029
2030 wcnss: remoteproc@a204000 {
2031 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2032 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2033 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2034 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2035 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2036 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2037 interrupt-names = "wdog",
2038 "fatal",
2039 "ready",
2040 "handover",
2041 "stop-ack";
2042 reg = <0x0a204000 0x2000>,
2043 <0x0a202000 0x1000>,
2044 <0x0a21b000 0x3000>;
2045 reg-names = "ccu", "dxe", "pmu";
2046
2047 memory-region = <&wcnss_mem>;
2048
2049 power-domains = <&rpmpd MSM8939_VDDCX>,
2050 <&rpmpd MSM8939_VDDMX>;
2051 power-domain-names = "cx", "mx";
2052
2053 qcom,smem-states = <&wcnss_smp2p_out 0>;
2054 qcom,smem-state-names = "stop";
2055
2056 pinctrl-names = "default";
2057 pinctrl-0 = <&wcss_wlan_default>;
2058
2059 status = "disabled";
2060
2061 wcnss_iris: iris {
2062 /* Separate chip, compatible is board-specific */
2063 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2064 clock-names = "xo";
2065 };
2066
2067 smd-edge {
2068 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2069 mboxes = <&apcs1_mbox 17>;
2070 qcom,smd-edge = <6>;
2071 qcom,remote-pid = <4>;
2072
2073 label = "pronto";
2074
2075 wcnss {
2076 compatible = "qcom,wcnss";
2077 qcom,smd-channels = "WCNSS_CTRL";
2078
2079 qcom,mmio = <&wcnss>;
2080
2081 wcnss_bt: bluetooth {
2082 compatible = "qcom,wcnss-bt";
2083 };
2084
2085 wcnss_wifi: wifi {
2086 compatible = "qcom,wcnss-wlan";
2087
2088 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2090 interrupt-names = "tx", "rx";
2091
2092 qcom,smem-states = <&apps_smsm 10>,
2093 <&apps_smsm 9>;
2094 qcom,smem-state-names = "tx-enable",
2095 "tx-rings-empty";
2096 };
2097 };
2098 };
2099 };
2100
2101 intc: interrupt-controller@b000000 {
2102 compatible = "qcom,msm-qgic2";
2103 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2104 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2105 interrupt-controller;
2106 #interrupt-cells = <3>;
2107 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2108 };
2109
2110 apcs1_mbox: mailbox@b011000 {
2111 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2112 reg = <0x0b011000 0x1000>;
2113 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2114 clock-names = "pll", "aux", "ref";
2115 #clock-cells = <0>;
2116 assigned-clocks = <&apcs2>;
2117 assigned-clock-rates = <297600000>;
2118 #mbox-cells = <1>;
2119 };
2120
2121 a53pll_c1: clock@b016000 {
2122 compatible = "qcom,msm8939-a53pll";
2123 reg = <0x0b016000 0x40>;
2124 #clock-cells = <0>;
2125 };
2126
2127 acc0: clock-controller@b088000 {
2128 compatible = "qcom,kpss-acc-v2";
2129 reg = <0x0b088000 0x1000>;
2130 };
2131
2132 saw0: power-manager@b089000 {
2133 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2134 reg = <0x0b089000 0x1000>;
2135 };
2136
2137 acc1: clock-controller@b098000 {
2138 compatible = "qcom,kpss-acc-v2";
2139 reg = <0x0b098000 0x1000>;
2140 };
2141
2142 saw1: power-manager@b099000 {
2143 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2144 reg = <0x0b099000 0x1000>;
2145 };
2146
2147 acc2: clock-controller@b0a8000 {
2148 compatible = "qcom,kpss-acc-v2";
2149 reg = <0x0b0a8000 0x1000>;
2150 };
2151
2152 saw2: power-manager@b0a9000 {
2153 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2154 reg = <0x0b0a9000 0x1000>;
2155 };
2156
2157 acc3: clock-controller@b0b8000 {
2158 compatible = "qcom,kpss-acc-v2";
2159 reg = <0x0b0b8000 0x1000>;
2160 };
2161
2162 saw3: power-manager@b0b9000 {
2163 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2164 reg = <0x0b0b9000 0x1000>;
2165 };
2166
2167 apcs0_mbox: mailbox@b111000 {
2168 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2169 reg = <0x0b111000 0x1000>;
2170 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2171 clock-names = "pll", "aux", "ref";
2172 #clock-cells = <0>;
2173 #mbox-cells = <1>;
2174 };
2175
2176 a53pll_c0: clock@b116000 {
2177 compatible = "qcom,msm8939-a53pll";
2178 reg = <0x0b116000 0x40>;
2179 #clock-cells = <0>;
2180 };
2181
2182 timer@b120000 {
2183 compatible = "arm,armv7-timer-mem";
2184 reg = <0x0b120000 0x1000>;
2185 #address-cells = <1>;
2186 #size-cells = <1>;
2187 ranges;
2188 /* Necessary because firmware does not configure this correctly */
2189 clock-frequency = <19200000>;
2190
2191 frame@b121000 {
2192 reg = <0x0b121000 0x1000>,
2193 <0x0b122000 0x1000>;
2194 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2195 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2196 frame-number = <0>;
2197 };
2198
2199 frame@b123000 {
2200 reg = <0x0b123000 0x1000>;
2201 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2202 frame-number = <1>;
2203 status = "disabled";
2204 };
2205
2206 frame@b124000 {
2207 reg = <0x0b124000 0x1000>;
2208 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2209 frame-number = <2>;
2210 status = "disabled";
2211 };
2212
2213 frame@b125000 {
2214 reg = <0x0b125000 0x1000>;
2215 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2216 frame-number = <3>;
2217 status = "disabled";
2218 };
2219
2220 frame@b126000 {
2221 reg = <0x0b126000 0x1000>;
2222 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2223 frame-number = <4>;
2224 status = "disabled";
2225 };
2226
2227 frame@b127000 {
2228 reg = <0x0b127000 0x1000>;
2229 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2230 frame-number = <5>;
2231 status = "disabled";
2232 };
2233
2234 frame@b128000 {
2235 reg = <0x0b128000 0x1000>;
2236 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2237 frame-number = <6>;
2238 status = "disabled";
2239 };
2240 };
2241
2242 acc4: clock-controller@b188000 {
2243 compatible = "qcom,kpss-acc-v2";
2244 reg = <0x0b188000 0x1000>;
2245 };
2246
2247 saw4: power-manager@b189000 {
2248 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2249 reg = <0x0b189000 0x1000>;
2250 };
2251
2252 acc5: clock-controller@b198000 {
2253 compatible = "qcom,kpss-acc-v2";
2254 reg = <0x0b198000 0x1000>;
2255 };
2256
2257 saw5: power-manager@b199000 {
2258 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2259 reg = <0x0b199000 0x1000>;
2260 };
2261
2262 acc6: clock-controller@b1a8000 {
2263 compatible = "qcom,kpss-acc-v2";
2264 reg = <0x0b1a8000 0x1000>;
2265 };
2266
2267 saw6: power-manager@b1a9000 {
2268 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2269 reg = <0x0b1a9000 0x1000>;
2270 };
2271
2272 acc7: clock-controller@b1b8000 {
2273 compatible = "qcom,kpss-acc-v2";
2274 reg = <0x0b1b8000 0x1000>;
2275 };
2276
2277 saw7: power-manager@b1b9000 {
2278 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2279 reg = <0x0b1b9000 0x1000>;
2280 };
2281
2282 a53pll_cci: clock@b1d0000 {
2283 compatible = "qcom,msm8939-a53pll";
2284 reg = <0x0b1d0000 0x40>;
2285 #clock-cells = <0>;
2286 };
2287
2288 apcs2: mailbox@b1d1000 {
2289 compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2290 reg = <0x0b1d1000 0x1000>;
2291 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2292 clock-names = "pll", "aux", "ref";
2293 #clock-cells = <0>;
2294 #mbox-cells = <1>;
2295 };
2296 };
2297
2298 thermal_zones: thermal-zones {
2299 cpu0-thermal {
2300 polling-delay-passive = <250>;
2301
2302 thermal-sensors = <&tsens 5>;
2303
2304 trips {
2305 cpu0_alert: trip0 {
2306 temperature = <75000>;
2307 hysteresis = <2000>;
2308 type = "passive";
2309 };
2310
2311 cpu0_crit: trip1 {
2312 temperature = <115000>;
2313 hysteresis = <0>;
2314 type = "critical";
2315 };
2316 };
2317
2318 cooling-maps {
2319 map0 {
2320 trip = <&cpu0_alert>;
2321 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2322 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2323 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2324 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2325 };
2326 };
2327 };
2328
2329 cpu1-thermal {
2330 polling-delay-passive = <250>;
2331
2332 thermal-sensors = <&tsens 6>;
2333
2334 trips {
2335 cpu1_alert: trip0 {
2336 temperature = <75000>;
2337 hysteresis = <2000>;
2338 type = "passive";
2339 };
2340
2341 cpu1_crit: trip1 {
2342 temperature = <110000>;
2343 hysteresis = <2000>;
2344 type = "critical";
2345 };
2346 };
2347
2348 cooling-maps {
2349 map0 {
2350 trip = <&cpu1_alert>;
2351 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2352 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2353 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2354 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2355 };
2356 };
2357 };
2358
2359 cpu2-thermal {
2360 polling-delay-passive = <250>;
2361
2362 thermal-sensors = <&tsens 7>;
2363
2364 trips {
2365 cpu2_alert: trip0 {
2366 temperature = <75000>;
2367 hysteresis = <2000>;
2368 type = "passive";
2369 };
2370
2371 cpu2_crit: trip1 {
2372 temperature = <110000>;
2373 hysteresis = <2000>;
2374 type = "critical";
2375 };
2376 };
2377
2378 cooling-maps {
2379 map0 {
2380 trip = <&cpu2_alert>;
2381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2384 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2385 };
2386 };
2387 };
2388
2389 cpu3-thermal {
2390 polling-delay-passive = <250>;
2391
2392 thermal-sensors = <&tsens 8>;
2393
2394 trips {
2395 cpu3_alert: trip0 {
2396 temperature = <75000>;
2397 hysteresis = <2000>;
2398 type = "passive";
2399 };
2400
2401 cpu3_crit: trip1 {
2402 temperature = <110000>;
2403 hysteresis = <2000>;
2404 type = "critical";
2405 };
2406 };
2407
2408 cooling-maps {
2409 map0 {
2410 trip = <&cpu3_alert>;
2411 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2412 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2413 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2414 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2415 };
2416 };
2417 };
2418
2419 cpu4567-thermal {
2420 polling-delay-passive = <250>;
2421
2422 thermal-sensors = <&tsens 9>;
2423
2424 trips {
2425 cpu4567_alert: trip0 {
2426 temperature = <75000>;
2427 hysteresis = <2000>;
2428 type = "passive";
2429 };
2430
2431 cpu4567_crit: trip1 {
2432 temperature = <110000>;
2433 hysteresis = <2000>;
2434 type = "critical";
2435 };
2436 };
2437
2438 cooling-maps {
2439 map0 {
2440 trip = <&cpu4567_alert>;
2441 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2442 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2443 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2445 };
2446 };
2447 };
2448
2449 gpu-thermal {
2450 polling-delay-passive = <250>;
2451
2452 thermal-sensors = <&tsens 3>;
2453
2454 cooling-maps {
2455 map0 {
2456 trip = <&gpu_alert0>;
2457 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2458 };
2459 };
2460
2461 trips {
2462 gpu_alert0: trip-point0 {
2463 temperature = <75000>;
2464 hysteresis = <2000>;
2465 type = "passive";
2466 };
2467
2468 gpu_crit: gpu-crit {
2469 temperature = <95000>;
2470 hysteresis = <2000>;
2471 type = "critical";
2472 };
2473 };
2474 };
2475
2476 modem1-thermal {
2477 polling-delay-passive = <250>;
2478
2479 thermal-sensors = <&tsens 0>;
2480
2481 trips {
2482 modem1_alert0: trip-point0 {
2483 temperature = <85000>;
2484 hysteresis = <2000>;
2485 type = "hot";
2486 };
2487 };
2488 };
2489
2490 modem2-thermal {
2491 polling-delay-passive = <250>;
2492
2493 thermal-sensors = <&tsens 2>;
2494
2495 trips {
2496 modem2_alert0: trip-point0 {
2497 temperature = <85000>;
2498 hysteresis = <2000>;
2499 type = "hot";
2500 };
2501 };
2502 };
2503
2504 camera-thermal {
2505 polling-delay-passive = <250>;
2506
2507 thermal-sensors = <&tsens 1>;
2508
2509 trips {
2510 cam_alert0: trip-point0 {
2511 temperature = <75000>;
2512 hysteresis = <2000>;
2513 type = "hot";
2514 };
2515 };
2516 };
2517 };
2518
2519 timer {
2520 compatible = "arm,armv8-timer";
2521 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2522 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2523 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2524 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2525 };
2526 };
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