1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
3
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen { };
21
22 clocks {
23 sleep_clk: sleep-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <32768>;
27 };
28
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
33 clock-output-names = "xo";
34 };
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 CPU0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53";
44 reg = <0x0>;
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 next-level-cache = <&L2_0>;
48 #cooling-cells = <2>;
49 };
50
51 CPU1: cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a53";
54 reg = <0x1>;
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
59 };
60
61 CPU2: cpu@2 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a53";
64 reg = <0x2>;
65 enable-method = "psci";
66 capacity-dmips-mhz = <1024>;
67 next-level-cache = <&L2_0>;
68 #cooling-cells = <2>;
69 };
70
71 CPU3: cpu@3 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a53";
74 reg = <0x3>;
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
78 #cooling-cells = <2>;
79 };
80
81 CPU4: cpu@100 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 reg = <0x100>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <1024>;
87 next-level-cache = <&L2_1>;
88 #cooling-cells = <2>;
89 };
90
91 CPU5: cpu@101 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a53";
94 reg = <0x101>;
95 enable-method = "psci";
96 capacity-dmips-mhz = <1024>;
97 next-level-cache = <&L2_1>;
98 #cooling-cells = <2>;
99 };
100
101 CPU6: cpu@102 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a53";
104 reg = <0x102>;
105 enable-method = "psci";
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&L2_1>;
108 #cooling-cells = <2>;
109 };
110
111 CPU7: cpu@103 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a53";
114 reg = <0x103>;
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
117 next-level-cache = <&L2_1>;
118 #cooling-cells = <2>;
119 };
120
121 cpu-map {
122 cluster0 {
123 core0 {
124 cpu = <&CPU0>;
125 };
126 core1 {
127 cpu = <&CPU1>;
128 };
129 core2 {
130 cpu = <&CPU2>;
131 };
132 core3 {
133 cpu = <&CPU3>;
134 };
135 };
136
137 cluster1 {
138 core0 {
139 cpu = <&CPU4>;
140 };
141 core1 {
142 cpu = <&CPU5>;
143 };
144 core2 {
145 cpu = <&CPU6>;
146 };
147 core3 {
148 cpu = <&CPU7>;
149 };
150 };
151 };
152
153 L2_0: l2-cache-0 {
154 compatible = "cache";
155 cache-level = <2>;
156 cache-unified;
157 };
158
159 L2_1: l2-cache-1 {
160 compatible = "cache";
161 cache-level = <2>;
162 cache-unified;
163 };
164 };
165
166 firmware {
167 scm: scm {
168 compatible = "qcom,scm-msm8953", "qcom,scm";
169 clocks = <&gcc GCC_CRYPTO_CLK>,
170 <&gcc GCC_CRYPTO_AXI_CLK>,
171 <&gcc GCC_CRYPTO_AHB_CLK>;
172 clock-names = "core", "bus", "iface";
173 #reset-cells = <1>;
174 };
175 };
176
177 memory@10000000 {
178 device_type = "memory";
179 /* We expect the bootloader to fill in the reg */
180 reg = <0 0x10000000 0 0>;
181 };
182
183 pmu {
184 compatible = "arm,cortex-a53-pmu";
185 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
186 };
187
188 psci {
189 compatible = "arm,psci-1.0";
190 method = "smc";
191 };
192
193 rpm: remoteproc {
194 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
195
196 smd-edge {
197 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
198 mboxes = <&apcs 0>;
199 qcom,smd-edge = <15>;
200
201 rpm_requests: rpm-requests {
202 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm";
203 qcom,smd-channels = "rpm_requests";
204
205 rpmcc: clock-controller {
206 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
207 clocks = <&xo_board>;
208 clock-names = "xo";
209 #clock-cells = <1>;
210 };
211
212 rpmpd: power-controller {
213 compatible = "qcom,msm8953-rpmpd";
214 #power-domain-cells = <1>;
215 operating-points-v2 = <&rpmpd_opp_table>;
216
217 rpmpd_opp_table: opp-table {
218 compatible = "operating-points-v2";
219
220 rpmpd_opp_ret: opp1 {
221 opp-level = <RPM_SMD_LEVEL_RETENTION>;
222 };
223
224 rpmpd_opp_ret_plus: opp2 {
225 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
226 };
227
228 rpmpd_opp_min_svs: opp3 {
229 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
230 };
231
232 rpmpd_opp_low_svs: opp4 {
233 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
234 };
235
236 rpmpd_opp_svs: opp5 {
237 opp-level = <RPM_SMD_LEVEL_SVS>;
238 };
239
240 rpmpd_opp_svs_plus: opp6 {
241 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
242 };
243
244 rpmpd_opp_nom: opp7 {
245 opp-level = <RPM_SMD_LEVEL_NOM>;
246 };
247
248 rpmpd_opp_nom_plus: opp8 {
249 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
250 };
251
252 rpmpd_opp_turbo: opp9 {
253 opp-level = <RPM_SMD_LEVEL_TURBO>;
254 };
255 };
256 };
257 };
258 };
259 };
260
261 reserved-memory {
262 #address-cells = <2>;
263 #size-cells = <2>;
264 ranges;
265
266 zap_shader_region: zap@81800000 {
267 compatible = "shared-dma-pool";
268 reg = <0x0 0x81800000 0x0 0x2000>;
269 no-map;
270 };
271
272 qseecom_mem: qseecom@85b00000 {
273 reg = <0x0 0x85b00000 0x0 0x800000>;
274 no-map;
275 };
276
277 smem_mem: smem@86300000 {
278 compatible = "qcom,smem";
279 reg = <0x0 0x86300000 0x0 0x100000>;
280 qcom,rpm-msg-ram = <&rpm_msg_ram>;
281 hwlocks = <&tcsr_mutex 3>;
282 no-map;
283 };
284
285 reserved@86400000 {
286 reg = <0x0 0x86400000 0x0 0x400000>;
287 no-map;
288 };
289
290 mpss_mem: mpss@86c00000 {
291 reg = <0x0 0x86c00000 0x0 0x6a00000>;
292 no-map;
293 };
294
295 adsp_fw_mem: adsp@8d600000 {
296 reg = <0x0 0x8d600000 0x0 0x1100000>;
297 no-map;
298 };
299
300 wcnss_fw_mem: wcnss@8e700000 {
301 reg = <0x0 0x8e700000 0x0 0x700000>;
302 no-map;
303 };
304
305 dfps_data_mem: dfps-data@90000000 {
306 reg = <0 0x90000000 0 0x1000>;
307 no-map;
308 };
309
310 cont_splash_mem: cont-splash@90001000 {
311 reg = <0x0 0x90001000 0x0 0x13ff000>;
312 no-map;
313 };
314
315 venus_mem: venus@91400000 {
316 reg = <0x0 0x91400000 0x0 0x700000>;
317 no-map;
318 };
319
320 mba_mem: mba@92000000 {
321 reg = <0x0 0x92000000 0x0 0x100000>;
322 no-map;
323 };
324
325 rmtfs@f2d00000 {
326 compatible = "qcom,rmtfs-mem";
327 reg = <0x0 0xf2d00000 0x0 0x180000>;
328 no-map;
329
330 qcom,client-id = <1>;
331 };
332 };
333
334 smp2p-adsp {
335 compatible = "qcom,smp2p";
336 qcom,smem = <443>, <429>;
337
338 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
339
340 mboxes = <&apcs 10>;
341
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <2>;
344
345 smp2p_adsp_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
348 };
349
350 smp2p_adsp_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
352
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 };
356 };
357
358 smp2p-modem {
359 compatible = "qcom,smp2p";
360 qcom,smem = <435>, <428>;
361
362 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
363
364 mboxes = <&apcs 14>;
365
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <1>;
368
369 smp2p_modem_out: master-kernel {
370 qcom,entry-name = "master-kernel";
371
372 #qcom,smem-state-cells = <1>;
373 };
374
375 smp2p_modem_in: slave-kernel {
376 qcom,entry-name = "slave-kernel";
377
378 interrupt-controller;
379 #interrupt-cells = <2>;
380 };
381 };
382
383 smp2p-wcnss {
384 compatible = "qcom,smp2p";
385 qcom,smem = <451>, <431>;
386
387 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
388
389 mboxes = <&apcs 18>;
390
391 qcom,local-pid = <0>;
392 qcom,remote-pid = <4>;
393
394 smp2p_wcnss_out: master-kernel {
395 qcom,entry-name = "master-kernel";
396
397 #qcom,smem-state-cells = <1>;
398 };
399
400 smp2p_wcnss_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
402
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406 };
407
408 smsm {
409 compatible = "qcom,smsm";
410
411 #address-cells = <1>;
412 #size-cells = <0>;
413
414 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
415
416 apps_smsm: apps@0 {
417 reg = <0>;
418
419 #qcom,smem-state-cells = <1>;
420 };
421
422 modem_smsm: modem@1 {
423 reg = <1>;
424 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
425
426 interrupt-controller;
427 #interrupt-cells = <2>;
428 };
429
430 wcnss_smsm: wcnss@6 {
431 reg = <6>;
432 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
433
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 };
437 };
438
439 soc: soc@0 {
440 #address-cells = <1>;
441 #size-cells = <1>;
442 ranges = <0 0 0 0xffffffff>;
443 compatible = "simple-bus";
444
445 rpm_msg_ram: sram@60000 {
446 compatible = "qcom,rpm-msg-ram";
447 reg = <0x00060000 0x8000>;
448 };
449
450 hsusb_phy: phy@79000 {
451 compatible = "qcom,msm8953-qusb2-phy";
452 reg = <0x00079000 0x180>;
453 #phy-cells = <0>;
454
455 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
456 <&gcc GCC_QUSB_REF_CLK>;
457 clock-names = "cfg_ahb", "ref";
458
459 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
460
461 resets = <&gcc GCC_QUSB2_PHY_BCR>;
462
463 status = "disabled";
464 };
465
466 rng@e3000 {
467 compatible = "qcom,prng";
468 reg = <0x000e3000 0x1000>;
469 clocks = <&gcc GCC_PRNG_AHB_CLK>;
470 clock-names = "core";
471 };
472
473 tsens0: thermal-sensor@4a9000 {
474 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
475 reg = <0x004a9000 0x1000>, /* TM */
476 <0x004a8000 0x1000>; /* SROT */
477 #qcom,sensors = <16>;
478 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
480 interrupt-names = "uplow", "critical";
481 #thermal-sensor-cells = <1>;
482 };
483
484 restart@4ab000 {
485 compatible = "qcom,pshold";
486 reg = <0x004ab000 0x4>;
487 };
488
489 tlmm: pinctrl@1000000 {
490 compatible = "qcom,msm8953-pinctrl";
491 reg = <0x01000000 0x300000>;
492 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
493 gpio-controller;
494 gpio-ranges = <&tlmm 0 0 142>;
495 #gpio-cells = <2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498
499 uart_console_active: uart-console-active-state {
500 pins = "gpio4", "gpio5";
501 function = "blsp_uart2";
502 drive-strength = <2>;
503 bias-disable;
504 };
505
506 uart_console_sleep: uart-console-sleep-state {
507 pins = "gpio4", "gpio5";
508 function = "blsp_uart2";
509 drive-strength = <2>;
510 bias-pull-down;
511 };
512
513 sdc1_clk_on: sdc1-clk-on-state {
514 pins = "sdc1_clk";
515 bias-disable;
516 drive-strength = <16>;
517 };
518
519 sdc1_clk_off: sdc1-clk-off-state {
520 pins = "sdc1_clk";
521 bias-disable;
522 drive-strength = <2>;
523 };
524
525 sdc1_cmd_on: sdc1-cmd-on-state {
526 pins = "sdc1_cmd";
527 bias-disable;
528 drive-strength = <10>;
529 };
530
531 sdc1_cmd_off: sdc1-cmd-off-state {
532 pins = "sdc1_cmd";
533 bias-disable;
534 drive-strength = <2>;
535 };
536
537 sdc1_data_on: sdc1-data-on-state {
538 pins = "sdc1_data";
539 bias-pull-up;
540 drive-strength = <10>;
541 };
542
543 sdc1_data_off: sdc1-data-off-state {
544 pins = "sdc1_data";
545 bias-pull-up;
546 drive-strength = <2>;
547 };
548
549 sdc1_rclk_on: sdc1-rclk-on-state {
550 pins = "sdc1_rclk";
551 bias-pull-down;
552 };
553
554 sdc1_rclk_off: sdc1-rclk-off-state {
555 pins = "sdc1_rclk";
556 bias-pull-down;
557 };
558
559 sdc2_clk_on: sdc2-clk-on-state {
560 pins = "sdc2_clk";
561 drive-strength = <16>;
562 bias-disable;
563 };
564
565 sdc2_clk_off: sdc2-clk-off-state {
566 pins = "sdc2_clk";
567 bias-disable;
568 drive-strength = <2>;
569 };
570
571 sdc2_cmd_on: sdc2-cmd-on-state {
572 pins = "sdc2_cmd";
573 bias-pull-up;
574 drive-strength = <10>;
575 };
576
577 sdc2_cmd_off: sdc2-cmd-off-state {
578 pins = "sdc2_cmd";
579 bias-pull-up;
580 drive-strength = <2>;
581 };
582
583 sdc2_data_on: sdc2-data-on-state {
584 pins = "sdc2_data";
585 bias-pull-up;
586 drive-strength = <10>;
587 };
588
589 sdc2_data_off: sdc2-data-off-state {
590 pins = "sdc2_data";
591 bias-pull-up;
592 drive-strength = <2>;
593 };
594
595 sdc2_cd_on: cd-on-state {
596 pins = "gpio133";
597 function = "gpio";
598 drive-strength = <2>;
599 bias-pull-up;
600 };
601
602 sdc2_cd_off: cd-off-state {
603 pins = "gpio133";
604 function = "gpio";
605 drive-strength = <2>;
606 bias-disable;
607 };
608
609 gpio_key_default: gpio-key-default-state {
610 pins = "gpio85";
611 function = "gpio";
612 drive-strength = <2>;
613 bias-pull-up;
614 };
615
616 i2c_1_default: i2c-1-default-state {
617 pins = "gpio2", "gpio3";
618 function = "blsp_i2c1";
619 drive-strength = <2>;
620 bias-disable;
621 };
622
623 i2c_1_sleep: i2c-1-sleep-state {
624 pins = "gpio2", "gpio3";
625 function = "gpio";
626 drive-strength = <2>;
627 bias-disable;
628 };
629
630 i2c_2_default: i2c-2-default-state {
631 pins = "gpio6", "gpio7";
632 function = "blsp_i2c2";
633 drive-strength = <2>;
634 bias-disable;
635 };
636
637 i2c_2_sleep: i2c-2-sleep-state {
638 pins = "gpio6", "gpio7";
639 function = "gpio";
640 drive-strength = <2>;
641 bias-disable;
642 };
643
644 i2c_3_default: i2c-3-default-state {
645 pins = "gpio10", "gpio11";
646 function = "blsp_i2c3";
647 drive-strength = <2>;
648 bias-disable;
649 };
650
651 i2c_3_sleep: i2c-3-sleep-state {
652 pins = "gpio10", "gpio11";
653 function = "gpio";
654 drive-strength = <2>;
655 bias-disable;
656 };
657
658 i2c_4_default: i2c-4-default-state {
659 pins = "gpio14", "gpio15";
660 function = "blsp_i2c4";
661 drive-strength = <2>;
662 bias-disable;
663 };
664
665 i2c_4_sleep: i2c-4-sleep-state {
666 pins = "gpio14", "gpio15";
667 function = "gpio";
668 drive-strength = <2>;
669 bias-disable;
670 };
671
672 i2c_5_default: i2c-5-default-state {
673 pins = "gpio18", "gpio19";
674 function = "blsp_i2c5";
675 drive-strength = <2>;
676 bias-disable;
677 };
678
679 i2c_5_sleep: i2c-5-sleep-state {
680 pins = "gpio18", "gpio19";
681 function = "gpio";
682 drive-strength = <2>;
683 bias-disable;
684 };
685
686 i2c_6_default: i2c-6-default-state {
687 pins = "gpio22", "gpio23";
688 function = "blsp_i2c6";
689 drive-strength = <2>;
690 bias-disable;
691 };
692
693 i2c_6_sleep: i2c-6-sleep-state {
694 pins = "gpio22", "gpio23";
695 function = "gpio";
696 drive-strength = <2>;
697 bias-disable;
698 };
699
700 i2c_7_default: i2c-7-default-state {
701 pins = "gpio135", "gpio136";
702 function = "blsp_i2c7";
703 drive-strength = <2>;
704 bias-disable;
705 };
706
707 i2c_7_sleep: i2c-7-sleep-state {
708 pins = "gpio135", "gpio136";
709 function = "gpio";
710 drive-strength = <2>;
711 bias-disable;
712 };
713
714 i2c_8_default: i2c-8-default-state {
715 pins = "gpio98", "gpio99";
716 function = "blsp_i2c8";
717 drive-strength = <2>;
718 bias-disable;
719 };
720
721 i2c_8_sleep: i2c-8-sleep-state {
722 pins = "gpio98", "gpio99";
723 function = "gpio";
724 drive-strength = <2>;
725 bias-disable;
726 };
727
728 spi_3_default: spi-3-default-state {
729 pins = "gpio10", "gpio11";
730 function = "blsp_spi3";
731 drive-strength = <2>;
732 bias-disable;
733 };
734
735 spi_3_sleep: spi-3-sleep-state {
736 pins = "gpio10", "gpio11";
737 function = "gpio";
738 drive-strength = <2>;
739 bias-disable;
740 };
741
742 spi_5_default: spi-5-default-state {
743 pins = "gpio18", "gpio19";
744 function = "blsp_spi5";
745 drive-strength = <2>;
746 bias-disable;
747 };
748
749 spi_5_sleep: spi-5-sleep-state {
750 pins = "gpio18", "gpio19";
751 function = "gpio";
752 drive-strength = <2>;
753 bias-disable;
754 };
755
756 spi_6_default: spi-6-default-state {
757 pins = "gpio22", "gpio23";
758 function = "blsp_spi6";
759 drive-strength = <2>;
760 bias-disable;
761 };
762
763 spi_6_sleep: spi-6-sleep-state {
764 pins = "gpio22", "gpio23";
765 function = "gpio";
766 drive-strength = <2>;
767 bias-disable;
768 };
769
770 wcnss_pin_a: wcnss-active-state {
771
772 wcss-wlan2-pins {
773 pins = "gpio76";
774 function = "wcss_wlan2";
775 drive-strength = <6>;
776 bias-pull-up;
777 };
778
779 wcss-wlan1-pins {
780 pins = "gpio77";
781 function = "wcss_wlan1";
782 drive-strength = <6>;
783 bias-pull-up;
784 };
785
786 wcss-wlan0-pins {
787 pins = "gpio78";
788 function = "wcss_wlan0";
789 drive-strength = <6>;
790 bias-pull-up;
791 };
792
793 wcss-wlan-pins {
794 pins = "gpio79", "gpio80";
795 function = "wcss_wlan";
796 drive-strength = <6>;
797 bias-pull-up;
798 };
799 };
800 };
801
802 gcc: clock-controller@1800000 {
803 compatible = "qcom,gcc-msm8953";
804 reg = <0x01800000 0x80000>;
805 #clock-cells = <1>;
806 #reset-cells = <1>;
807 #power-domain-cells = <1>;
808 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
809 <&sleep_clk>,
810 <&mdss_dsi0_phy 1>,
811 <&mdss_dsi0_phy 0>,
812 <&mdss_dsi1_phy 1>,
813 <&mdss_dsi1_phy 0>;
814 clock-names = "xo",
815 "sleep",
816 "dsi0pll",
817 "dsi0pllbyte",
818 "dsi1pll",
819 "dsi1pllbyte";
820 };
821
822 tcsr_mutex: hwlock@1905000 {
823 compatible = "qcom,tcsr-mutex";
824 reg = <0x01905000 0x20000>;
825 #hwlock-cells = <1>;
826 };
827
828 tcsr: syscon@1937000 {
829 compatible = "qcom,tcsr-msm8953", "syscon";
830 reg = <0x01937000 0x30000>;
831 };
832
833 tcsr_phy_clk_scheme_sel: syscon@193f044 {
834 compatible = "qcom,tcsr-msm8953", "syscon";
835 reg = <0x0193f044 0x4>;
836 };
837
838 mdss: display-subsystem@1a00000 {
839 compatible = "qcom,mdss";
840
841 reg = <0x01a00000 0x1000>,
842 <0x01ab0000 0x1040>;
843 reg-names = "mdss_phys",
844 "vbif_phys";
845
846 power-domains = <&gcc MDSS_GDSC>;
847 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
848
849 interrupt-controller;
850 #interrupt-cells = <1>;
851
852 clocks = <&gcc GCC_MDSS_AHB_CLK>,
853 <&gcc GCC_MDSS_AXI_CLK>,
854 <&gcc GCC_MDSS_VSYNC_CLK>,
855 <&gcc GCC_MDSS_MDP_CLK>;
856 clock-names = "iface",
857 "bus",
858 "vsync",
859 "core";
860
861 resets = <&gcc GCC_MDSS_BCR>;
862
863 #address-cells = <1>;
864 #size-cells = <1>;
865 ranges;
866
867 status = "disabled";
868
869 mdp: display-controller@1a01000 {
870 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
871 reg = <0x01a01000 0x89000>;
872 reg-names = "mdp_phys";
873
874 interrupt-parent = <&mdss>;
875 interrupts = <0>;
876
877 power-domains = <&gcc MDSS_GDSC>;
878
879 clocks = <&gcc GCC_MDSS_AHB_CLK>,
880 <&gcc GCC_MDSS_AXI_CLK>,
881 <&gcc GCC_MDSS_MDP_CLK>,
882 <&gcc GCC_MDSS_VSYNC_CLK>;
883 clock-names = "iface",
884 "bus",
885 "core",
886 "vsync";
887
888 iommus = <&apps_iommu 0x15>;
889
890 ports {
891 #address-cells = <1>;
892 #size-cells = <0>;
893
894 port@0 {
895 reg = <0>;
896 mdp5_intf1_out: endpoint {
897 remote-endpoint = <&mdss_dsi0_in>;
898 };
899 };
900
901 port@1 {
902 reg = <1>;
903 mdp5_intf2_out: endpoint {
904 remote-endpoint = <&mdss_dsi1_in>;
905 };
906 };
907 };
908 };
909
910 mdss_dsi0: dsi@1a94000 {
911 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
912 reg = <0x01a94000 0x400>;
913 reg-names = "dsi_ctrl";
914
915 interrupt-parent = <&mdss>;
916 interrupts = <4>;
917
918 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
919 <&gcc PCLK0_CLK_SRC>;
920 assigned-clock-parents = <&mdss_dsi0_phy 0>,
921 <&mdss_dsi0_phy 1>;
922
923 clocks = <&gcc GCC_MDSS_MDP_CLK>,
924 <&gcc GCC_MDSS_AHB_CLK>,
925 <&gcc GCC_MDSS_AXI_CLK>,
926 <&gcc GCC_MDSS_BYTE0_CLK>,
927 <&gcc GCC_MDSS_PCLK0_CLK>,
928 <&gcc GCC_MDSS_ESC0_CLK>;
929 clock-names = "mdp_core",
930 "iface",
931 "bus",
932 "byte",
933 "pixel",
934 "core";
935
936 phys = <&mdss_dsi0_phy>;
937
938 #address-cells = <1>;
939 #size-cells = <0>;
940
941 status = "disabled";
942
943 ports {
944 #address-cells = <1>;
945 #size-cells = <0>;
946
947 port@0 {
948 reg = <0>;
949 mdss_dsi0_in: endpoint {
950 remote-endpoint = <&mdp5_intf1_out>;
951 };
952 };
953
954 port@1 {
955 reg = <1>;
956 mdss_dsi0_out: endpoint {
957 };
958 };
959 };
960 };
961
962 mdss_dsi0_phy: phy@1a94400 {
963 compatible = "qcom,dsi-phy-14nm-8953";
964 reg = <0x01a94400 0x100>,
965 <0x01a94500 0x300>,
966 <0x01a94800 0x188>;
967 reg-names = "dsi_phy",
968 "dsi_phy_lane",
969 "dsi_pll";
970
971 #clock-cells = <1>;
972 #phy-cells = <0>;
973
974 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
975 clock-names = "iface", "ref";
976
977 status = "disabled";
978 };
979
980 mdss_dsi1: dsi@1a96000 {
981 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
982 reg = <0x01a96000 0x400>;
983 reg-names = "dsi_ctrl";
984
985 interrupt-parent = <&mdss>;
986 interrupts = <5>;
987
988 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
989 <&gcc PCLK1_CLK_SRC>;
990 assigned-clock-parents = <&mdss_dsi1_phy 0>,
991 <&mdss_dsi1_phy 1>;
992
993 clocks = <&gcc GCC_MDSS_MDP_CLK>,
994 <&gcc GCC_MDSS_AHB_CLK>,
995 <&gcc GCC_MDSS_AXI_CLK>,
996 <&gcc GCC_MDSS_BYTE1_CLK>,
997 <&gcc GCC_MDSS_PCLK1_CLK>,
998 <&gcc GCC_MDSS_ESC1_CLK>;
999 clock-names = "mdp_core",
1000 "iface",
1001 "bus",
1002 "byte",
1003 "pixel",
1004 "core";
1005
1006 phys = <&mdss_dsi1_phy>;
1007
1008 status = "disabled";
1009
1010 ports {
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013
1014 port@0 {
1015 reg = <0>;
1016 mdss_dsi1_in: endpoint {
1017 remote-endpoint = <&mdp5_intf2_out>;
1018 };
1019 };
1020
1021 port@1 {
1022 reg = <1>;
1023 mdss_dsi1_out: endpoint {
1024 };
1025 };
1026 };
1027 };
1028
1029 mdss_dsi1_phy: phy@1a96400 {
1030 compatible = "qcom,dsi-phy-14nm-8953";
1031 reg = <0x01a96400 0x100>,
1032 <0x01a96500 0x300>,
1033 <0x01a96800 0x188>;
1034 reg-names = "dsi_phy",
1035 "dsi_phy_lane",
1036 "dsi_pll";
1037
1038 #clock-cells = <1>;
1039 #phy-cells = <0>;
1040
1041 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1042 clock-names = "iface", "ref";
1043
1044 status = "disabled";
1045 };
1046 };
1047
1048 gpu: gpu@1c00000 {
1049 compatible = "qcom,adreno-506.0", "qcom,adreno";
1050 reg = <0x01c00000 0x40000>;
1051 reg-names = "kgsl_3d0_reg_memory";
1052 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1053
1054 clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1055 <&gcc GCC_OXILI_AHB_CLK>,
1056 <&gcc GCC_BIMC_GFX_CLK>,
1057 <&gcc GCC_BIMC_GPU_CLK>,
1058 <&gcc GCC_OXILI_TIMER_CLK>,
1059 <&gcc GCC_OXILI_AON_CLK>;
1060 clock-names = "core",
1061 "iface",
1062 "mem_iface",
1063 "alt_mem_iface",
1064 "rbbmtimer",
1065 "alwayson";
1066 power-domains = <&gcc OXILI_GX_GDSC>;
1067
1068 iommus = <&gpu_iommu 0>;
1069 operating-points-v2 = <&gpu_opp_table>;
1070
1071 #cooling-cells = <2>;
1072
1073 status = "disabled";
1074
1075 zap-shader {
1076 memory-region = <&zap_shader_region>;
1077 };
1078
1079 gpu_opp_table: opp-table {
1080 compatible = "operating-points-v2";
1081
1082 opp-19200000 {
1083 opp-hz = /bits/ 64 <19200000>;
1084 opp-supported-hw = <0xff>;
1085 required-opps = <&rpmpd_opp_min_svs>;
1086 };
1087
1088 opp-133300000 {
1089 opp-hz = /bits/ 64 <133300000>;
1090 opp-supported-hw = <0xff>;
1091 required-opps = <&rpmpd_opp_min_svs>;
1092 };
1093
1094 opp-216000000 {
1095 opp-hz = /bits/ 64 <216000000>;
1096 opp-supported-hw = <0xff>;
1097 required-opps = <&rpmpd_opp_low_svs>;
1098 };
1099
1100 opp-320000000 {
1101 opp-hz = /bits/ 64 <320000000>;
1102 opp-supported-hw = <0xff>;
1103 required-opps = <&rpmpd_opp_svs>;
1104 };
1105
1106 opp-400000000 {
1107 opp-hz = /bits/ 64 <400000000>;
1108 opp-supported-hw = <0xff>;
1109 required-opps = <&rpmpd_opp_svs_plus>;
1110 };
1111
1112 opp-510000000 {
1113 opp-hz = /bits/ 64 <510000000>;
1114 opp-supported-hw = <0xff>;
1115 required-opps = <&rpmpd_opp_nom>;
1116 };
1117
1118 opp-560000000 {
1119 opp-hz = /bits/ 64 <560000000>;
1120 opp-supported-hw = <0xff>;
1121 required-opps = <&rpmpd_opp_nom_plus>;
1122 };
1123
1124 /*
1125 * This opp is only available on msm8953 and
1126 * sdm632, the max for sdm450 is 600MHz.
1127 */
1128 opp-650000000 {
1129 opp-hz = /bits/ 64 <650000000>;
1130 opp-supported-hw = <0xff>;
1131 required-opps = <&rpmpd_opp_turbo>;
1132 };
1133 };
1134 };
1135
1136 gpu_iommu: iommu@1c48000 {
1137 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
1138 ranges = <0 0x01c48000 0x8000>;
1139
1140 clocks = <&gcc GCC_OXILI_AHB_CLK>,
1141 <&gcc GCC_BIMC_GFX_CLK>;
1142 clock-names = "iface", "bus";
1143
1144 power-domains = <&gcc OXILI_CX_GDSC>;
1145
1146 qcom,iommu-secure-id = <18>;
1147
1148 #address-cells = <1>;
1149 #iommu-cells = <1>;
1150 #size-cells = <1>;
1151
1152 /* gfx3d_user */
1153 iommu-ctx@0 {
1154 compatible = "qcom,msm-iommu-v2-ns";
1155 reg = <0x0000 0x1000>;
1156 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1157 };
1158
1159 /* gfx3d_secure */
1160 iommu-ctx@2000 {
1161 compatible = "qcom,msm-iommu-v2-sec";
1162 reg = <0x2000 0x1000>;
1163 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1164 };
1165 };
1166
1167 apps_iommu: iommu@1e20000 {
1168 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1169 ranges = <0 0x01e20000 0x20000>;
1170
1171 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1172 <&gcc GCC_APSS_TCU_ASYNC_CLK>;
1173 clock-names = "iface", "bus";
1174
1175 qcom,iommu-secure-id = <17>;
1176
1177 #address-cells = <1>;
1178 #iommu-cells = <1>;
1179 #size-cells = <1>;
1180
1181 /* VFE */
1182 iommu-ctx@14000 {
1183 compatible = "qcom,msm-iommu-v1-ns";
1184 reg = <0x14000 0x1000>;
1185 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1186 };
1187
1188 /* MDP_0 */
1189 iommu-ctx@15000 {
1190 compatible = "qcom,msm-iommu-v1-ns";
1191 reg = <0x15000 0x1000>;
1192 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1193 };
1194
1195 /* VENUS_NS */
1196 iommu-ctx@16000 {
1197 compatible = "qcom,msm-iommu-v1-ns";
1198 reg = <0x16000 0x1000>;
1199 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1200 };
1201 };
1202
1203 spmi_bus: spmi@200f000 {
1204 compatible = "qcom,spmi-pmic-arb";
1205 reg = <0x0200f000 0x1000>,
1206 <0x02400000 0x800000>,
1207 <0x02c00000 0x800000>,
1208 <0x03800000 0x200000>,
1209 <0x0200a000 0x2100>;
1210 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1211 interrupt-names = "periph_irq";
1212 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1213 qcom,ee = <0>;
1214 qcom,channel = <0>;
1215 interrupt-controller;
1216
1217 #interrupt-cells = <4>;
1218 #address-cells = <2>;
1219 #size-cells = <0>;
1220 };
1221
1222 mpss: remoteproc@4080000 {
1223 compatible = "qcom,msm8953-mss-pil";
1224 reg = <0x04080000 0x100>,
1225 <0x04020000 0x040>;
1226 reg-names = "qdsp6", "rmb";
1227
1228 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1229 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1230 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1231 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1232 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>;
1233 interrupt-names = "wdog", "fatal", "ready",
1234 "handover", "stop-ack";
1235
1236 power-domains = <&rpmpd MSM8953_VDDCX>,
1237 <&rpmpd MSM8953_VDDMX>,
1238 <&rpmpd MSM8953_VDDMD>;
1239 power-domain-names = "cx", "mx","mss";
1240
1241 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1242 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1243 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1244 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1245 clock-names = "iface", "bus", "mem", "xo";
1246
1247 qcom,smem-states = <&smp2p_modem_out 0>;
1248 qcom,smem-state-names = "stop";
1249
1250 resets = <&gcc GCC_MSS_BCR>;
1251 reset-names = "mss_restart";
1252
1253 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1254
1255 status = "disabled";
1256
1257 mba {
1258 memory-region = <&mba_mem>;
1259 };
1260
1261 mpss {
1262 memory-region = <&mpss_mem>;
1263 };
1264
1265 smd-edge {
1266 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1267
1268 qcom,smd-edge = <0>;
1269 mboxes = <&apcs 12>;
1270 qcom,remote-pid = <1>;
1271
1272 label = "modem";
1273 };
1274 };
1275
1276 usb3: usb@70f8800 {
1277 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1278 reg = <0x070f8800 0x400>;
1279 #address-cells = <1>;
1280 #size-cells = <1>;
1281 ranges;
1282
1283 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1286 interrupt-names = "pwr_event",
1287 "qusb2_phy",
1288 "ss_phy_irq";
1289
1290 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
1291 <&gcc GCC_USB30_MASTER_CLK>,
1292 <&gcc GCC_PCNOC_USB3_AXI_CLK>,
1293 <&gcc GCC_USB30_SLEEP_CLK>,
1294 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1295 clock-names = "cfg_noc",
1296 "core",
1297 "iface",
1298 "sleep",
1299 "mock_utmi";
1300
1301 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1302 <&gcc GCC_USB30_MASTER_CLK>;
1303 assigned-clock-rates = <19200000>, <133330000>;
1304
1305 power-domains = <&gcc USB30_GDSC>;
1306
1307 qcom,select-utmi-as-pipe-clk;
1308
1309 status = "disabled";
1310
1311 usb3_dwc3: usb@7000000 {
1312 compatible = "snps,dwc3";
1313 reg = <0x07000000 0xcc00>;
1314 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1315 phys = <&hsusb_phy>;
1316 phy-names = "usb2-phy";
1317
1318 snps,usb2-gadget-lpm-disable;
1319 snps,dis-u1-entry-quirk;
1320 snps,dis-u2-entry-quirk;
1321 snps,is-utmi-l1-suspend;
1322 snps,hird-threshold = /bits/ 8 <0x00>;
1323
1324 maximum-speed = "high-speed";
1325
1326 usb-role-switch;
1327
1328 ports {
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331
1332 port@0 {
1333 reg = <0>;
1334
1335 usb_dwc3_hs: endpoint {
1336 };
1337 };
1338 };
1339 };
1340 };
1341
1342 sdhc_1: mmc@7824900 {
1343 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1344
1345 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1346 reg-names = "hc", "core";
1347
1348 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "hc_irq", "pwr_irq";
1351
1352 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1353 <&gcc GCC_SDCC1_APPS_CLK>,
1354 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1355 clock-names = "iface", "core", "xo";
1356
1357 power-domains = <&rpmpd MSM8953_VDDCX>;
1358 operating-points-v2 = <&sdhc1_opp_table>;
1359
1360 pinctrl-names = "default", "sleep";
1361 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1362 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1363
1364 mmc-hs400-1_8v;
1365 mmc-hs200-1_8v;
1366 mmc-ddr-1_8v;
1367 bus-width = <8>;
1368 non-removable;
1369
1370 status = "disabled";
1371
1372 sdhc1_opp_table: opp-table-sdhc1 {
1373 compatible = "operating-points-v2";
1374
1375 opp-25000000 {
1376 opp-hz = /bits/ 64 <25000000>;
1377 required-opps = <&rpmpd_opp_low_svs>;
1378 };
1379
1380 opp-50000000 {
1381 opp-hz = /bits/ 64 <50000000>;
1382 required-opps = <&rpmpd_opp_svs>;
1383 };
1384
1385 opp-100000000 {
1386 opp-hz = /bits/ 64 <100000000>;
1387 required-opps = <&rpmpd_opp_svs>;
1388 };
1389
1390 opp-192000000 {
1391 opp-hz = /bits/ 64 <192000000>;
1392 required-opps = <&rpmpd_opp_nom>;
1393 };
1394
1395 opp-384000000 {
1396 opp-hz = /bits/ 64 <384000000>;
1397 required-opps = <&rpmpd_opp_nom>;
1398 };
1399 };
1400 };
1401
1402 sdhc_2: mmc@7864900 {
1403 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1404
1405 reg = <0x07864900 0x500>, <0x07864000 0x800>;
1406 reg-names = "hc", "core";
1407
1408 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1410 interrupt-names = "hc_irq", "pwr_irq";
1411
1412 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1413 <&gcc GCC_SDCC2_APPS_CLK>,
1414 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1415 clock-names = "iface", "core", "xo";
1416
1417 power-domains = <&rpmpd MSM8953_VDDCX>;
1418 operating-points-v2 = <&sdhc2_opp_table>;
1419
1420 pinctrl-names = "default", "sleep";
1421 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1422 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1423
1424 bus-width = <4>;
1425
1426 status = "disabled";
1427
1428 sdhc2_opp_table: opp-table-sdhc2 {
1429 compatible = "operating-points-v2";
1430
1431 opp-25000000 {
1432 opp-hz = /bits/ 64 <25000000>;
1433 required-opps = <&rpmpd_opp_low_svs>;
1434 };
1435
1436 opp-50000000 {
1437 opp-hz = /bits/ 64 <50000000>;
1438 required-opps = <&rpmpd_opp_svs>;
1439 };
1440
1441 opp-100000000 {
1442 opp-hz = /bits/ 64 <100000000>;
1443 required-opps = <&rpmpd_opp_svs>;
1444 };
1445
1446 opp-177770000 {
1447 opp-hz = /bits/ 64 <177770000>;
1448 required-opps = <&rpmpd_opp_nom>;
1449 };
1450
1451 opp-200000000 {
1452 opp-hz = /bits/ 64 <200000000>;
1453 required-opps = <&rpmpd_opp_nom>;
1454 };
1455 };
1456 };
1457
1458 blsp1_dma: dma-controller@7884000 {
1459 compatible = "qcom,bam-v1.7.0";
1460 reg = <0x07884000 0x1f000>;
1461 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1462 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1463 clock-names = "bam_clk";
1464 num-channels = <12>;
1465 #dma-cells = <1>;
1466 qcom,ee = <0>;
1467 qcom,num-ees = <4>;
1468 qcom,controlled-remotely;
1469 };
1470
1471 uart_0: serial@78af000 {
1472 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1473 reg = <0x078af000 0x200>;
1474 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1475 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1476 <&gcc GCC_BLSP1_AHB_CLK>;
1477 clock-names = "core", "iface";
1478
1479 status = "disabled";
1480 };
1481
1482 i2c_1: i2c@78b5000 {
1483 compatible = "qcom,i2c-qup-v2.2.1";
1484 reg = <0x078b5000 0x600>;
1485 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1486 clock-names = "core", "iface";
1487 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1488 <&gcc GCC_BLSP1_AHB_CLK>;
1489 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1490 dma-names = "tx", "rx";
1491
1492 pinctrl-names = "default", "sleep";
1493 pinctrl-0 = <&i2c_1_default>;
1494 pinctrl-1 = <&i2c_1_sleep>;
1495
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498
1499 status = "disabled";
1500 };
1501
1502 i2c_2: i2c@78b6000 {
1503 compatible = "qcom,i2c-qup-v2.2.1";
1504 reg = <0x078b6000 0x600>;
1505 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1506 clock-names = "core", "iface";
1507 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1508 <&gcc GCC_BLSP1_AHB_CLK>;
1509 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1510 dma-names = "tx", "rx";
1511
1512 pinctrl-names = "default", "sleep";
1513 pinctrl-0 = <&i2c_2_default>;
1514 pinctrl-1 = <&i2c_2_sleep>;
1515
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1518
1519 status = "disabled";
1520 };
1521
1522 i2c_3: i2c@78b7000 {
1523 compatible = "qcom,i2c-qup-v2.2.1";
1524 reg = <0x078b7000 0x600>;
1525 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1526 clock-names = "core", "iface";
1527 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1528 <&gcc GCC_BLSP1_AHB_CLK>;
1529 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1530 dma-names = "tx", "rx";
1531
1532 pinctrl-names = "default", "sleep";
1533 pinctrl-0 = <&i2c_3_default>;
1534 pinctrl-1 = <&i2c_3_sleep>;
1535
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1538
1539 status = "disabled";
1540 };
1541
1542 spi_3: spi@78b7000 {
1543 compatible = "qcom,spi-qup-v2.2.1";
1544 reg = <0x078b7000 0x600>;
1545 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1546 clock-names = "core", "iface";
1547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1548 <&gcc GCC_BLSP1_AHB_CLK>;
1549 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1550 dma-names = "tx", "rx";
1551
1552 pinctrl-names = "default", "sleep";
1553 pinctrl-0 = <&spi_3_default>;
1554 pinctrl-1 = <&spi_3_sleep>;
1555
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558
1559 status = "disabled";
1560 };
1561
1562 i2c_4: i2c@78b8000 {
1563 compatible = "qcom,i2c-qup-v2.2.1";
1564 reg = <0x078b8000 0x600>;
1565 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1566 clock-names = "core", "iface";
1567 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1568 <&gcc GCC_BLSP1_AHB_CLK>;
1569 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1570 dma-names = "tx", "rx";
1571
1572 pinctrl-names = "default", "sleep";
1573 pinctrl-0 = <&i2c_4_default>;
1574 pinctrl-1 = <&i2c_4_sleep>;
1575
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1578
1579 status = "disabled";
1580 };
1581
1582 blsp2_dma: dma-controller@7ac4000 {
1583 compatible = "qcom,bam-v1.7.0";
1584 reg = <0x07ac4000 0x1f000>;
1585 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1587 clock-names = "bam_clk";
1588 num-channels = <12>;
1589 #dma-cells = <1>;
1590 qcom,ee = <0>;
1591 qcom,num-ees = <4>;
1592 qcom,controlled-remotely;
1593 };
1594
1595 i2c_5: i2c@7af5000 {
1596 compatible = "qcom,i2c-qup-v2.2.1";
1597 reg = <0x07af5000 0x600>;
1598 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1599 clock-names = "core", "iface";
1600 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1601 <&gcc GCC_BLSP2_AHB_CLK>;
1602 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1603 dma-names = "tx", "rx";
1604
1605 pinctrl-names = "default", "sleep";
1606 pinctrl-0 = <&i2c_5_default>;
1607 pinctrl-1 = <&i2c_5_sleep>;
1608
1609 #address-cells = <1>;
1610 #size-cells = <0>;
1611
1612 status = "disabled";
1613 };
1614
1615 spi_5: spi@7af5000 {
1616 compatible = "qcom,spi-qup-v2.2.1";
1617 reg = <0x07af5000 0x600>;
1618 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1619 clock-names = "core", "iface";
1620 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1621 <&gcc GCC_BLSP2_AHB_CLK>;
1622 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1623 dma-names = "tx", "rx";
1624
1625 pinctrl-names = "default", "sleep";
1626 pinctrl-0 = <&spi_5_default>;
1627 pinctrl-1 = <&spi_5_sleep>;
1628
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1631
1632 status = "disabled";
1633 };
1634
1635 i2c_6: i2c@7af6000 {
1636 compatible = "qcom,i2c-qup-v2.2.1";
1637 reg = <0x07af6000 0x600>;
1638 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1639 clock-names = "core", "iface";
1640 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1641 <&gcc GCC_BLSP2_AHB_CLK>;
1642 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1643 dma-names = "tx", "rx";
1644
1645 pinctrl-names = "default", "sleep";
1646 pinctrl-0 = <&i2c_6_default>;
1647 pinctrl-1 = <&i2c_6_sleep>;
1648
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1651
1652 status = "disabled";
1653 };
1654
1655 spi_6: spi@7af6000 {
1656 compatible = "qcom,spi-qup-v2.2.1";
1657 reg = <0x07af6000 0x600>;
1658 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1659 clock-names = "core", "iface";
1660 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1661 <&gcc GCC_BLSP2_AHB_CLK>;
1662 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1663 dma-names = "tx", "rx";
1664
1665 pinctrl-names = "default", "sleep";
1666 pinctrl-0 = <&spi_6_default>;
1667 pinctrl-1 = <&spi_6_sleep>;
1668
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1671
1672 status = "disabled";
1673 };
1674
1675 i2c_7: i2c@7af7000 {
1676 compatible = "qcom,i2c-qup-v2.2.1";
1677 reg = <0x07af7000 0x600>;
1678 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1679 clock-names = "core", "iface";
1680 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1681 <&gcc GCC_BLSP2_AHB_CLK>;
1682 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1683 dma-names = "tx", "rx";
1684
1685 pinctrl-names = "default", "sleep";
1686 pinctrl-0 = <&i2c_7_default>;
1687 pinctrl-1 = <&i2c_7_sleep>;
1688
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1691
1692 status = "disabled";
1693 };
1694
1695 i2c_8: i2c@7af8000 {
1696 compatible = "qcom,i2c-qup-v2.2.1";
1697 reg = <0x07af8000 0x600>;
1698 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1699 clock-names = "core", "iface";
1700 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1701 <&gcc GCC_BLSP2_AHB_CLK>;
1702 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1703 dma-names = "tx", "rx";
1704
1705 pinctrl-names = "default", "sleep";
1706 pinctrl-0 = <&i2c_8_default>;
1707 pinctrl-1 = <&i2c_8_sleep>;
1708
1709 #address-cells = <1>;
1710 #size-cells = <0>;
1711
1712 status = "disabled";
1713 };
1714
1715 wcnss: remoteproc@a204000 {
1716 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1717 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1718 reg-names = "ccu", "dxe", "pmu";
1719
1720 memory-region = <&wcnss_fw_mem>;
1721
1722 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1723 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
1724 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>,
1725 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>,
1726 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>;
1727 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1728
1729 power-domains = <&rpmpd MSM8953_VDDCX>,
1730 <&rpmpd MSM8953_VDDMX>;
1731 power-domain-names = "cx", "mx";
1732
1733 qcom,smem-states = <&smp2p_wcnss_out 0>;
1734 qcom,smem-state-names = "stop";
1735
1736 pinctrl-names = "default";
1737 pinctrl-0 = <&wcnss_pin_a>;
1738
1739 status = "disabled";
1740
1741 wcnss_iris: iris {
1742 /* Separate chip, compatible is board-specific */
1743 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1744 clock-names = "xo";
1745 };
1746
1747 smd-edge {
1748 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1749
1750 mboxes = <&apcs 17>;
1751 qcom,smd-edge = <6>;
1752 qcom,remote-pid = <4>;
1753
1754 label = "pronto";
1755
1756 wcnss_ctrl: wcnss {
1757 compatible = "qcom,wcnss";
1758 qcom,smd-channels = "WCNSS_CTRL";
1759
1760 qcom,mmio = <&wcnss>;
1761
1762 wcnss_bt: bluetooth {
1763 compatible = "qcom,wcnss-bt";
1764 };
1765
1766 wcnss_wifi: wifi {
1767 compatible = "qcom,wcnss-wlan";
1768
1769 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1771 interrupt-names = "tx", "rx";
1772
1773 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1774 qcom,smem-state-names = "tx-enable",
1775 "tx-rings-empty";
1776 };
1777 };
1778 };
1779 };
1780
1781 intc: interrupt-controller@b000000 {
1782 compatible = "qcom,msm-qgic2";
1783 interrupt-controller;
1784 #interrupt-cells = <3>;
1785 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1786 };
1787
1788 apcs: mailbox@b011000 {
1789 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1790 reg = <0x0b011000 0x1000>;
1791 #mbox-cells = <1>;
1792 };
1793
1794 timer@b120000 {
1795 compatible = "arm,armv7-timer-mem";
1796 reg = <0x0b120000 0x1000>;
1797 #address-cells = <1>;
1798 #size-cells = <1>;
1799 ranges;
1800
1801 frame@b121000 {
1802 frame-number = <0>;
1803 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1805 reg = <0x0b121000 0x1000>,
1806 <0x0b122000 0x1000>;
1807 };
1808
1809 frame@b123000 {
1810 frame-number = <1>;
1811 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1812 reg = <0x0b123000 0x1000>;
1813 status = "disabled";
1814 };
1815
1816 frame@b124000 {
1817 frame-number = <2>;
1818 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1819 reg = <0x0b124000 0x1000>;
1820 status = "disabled";
1821 };
1822
1823 frame@b125000 {
1824 frame-number = <3>;
1825 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1826 reg = <0x0b125000 0x1000>;
1827 status = "disabled";
1828 };
1829
1830 frame@b126000 {
1831 frame-number = <4>;
1832 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1833 reg = <0x0b126000 0x1000>;
1834 status = "disabled";
1835 };
1836
1837 frame@b127000 {
1838 frame-number = <5>;
1839 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1840 reg = <0x0b127000 0x1000>;
1841 status = "disabled";
1842 };
1843
1844 frame@b128000 {
1845 frame-number = <6>;
1846 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1847 reg = <0x0b128000 0x1000>;
1848 status = "disabled";
1849 };
1850 };
1851
1852 lpass: remoteproc@c200000 {
1853 compatible = "qcom,msm8953-adsp-pil";
1854 reg = <0x0c200000 0x100>;
1855
1856 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1857 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1858 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1859 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1860 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1861 interrupt-names = "wdog", "fatal", "ready",
1862 "handover", "stop-ack";
1863 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1864 clock-names = "xo";
1865
1866 power-domains = <&rpmpd MSM8953_VDDCX>;
1867 power-domain-names = "cx";
1868
1869 memory-region = <&adsp_fw_mem>;
1870
1871 qcom,smem-states = <&smp2p_adsp_out 0>;
1872 qcom,smem-state-names = "stop";
1873
1874 status = "disabled";
1875
1876 smd-edge {
1877 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1878
1879 label = "lpass";
1880 mboxes = <&apcs 8>;
1881 qcom,smd-edge = <1>;
1882 qcom,remote-pid = <2>;
1883
1884 apr {
1885 compatible = "qcom,apr-v2";
1886 qcom,smd-channels = "apr_audio_svc";
1887 qcom,domain = <APR_DOMAIN_ADSP>;
1888 #address-cells = <1>;
1889 #size-cells = <0>;
1890
1891 q6core: service@3 {
1892 reg = <APR_SVC_ADSP_CORE>;
1893 compatible = "qcom,q6core";
1894 };
1895
1896 q6afe: service@4 {
1897 compatible = "qcom,q6afe";
1898 reg = <APR_SVC_AFE>;
1899 q6afedai: dais {
1900 compatible = "qcom,q6afe-dais";
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1903 #sound-dai-cells = <1>;
1904
1905 dai@16 {
1906 reg = <PRIMARY_MI2S_RX>;
1907 qcom,sd-lines = <0 1>;
1908 };
1909 dai@20 {
1910 reg = <TERTIARY_MI2S_TX>;
1911 qcom,sd-lines = <0 1>;
1912 };
1913 dai@127 {
1914 reg = <QUINARY_MI2S_RX>;
1915 qcom,sd-lines = <0>;
1916 };
1917 };
1918
1919 q6afecc: clock-controller {
1920 compatible = "qcom,q6afe-clocks";
1921 #clock-cells = <2>;
1922 };
1923 };
1924
1925 q6asm: service@7 {
1926 compatible = "qcom,q6asm";
1927 reg = <APR_SVC_ASM>;
1928 q6asmdai: dais {
1929 compatible = "qcom,q6asm-dais";
1930 #address-cells = <1>;
1931 #size-cells = <0>;
1932 #sound-dai-cells = <1>;
1933
1934 dai@0 {
1935 reg = <0>;
1936 direction = <Q6ASM_DAI_RX>;
1937 };
1938 dai@1 {
1939 reg = <1>;
1940 direction = <Q6ASM_DAI_TX>;
1941 };
1942 dai@2 {
1943 reg = <2>;
1944 direction = <Q6ASM_DAI_RX>;
1945 };
1946 dai@3 {
1947 reg = <3>;
1948 direction = <Q6ASM_DAI_RX>;
1949 is-compress-dai;
1950 };
1951 };
1952 };
1953
1954 q6adm: service@8 {
1955 compatible = "qcom,q6adm";
1956 reg = <APR_SVC_ADM>;
1957 q6routing: routing {
1958 compatible = "qcom,q6adm-routing";
1959 #sound-dai-cells = <0>;
1960 };
1961 };
1962 };
1963 };
1964 };
1965 };
1966
1967 thermal-zones {
1968 cpu0-thermal {
1969 polling-delay-passive = <250>;
1970
1971 thermal-sensors = <&tsens0 9>;
1972
1973 trips {
1974 cpu0_alert: trip-point0 {
1975 temperature = <80000>;
1976 hysteresis = <2000>;
1977 type = "passive";
1978 };
1979 cpu0_crit: crit {
1980 temperature = <100000>;
1981 hysteresis = <2000>;
1982 type = "critical";
1983 };
1984 };
1985 cooling-maps {
1986 map0 {
1987 trip = <&cpu0_alert>;
1988 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1989 };
1990 };
1991 };
1992 cpu1-thermal {
1993 polling-delay-passive = <250>;
1994
1995 thermal-sensors = <&tsens0 10>;
1996
1997 trips {
1998 cpu1_alert: trip-point0 {
1999 temperature = <80000>;
2000 hysteresis = <2000>;
2001 type = "passive";
2002 };
2003 cpu1_crit: crit {
2004 temperature = <100000>;
2005 hysteresis = <2000>;
2006 type = "critical";
2007 };
2008 };
2009 cooling-maps {
2010 map0 {
2011 trip = <&cpu1_alert>;
2012 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2013 };
2014 };
2015 };
2016 cpu2-thermal {
2017 polling-delay-passive = <250>;
2018
2019 thermal-sensors = <&tsens0 11>;
2020
2021 trips {
2022 cpu2_alert: trip-point0 {
2023 temperature = <80000>;
2024 hysteresis = <2000>;
2025 type = "passive";
2026 };
2027 cpu2_crit: crit {
2028 temperature = <100000>;
2029 hysteresis = <2000>;
2030 type = "critical";
2031 };
2032 };
2033 cooling-maps {
2034 map0 {
2035 trip = <&cpu2_alert>;
2036 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2037 };
2038 };
2039 };
2040 cpu3-thermal {
2041 polling-delay-passive = <250>;
2042
2043 thermal-sensors = <&tsens0 12>;
2044
2045 trips {
2046 cpu3_alert: trip-point0 {
2047 temperature = <80000>;
2048 hysteresis = <2000>;
2049 type = "passive";
2050 };
2051 cpu3_crit: crit {
2052 temperature = <100000>;
2053 hysteresis = <2000>;
2054 type = "critical";
2055 };
2056 };
2057 cooling-maps {
2058 map0 {
2059 trip = <&cpu3_alert>;
2060 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2061 };
2062 };
2063 };
2064 cpu4-thermal {
2065 polling-delay-passive = <250>;
2066 thermal-sensors = <&tsens0 4>;
2067 trips {
2068 cpu4_alert: trip-point0 {
2069 temperature = <80000>;
2070 hysteresis = <2000>;
2071 type = "passive";
2072 };
2073 cpu4_crit: crit {
2074 temperature = <100000>;
2075 hysteresis = <2000>;
2076 type = "critical";
2077 };
2078 };
2079 cooling-maps {
2080 map0 {
2081 trip = <&cpu4_alert>;
2082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2083 };
2084 };
2085 };
2086 cpu5-thermal {
2087 polling-delay-passive = <250>;
2088 thermal-sensors = <&tsens0 5>;
2089 trips {
2090 cpu5_alert: trip-point0 {
2091 temperature = <80000>;
2092 hysteresis = <2000>;
2093 type = "passive";
2094 };
2095 cpu5_crit: crit {
2096 temperature = <100000>;
2097 hysteresis = <2000>;
2098 type = "critical";
2099 };
2100 };
2101 cooling-maps {
2102 map0 {
2103 trip = <&cpu5_alert>;
2104 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2105 };
2106 };
2107 };
2108 cpu6-thermal {
2109 polling-delay-passive = <250>;
2110 thermal-sensors = <&tsens0 6>;
2111 trips {
2112 cpu6_alert: trip-point0 {
2113 temperature = <80000>;
2114 hysteresis = <2000>;
2115 type = "passive";
2116 };
2117 cpu6_crit: crit {
2118 temperature = <100000>;
2119 hysteresis = <2000>;
2120 type = "critical";
2121 };
2122 };
2123 cooling-maps {
2124 map0 {
2125 trip = <&cpu6_alert>;
2126 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2127 };
2128 };
2129 };
2130 cpu7-thermal {
2131 polling-delay-passive = <250>;
2132 thermal-sensors = <&tsens0 7>;
2133 trips {
2134 cpu7_alert: trip-point0 {
2135 temperature = <80000>;
2136 hysteresis = <2000>;
2137 type = "passive";
2138 };
2139 cpu7_crit: crit {
2140 temperature = <100000>;
2141 hysteresis = <2000>;
2142 type = "critical";
2143 };
2144 };
2145 cooling-maps {
2146 map0 {
2147 trip = <&cpu7_alert>;
2148 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2149 };
2150 };
2151 };
2152
2153 gpu-thermal {
2154 polling-delay-passive = <250>;
2155 thermal-sensors = <&tsens0 15>;
2156
2157 trips {
2158 gpu_alert: trip-point0 {
2159 temperature = <70000>;
2160 hysteresis = <2000>;
2161 type = "passive";
2162 };
2163
2164 gpu_crit: crit {
2165 temperature = <90000>;
2166 hysteresis = <2000>;
2167 type = "critical";
2168 };
2169 };
2170
2171 cooling-maps {
2172 map0 {
2173 trip = <&gpu_alert>;
2174 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2175 };
2176 };
2177 };
2178 };
2179
2180 timer {
2181 compatible = "arm,armv8-timer";
2182 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2183 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2184 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2185 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2186 };
2187 };
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