1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
4 * <angelogioacchino.delregno@collabora.com>
5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
7 */
8
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15
16 / {
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 clocks {
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 };
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 CPU0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53";
37 reg = <0x0>;
38 enable-method = "psci";
39 cpu-idle-states = <&little_cpu_sleep_0>;
40 capacity-dmips-mhz = <573>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
43 };
44
45 CPU1: cpu@1 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 reg = <0x1>;
49 enable-method = "psci";
50 cpu-idle-states = <&little_cpu_sleep_0>;
51 capacity-dmips-mhz = <573>;
52 next-level-cache = <&l2_0>;
53 #cooling-cells = <2>;
54 };
55
56 CPU2: cpu@2 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53";
59 reg = <0x2>;
60 enable-method = "psci";
61 cpu-idle-states = <&little_cpu_sleep_0>;
62 capacity-dmips-mhz = <573>;
63 next-level-cache = <&l2_0>;
64 #cooling-cells = <2>;
65 };
66
67 CPU3: cpu@3 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 reg = <0x3>;
71 enable-method = "psci";
72 cpu-idle-states = <&little_cpu_sleep_0>;
73 capacity-dmips-mhz = <573>;
74 next-level-cache = <&l2_0>;
75 #cooling-cells = <2>;
76 };
77
78 CPU4: cpu@100 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a72";
81 reg = <0x100>;
82 enable-method = "psci";
83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
84 capacity-dmips-mhz = <1024>;
85 next-level-cache = <&l2_1>;
86 #cooling-cells = <2>;
87 };
88
89 CPU5: cpu@101 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a72";
92 reg = <0x101>;
93 enable-method = "psci";
94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
95 capacity-dmips-mhz = <1024>;
96 next-level-cache = <&l2_1>;
97 #cooling-cells = <2>;
98 };
99
100 CPU6: cpu@102 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a72";
103 reg = <0x102>;
104 enable-method = "psci";
105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
109 };
110
111 CPU7: cpu@103 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a72";
114 reg = <0x103>;
115 enable-method = "psci";
116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
117 capacity-dmips-mhz = <1024>;
118 next-level-cache = <&l2_1>;
119 #cooling-cells = <2>;
120 };
121
122 cpu-map {
123 cluster0 {
124 core0 {
125 cpu = <&CPU0>;
126 };
127
128 core1 {
129 cpu = <&CPU1>;
130 };
131
132 core2 {
133 cpu = <&CPU2>;
134 };
135
136 core3 {
137 cpu = <&CPU3>;
138 };
139 };
140
141 cluster1 {
142 core0 {
143 cpu = <&CPU4>;
144 };
145
146 core1 {
147 cpu = <&CPU5>;
148 };
149
150 core2 {
151 cpu = <&CPU6>;
152 };
153
154 core3 {
155 cpu = <&CPU7>;
156 };
157 };
158 };
159
160 idle-states {
161 entry-method = "psci";
162
163 little_cpu_sleep_0: cpu-sleep-0-0 {
164 compatible = "arm,idle-state";
165 idle-state-name = "little-power-collapse";
166 arm,psci-suspend-param = <0x40000003>;
167 entry-latency-us = <181>;
168 exit-latency-us = <149>;
169 min-residency-us = <703>;
170 local-timer-stop;
171 };
172
173 big_cpu_sleep_0: cpu-sleep-1-0 {
174 compatible = "arm,idle-state";
175 idle-state-name = "big-retention";
176 arm,psci-suspend-param = <0x00000002>;
177 entry-latency-us = <142>;
178 exit-latency-us = <99>;
179 min-residency-us = <242>;
180 };
181
182 big_cpu_sleep_1: cpu-sleep-1-1 {
183 compatible = "arm,idle-state";
184 idle-state-name = "big-power-collapse";
185 arm,psci-suspend-param = <0x40000003>;
186 entry-latency-us = <158>;
187 exit-latency-us = <144>;
188 min-residency-us = <863>;
189 local-timer-stop;
190 };
191 };
192
193 l2_0: l2-cache0 {
194 compatible = "cache";
195 cache-level = <2>;
196 cache-unified;
197 };
198
199 l2_1: l2-cache1 {
200 compatible = "cache";
201 cache-level = <2>;
202 cache-unified;
203 };
204 };
205
206 firmware {
207 scm: scm {
208 compatible = "qcom,scm-msm8976", "qcom,scm";
209 clocks = <&gcc GCC_CRYPTO_CLK>,
210 <&gcc GCC_CRYPTO_AXI_CLK>,
211 <&gcc GCC_CRYPTO_AHB_CLK>;
212 clock-names = "core", "bus", "iface";
213 #reset-cells = <1>;
214
215 qcom,dload-mode = <&tcsr 0x6100>;
216 };
217 };
218
219 memory@80000000 {
220 device_type = "memory";
221 /* We expect the bootloader to fill in the size */
222 reg = <0x0 0x80000000 0x0 0x0>;
223 };
224
225 pmu-a53 {
226 compatible = "arm,cortex-a53-pmu";
227 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
228 };
229
230 pmu_a72: pmu-a72 {
231 compatible = "arm,cortex-a72-pmu";
232 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
233 };
234
235
236 psci {
237 compatible = "arm,psci-1.0";
238 method = "smc";
239 };
240
241 rpm: remoteproc {
242 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
243
244 smd-edge {
245 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
246 mboxes = <&apcs 0>;
247 qcom,smd-edge = <15>;
248
249 rpm_requests: rpm-requests {
250 compatible = "qcom,rpm-msm8976";
251 qcom,smd-channels = "rpm_requests";
252
253 rpmcc: clock-controller {
254 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
255 clocks = <&xo_board>;
256 clock-names = "xo";
257 #clock-cells = <1>;
258 };
259
260 rpmpd: power-controller {
261 compatible = "qcom,msm8976-rpmpd";
262 #power-domain-cells = <1>;
263 operating-points-v2 = <&rpmpd_opp_table>;
264
265 rpmpd_opp_table: opp-table {
266 compatible = "operating-points-v2";
267
268 rpmpd_opp_ret: opp1 {
269 opp-level = <RPM_SMD_LEVEL_RETENTION>;
270 };
271
272 rpmpd_opp_ret_plus: opp2 {
273 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
274 };
275
276 rpmpd_opp_min_svs: opp3 {
277 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
278 };
279
280 rpmpd_opp_low_svs: opp4 {
281 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
282 };
283
284 rpmpd_opp_svs: opp5 {
285 opp-level = <RPM_SMD_LEVEL_SVS>;
286 };
287
288 rpmpd_opp_svs_plus: opp6 {
289 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
290 };
291
292 rpmpd_opp_nom: opp7 {
293 opp-level = <RPM_SMD_LEVEL_NOM>;
294 };
295
296 rpmpd_opp_nom_plus: opp8 {
297 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
298 };
299
300 rpmpd_opp_turbo: opp9 {
301 opp-level = <RPM_SMD_LEVEL_TURBO>;
302 };
303
304 rpmpd_opp_turbo_no_cpr: opp10 {
305 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
306 };
307
308 rpmpd_opp_turbo_high: opp111 {
309 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
310 };
311 };
312 };
313 };
314 };
315 };
316
317 reserved-memory {
318 #address-cells = <2>;
319 #size-cells = <2>;
320 ranges;
321
322 ext-region@85b00000 {
323 reg = <0x0 0x85b00000 0x0 0x500000>;
324 no-map;
325 };
326
327 smem@86300000 {
328 compatible = "qcom,smem";
329 reg = <0x0 0x86300000 0x0 0x100000>;
330 no-map;
331
332 hwlocks = <&tcsr_mutex 3>;
333 qcom,rpm-msg-ram = <&rpm_msg_ram>;
334 };
335
336 reserved@86400000 {
337 reg = <0x0 0x86400000 0x0 0x800000>;
338 no-map;
339 };
340
341 mpss_mem: mpss@86c00000 {
342 reg = <0x0 0x86c00000 0x0 0x5600000>;
343 no-map;
344 };
345
346 lpass_mem: lpass@8c200000 {
347 reg = <0x0 0x8c200000 0x0 0x1000000>;
348 no-map;
349 };
350
351 wcnss_fw_mem: wcnss@8d200000 {
352 reg = <0x0 0x8d200000 0x0 0x800000>;
353 no-map;
354 };
355
356 venus_mem: memory@8da00000 {
357 reg = <0x0 0x8da00000 0x0 0x2600000>;
358 no-map;
359 };
360
361 tz-apps@8dd00000 {
362 reg = <0x0 0x8dd00000 0x0 0x1400000>;
363 no-map;
364 };
365 };
366
367 smp2p-hexagon {
368 compatible = "qcom,smp2p";
369 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
370 mboxes = <&apcs 10>;
371
372 qcom,local-pid = <0>;
373 qcom,remote-pid = <2>;
374 qcom,smem = <443>, <429>;
375
376 adsp_smp2p_out: master-kernel {
377 qcom,entry-name = "master-kernel";
378
379 #qcom,smem-state-cells = <1>;
380 };
381
382 adsp_smp2p_in: slave-kernel {
383 qcom,entry-name = "slave-kernel";
384
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 };
388 };
389
390 smp2p-modem {
391 compatible = "qcom,smp2p";
392 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
393 mboxes = <&apcs 14>;
394
395 qcom,local-pid = <0>;
396 qcom,remote-pid = <1>;
397 qcom,smem = <435>, <428>;
398
399 modem_smp2p_out: master-kernel {
400 qcom,entry-name = "master-kernel";
401
402 #qcom,smem-state-cells = <1>;
403 };
404
405 modem_smp2p_in: slave-kernel {
406 qcom,entry-name = "slave-kernel";
407
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411 };
412
413 smp2p-wcnss {
414 compatible = "qcom,smp2p";
415 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
416 mboxes = <&apcs 18>;
417
418 qcom,local-pid = <0>;
419 qcom,remote-pid = <4>;
420 qcom,smem = <451>, <431>;
421
422 wcnss_smp2p_out: master-kernel {
423 qcom,entry-name = "master-kernel";
424
425 #qcom,smem-state-cells = <1>;
426 };
427
428 wcnss_smp2p_in: slave-kernel {
429 qcom,entry-name = "slave-kernel";
430
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 };
434 };
435
436 smsm {
437 compatible = "qcom,smsm";
438
439 #address-cells = <1>;
440 #size-cells = <0>;
441
442 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
443
444 apps_smsm: apps@0 {
445 reg = <0>;
446 #qcom,smem-state-cells = <1>;
447 };
448
449 hexagon_smsm: hexagon@1 {
450 reg = <1>;
451 interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>;
452
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
456
457 wcnss_smsm: wcnss@6 {
458 reg = <6>;
459 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
460
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 };
464 };
465
466 soc: soc@0 {
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges = <0 0 0 0xffffffff>;
470 compatible = "simple-bus";
471
472 rng@22000 {
473 compatible = "qcom,prng";
474 reg = <0x00022000 0x140>;
475 clocks = <&gcc GCC_PRNG_AHB_CLK>;
476 clock-names = "core";
477 };
478
479 rpm_msg_ram: sram@60000 {
480 compatible = "qcom,rpm-msg-ram";
481 reg = <0x00060000 0x8000>;
482 };
483
484 usb_hs_phy: phy@6c000 {
485 compatible = "qcom,usb-hs-28nm-femtophy";
486 reg = <0x0006c000 0x200>;
487 #phy-cells = <0>;
488 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
489 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
490 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
491 clock-names = "ref", "ahb", "sleep";
492 resets = <&gcc RST_QUSB2_PHY_BCR>,
493 <&gcc RST_USB2_HS_PHY_ONLY_BCR>;
494 reset-names = "phy", "por";
495 status = "disabled";
496 };
497
498 qfprom: qfprom@a4000 {
499 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
500 reg = <0x000a4000 0x1000>;
501 #address-cells = <1>;
502 #size-cells = <1>;
503
504 tsens_base1: base1@218 {
505 reg = <0x218 1>;
506 bits = <0 8>;
507 };
508
509 tsens_s0_p1: s0-p1@219 {
510 reg = <0x219 0x1>;
511 bits = <0 6>;
512 };
513
514 tsens_s0_p2: s0-p2@219 {
515 reg = <0x219 0x2>;
516 bits = <6 6>;
517 };
518
519 tsens_s1_p1: s1-p1@21a {
520 reg = <0x21a 0x2>;
521 bits = <4 6>;
522 };
523
524 tsens_s1_p2: s1-p2@21b {
525 reg = <0x21b 0x1>;
526 bits = <2 6>;
527 };
528
529 tsens_s2_p1: s2-p1@21c {
530 reg = <0x21c 0x1>;
531 bits = <0 6>;
532 };
533
534 tsens_s2_p2: s2-p2@21c {
535 reg = <0x21c 0x2>;
536 bits = <6 6>;
537 };
538
539 tsens_s3_p1: s3-p1@21d {
540 reg = <0x21d 0x2>;
541 bits = <4 6>;
542 };
543
544 tsens_s3_p2: s3-p2@21e {
545 reg = <0x21e 0x1>;
546 bits = <2 6>;
547 };
548
549 tsens_base2: base2@220 {
550 reg = <0x220 1>;
551 bits = <0 8>;
552 };
553
554 tsens_s4_p1: s4-p1@221 {
555 reg = <0x221 0x1>;
556 bits = <0 6>;
557 };
558
559 tsens_s4_p2: s4-p2@221 {
560 reg = <0x221 0x2>;
561 bits = <6 6>;
562 };
563
564 tsens_s5_p1: s5-p1@222 {
565 reg = <0x222 0x2>;
566 bits = <4 6>;
567 };
568
569 tsens_s5_p2: s5-p2@223 {
570 reg = <0x224 0x1>;
571 bits = <2 6>;
572 };
573
574 tsens_s6_p1: s6-p1@224 {
575 reg = <0x224 0x1>;
576 bits = <0 6>;
577 };
578
579 tsens_s6_p2: s6-p2@224 {
580 reg = <0x224 0x2>;
581 bits = <6 6>;
582 };
583
584 tsens_s7_p1: s7-p1@225 {
585 reg = <0x225 0x2>;
586 bits = <4 6>;
587 };
588
589 tsens_s7_p2: s7-p2@226 {
590 reg = <0x226 0x2>;
591 bits = <2 6>;
592 };
593
594 tsens_mode: mode@228 {
595 reg = <0x228 1>;
596 bits = <0 3>;
597 };
598
599 tsens_s8_p1: s8-p1@228 {
600 reg = <0x228 0x2>;
601 bits = <3 6>;
602 };
603
604 tsens_s8_p2: s8-p2@229 {
605 reg = <0x229 0x1>;
606 bits = <1 6>;
607 };
608
609 tsens_s9_p1: s9-p1@229 {
610 reg = <0x229 0x2>;
611 bits = <7 6>;
612 };
613
614 tsens_s9_p2: s9-p2@22a {
615 reg = <0x22a 0x2>;
616 bits = <5 6>;
617 };
618
619 tsens_s10_p1: s10-p1@22b {
620 reg = <0x22b 0x2>;
621 bits = <3 6>;
622 };
623
624 tsens_s10_p2: s10-p2@22c {
625 reg = <0x22c 0x1>;
626 bits = <1 6>;
627 };
628 };
629
630 tsens: thermal-sensor@4a9000 {
631 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
632 reg = <0x004a9000 0x1000>, /* TM */
633 <0x004a8000 0x1000>; /* SROT */
634 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-names = "uplow";
636 nvmem-cells = <&tsens_mode>,
637 <&tsens_base1>, <&tsens_base2>,
638 <&tsens_s0_p1>, <&tsens_s0_p2>,
639 <&tsens_s1_p1>, <&tsens_s1_p2>,
640 <&tsens_s2_p1>, <&tsens_s2_p2>,
641 <&tsens_s3_p1>, <&tsens_s3_p2>,
642 <&tsens_s4_p1>, <&tsens_s4_p2>,
643 <&tsens_s5_p1>, <&tsens_s5_p2>,
644 <&tsens_s6_p1>, <&tsens_s6_p2>,
645 <&tsens_s7_p1>, <&tsens_s7_p2>,
646 <&tsens_s8_p1>, <&tsens_s8_p2>,
647 <&tsens_s9_p1>, <&tsens_s9_p2>,
648 <&tsens_s10_p1>, <&tsens_s10_p2>;
649 nvmem-cell-names = "mode",
650 "base1", "base2",
651 "s0_p1", "s0_p2",
652 "s1_p1", "s1_p2",
653 "s2_p1", "s2_p2",
654 "s3_p1", "s3_p2",
655 "s4_p1", "s4_p2",
656 "s5_p1", "s5_p2",
657 "s6_p1", "s6_p2",
658 "s7_p1", "s7_p2",
659 "s8_p1", "s8_p2",
660 "s9_p1", "s9_p2",
661 "s10_p1", "s10_p2";
662 #qcom,sensors = <11>;
663 #thermal-sensor-cells = <1>;
664 };
665
666 tlmm: pinctrl@1000000 {
667 compatible = "qcom,msm8976-pinctrl";
668 reg = <0x01000000 0x300000>;
669 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
670 #gpio-cells = <2>;
671 gpio-controller;
672 gpio-ranges = <&tlmm 0 0 145>;
673 interrupt-controller;
674 #interrupt-cells = <2>;
675
676 spi1_default: spi0-default-state {
677 spi-pins {
678 pins = "gpio0", "gpio1", "gpio3";
679 function = "blsp_spi1";
680 drive-strength = <12>;
681 bias-disable;
682 };
683
684 cs-pins {
685 pins = "gpio2";
686 function = "blsp_spi1";
687 drive-strength = <2>;
688 bias-disable;
689 };
690 };
691
692 spi1_sleep: spi0-sleep-state {
693 spi-pins {
694 pins = "gpio0", "gpio1", "gpio3";
695 function = "gpio";
696 drive-strength = <2>;
697 bias-pull-down;
698 };
699
700 cs-pins {
701 pins = "gpio2";
702 function = "gpio";
703 drive-strength = <2>;
704 bias-disable;
705 };
706 };
707
708 blsp1_i2c2_default: blsp1-i2c2-default-state {
709 pins = "gpio6", "gpio7";
710 function = "blsp_i2c2";
711 drive-strength = <2>;
712 bias-disable;
713 };
714
715 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
716 pins = "gpio6", "gpio7";
717 function = "gpio";
718 drive-strength = <2>;
719 bias-disable;
720 };
721
722 blsp1_i2c4_default: blsp1-i2c4-default-state {
723 pins = "gpio14", "gpio15";
724 function = "blsp_i2c4";
725 drive-strength = <2>;
726 bias-disable;
727 };
728
729 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
730 pins = "gpio14", "gpio15";
731 function = "gpio";
732 drive-strength = <2>;
733 bias-disable;
734 };
735
736 blsp2_uart2_active: blsp2-uart2-active-state {
737 pins = "gpio20", "gpio21";
738 function = "blsp_uart6";
739 drive-strength = <4>;
740 bias-disable;
741 };
742
743 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
744 pins = "gpio20", "gpio21";
745 function = "gpio";
746 drive-strength = <2>;
747 bias-disable;
748 };
749
750 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */
751 blsp2_i2c2_default: blsp2-i2c2-default-state {
752 pins = "gpio22", "gpio23";
753 function = "blsp_i2c6";
754 drive-strength = <2>;
755 bias-disable;
756 };
757
758 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
759 pins = "gpio22", "gpio23";
760 function = "gpio";
761 drive-strength = <2>;
762 bias-disable;
763 };
764
765 blsp2_i2c4_default: blsp2-i2c4-default-state {
766 pins = "gpio18", "gpio19";
767 function = "blsp_i2c8";
768 drive-strength = <2>;
769 bias-disable;
770 };
771
772 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
773 pins = "gpio18", "gpio19";
774 function = "gpio";
775 drive-strength = <2>;
776 bias-disable;
777 };
778
779 wcss_wlan_default: wcss-wlan-default-state {
780 wcss-wlan2-pins {
781 pins = "gpio40";
782 function = "wcss_wlan2";
783 drive-strength = <6>;
784 bias-pull-up;
785 };
786
787 wcss-wlan1-pins {
788 pins = "gpio41";
789 function = "wcss_wlan1";
790 drive-strength = <6>;
791 bias-pull-up;
792 };
793
794 wcss-wlan0-pins {
795 pins = "gpio42";
796 function = "wcss_wlan0";
797 drive-strength = <6>;
798 bias-pull-up;
799 };
800
801 wcss-wlan-pins {
802 pins = "gpio43", "gpio44";
803 function = "wcss_wlan";
804 drive-strength = <6>;
805 bias-pull-up;
806 };
807 };
808 };
809
810 gcc: clock-controller@1800000 {
811 compatible = "qcom,gcc-msm8976";
812 reg = <0x01800000 0x80000>;
813 #clock-cells = <1>;
814 #reset-cells = <1>;
815 #power-domain-cells = <1>;
816
817 assigned-clocks = <&gcc GPLL3>;
818 assigned-clock-rates = <1100000000>;
819
820 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
821 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
822 <&mdss_dsi0_phy 1>,
823 <&mdss_dsi0_phy 0>,
824 <&mdss_dsi1_phy 1>,
825 <&mdss_dsi1_phy 0>;
826 clock-names = "xo",
827 "xo_a",
828 "dsi0pll",
829 "dsi0pllbyte",
830 "dsi1pll",
831 "dsi1pllbyte";
832 };
833
834 tcsr_mutex: hwlock@1905000 {
835 compatible = "qcom,tcsr-mutex";
836 reg = <0x01905000 0x20000>;
837 #hwlock-cells = <1>;
838 };
839
840 tcsr: syscon@1937000 {
841 compatible = "qcom,msm8976-tcsr", "syscon";
842 reg = <0x01937000 0x30000>;
843 };
844
845 mdss: display-subsystem@1a00000 {
846 compatible = "qcom,mdss";
847
848 reg = <0x01a00000 0x1000>,
849 <0x01ab0000 0x3000>;
850 reg-names = "mdss_phys", "vbif_phys";
851
852 power-domains = <&gcc MDSS_GDSC>;
853 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
854
855 interrupt-controller;
856 #interrupt-cells = <1>;
857
858 clocks = <&gcc GCC_MDSS_AHB_CLK>,
859 <&gcc GCC_MDSS_AXI_CLK>,
860 <&gcc GCC_MDSS_VSYNC_CLK>,
861 <&gcc GCC_MDSS_MDP_CLK>;
862 clock-names = "iface",
863 "bus",
864 "vsync",
865 "core";
866
867 #address-cells = <1>;
868 #size-cells = <1>;
869 ranges;
870
871 status = "disabled";
872
873 mdss_mdp: display-controller@1a01000 {
874 compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
875 reg = <0x01a01000 0x89000>;
876 reg-names = "mdp_phys";
877
878 interrupt-parent = <&mdss>;
879 interrupts = <0>;
880
881 clocks = <&gcc GCC_MDSS_AHB_CLK>,
882 <&gcc GCC_MDSS_AXI_CLK>,
883 <&gcc GCC_MDSS_MDP_CLK>,
884 <&gcc GCC_MDSS_VSYNC_CLK>,
885 <&gcc GCC_MDP_TBU_CLK>,
886 <&gcc GCC_MDP_RT_TBU_CLK>;
887 clock-names = "iface",
888 "bus",
889 "core",
890 "vsync",
891 "tbu",
892 "tbu_rt";
893
894 operating-points-v2 = <&mdp_opp_table>;
895 power-domains = <&gcc MDSS_GDSC>;
896
897 iommus = <&apps_iommu 22>;
898
899 ports {
900 #address-cells = <1>;
901 #size-cells = <0>;
902
903 port@0 {
904 reg = <0>;
905
906 mdss_mdp5_intf1_out: endpoint {
907 remote-endpoint = <&mdss_dsi0_in>;
908 };
909 };
910
911 port@1 {
912 reg = <1>;
913
914 mdss_mdp5_intf2_out: endpoint {
915 remote-endpoint = <&mdss_dsi1_in>;
916 };
917 };
918 };
919
920 mdp_opp_table: opp-table {
921 compatible = "operating-points-v2";
922
923 opp-177780000 {
924 opp-hz = /bits/ 64 <177780000>;
925 required-opps = <&rpmpd_opp_svs>;
926 };
927
928 opp-270000000 {
929 opp-hz = /bits/ 64 <270000000>;
930 required-opps = <&rpmpd_opp_svs_plus>;
931 };
932
933 opp-320000000 {
934 opp-hz = /bits/ 64 <320000000>;
935 required-opps = <&rpmpd_opp_nom>;
936 };
937
938 opp-360000000 {
939 opp-hz = /bits/ 64 <360000000>;
940 required-opps = <&rpmpd_opp_turbo>;
941 };
942 };
943 };
944
945 mdss_dsi0: dsi@1a94000 {
946 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
947 reg = <0x01a94000 0x300>;
948 reg-names = "dsi_ctrl";
949
950 interrupt-parent = <&mdss>;
951 interrupts = <4>;
952
953 clocks = <&gcc GCC_MDSS_MDP_CLK>,
954 <&gcc GCC_MDSS_AHB_CLK>,
955 <&gcc GCC_MDSS_AXI_CLK>,
956 <&gcc GCC_MDSS_BYTE0_CLK>,
957 <&gcc GCC_MDSS_PCLK0_CLK>,
958 <&gcc GCC_MDSS_ESC0_CLK>;
959 clock-names = "mdp_core",
960 "iface",
961 "bus",
962 "byte",
963 "pixel",
964 "core";
965
966 assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
967 <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
968 assigned-clock-parents = <&mdss_dsi0_phy 0>,
969 <&mdss_dsi0_phy 1>;
970
971 phys = <&mdss_dsi0_phy>;
972
973 operating-points-v2 = <&dsi0_opp_table>;
974 power-domains = <&gcc MDSS_GDSC>;
975
976 #address-cells = <1>;
977 #size-cells = <0>;
978
979 status = "disabled";
980
981 ports {
982 #address-cells = <1>;
983 #size-cells = <0>;
984
985 port@0 {
986 reg = <0>;
987
988 mdss_dsi0_in: endpoint {
989 remote-endpoint = <&mdss_mdp5_intf1_out>;
990 };
991 };
992
993 port@1 {
994 reg = <1>;
995
996 mdss_dsi0_out: endpoint {
997 };
998 };
999 };
1000
1001 dsi0_opp_table: opp-table {
1002 compatible = "operating-points-v2";
1003
1004 opp-125000000 {
1005 opp-hz = /bits/ 64 <125000000>;
1006 required-opps = <&rpmpd_opp_svs>;
1007 };
1008
1009 opp-161250000 {
1010 opp-hz = /bits/ 64 <161250000>;
1011 required-opps = <&rpmpd_opp_svs_plus>;
1012 };
1013
1014 opp-187500000 {
1015 opp-hz = /bits/ 64 <187500000>;
1016 required-opps = <&rpmpd_opp_nom>;
1017 };
1018 };
1019 };
1020
1021 mdss_dsi1: dsi@1a96000 {
1022 compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1023 reg = <0x01a96000 0x300>;
1024 reg-names = "dsi_ctrl";
1025
1026 interrupt-parent = <&mdss>;
1027 interrupts = <5>;
1028
1029 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1030 <&gcc GCC_MDSS_AHB_CLK>,
1031 <&gcc GCC_MDSS_AXI_CLK>,
1032 <&gcc GCC_MDSS_BYTE1_CLK>,
1033 <&gcc GCC_MDSS_PCLK1_CLK>,
1034 <&gcc GCC_MDSS_ESC1_CLK>;
1035 clock-names = "mdp_core",
1036 "iface",
1037 "bus",
1038 "byte",
1039 "pixel",
1040 "core";
1041
1042 assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
1043 <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
1044 assigned-clock-parents = <&mdss_dsi1_phy 0>,
1045 <&mdss_dsi1_phy 1>;
1046
1047 phys = <&mdss_dsi1_phy>;
1048
1049 operating-points-v2 = <&dsi0_opp_table>;
1050 power-domains = <&gcc MDSS_GDSC>;
1051
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054
1055 status = "disabled";
1056
1057 ports {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060
1061 port@0 {
1062 reg = <0>;
1063
1064 mdss_dsi1_in: endpoint {
1065 remote-endpoint = <&mdss_mdp5_intf2_out>;
1066 };
1067 };
1068
1069 port@1 {
1070 reg = <1>;
1071
1072 mdss_dsi1_out: endpoint {
1073 };
1074 };
1075 };
1076 };
1077
1078 mdss_dsi0_phy: phy@1a94a00 {
1079 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1080 reg = <0x01a94a00 0xd4>,
1081 <0x01a94400 0x280>,
1082 <0x01a94b80 0x30>;
1083 reg-names = "dsi_pll",
1084 "dsi_phy",
1085 "dsi_phy_regulator";
1086
1087 #clock-cells = <1>;
1088 #phy-cells = <0>;
1089
1090 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1091 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1092 clock-names = "iface", "ref";
1093
1094 status = "disabled";
1095 };
1096
1097 mdss_dsi1_phy: phy@1a96a00 {
1098 compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
1099 reg = <0x01a96a00 0xd4>,
1100 <0x01a96400 0x280>,
1101 <0x01a96b80 0x30>;
1102 reg-names = "dsi_pll",
1103 "dsi_phy",
1104 "dsi_phy_regulator";
1105
1106 #clock-cells = <1>;
1107 #phy-cells = <0>;
1108
1109 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1110 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1111 clock-names = "iface", "ref";
1112
1113 status = "disabled";
1114 };
1115 };
1116
1117 adreno_gpu: gpu@1c00000 {
1118 compatible = "qcom,adreno-510.0", "qcom,adreno";
1119
1120 reg = <0x01c00000 0x40000>;
1121 reg-names = "kgsl_3d0_reg_memory";
1122
1123 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1124 interrupt-names = "kgsl_3d0_irq";
1125
1126 clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
1127 <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
1128 <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
1129 <&gcc GCC_GFX3D_BIMC_CLK>,
1130 <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
1131 <&gcc GCC_GFX3D_OXILI_AON_CLK>;
1132 clock-names = "core",
1133 "iface",
1134 "mem",
1135 "mem_iface",
1136 "rbbmtimer",
1137 "alwayson";
1138
1139 power-domains = <&gcc OXILI_GX_GDSC>;
1140
1141 iommus = <&gpu_iommu 0>;
1142
1143 operating-points-v2 = <&gpu_opp_table>;
1144
1145 status = "disabled";
1146
1147 gpu_opp_table: opp-table {
1148 compatible = "operating-points-v2";
1149
1150 opp-200000000 {
1151 opp-hz = /bits/ 64 <200000000>;
1152 required-opps = <&rpmpd_opp_low_svs>;
1153 opp-supported-hw = <0xff>;
1154 };
1155
1156 opp-300000000 {
1157 opp-hz = /bits/ 64 <300000000>;
1158 required-opps = <&rpmpd_opp_svs>;
1159 opp-supported-hw = <0xff>;
1160 };
1161
1162 opp-400000000 {
1163 opp-hz = /bits/ 64 <400000000>;
1164 required-opps = <&rpmpd_opp_nom>;
1165 opp-supported-hw = <0xff>;
1166 };
1167
1168 opp-480000000 {
1169 opp-hz = /bits/ 64 <480000000>;
1170 required-opps = <&rpmpd_opp_nom_plus>;
1171 opp-supported-hw = <0xff>;
1172 };
1173
1174 opp-540000000 {
1175 opp-hz = /bits/ 64 <540000000>;
1176 required-opps = <&rpmpd_opp_turbo>;
1177 opp-supported-hw = <0xff>;
1178 };
1179
1180 opp-600000000 {
1181 opp-hz = /bits/ 64 <600000000>;
1182 required-opps = <&rpmpd_opp_turbo>;
1183 opp-supported-hw = <0xff>;
1184 };
1185 };
1186 };
1187
1188 apps_iommu: iommu@1ee0000 {
1189 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1190 reg = <0x01ee0000 0x3000>;
1191 ranges = <0 0x01e20000 0x20000>;
1192
1193 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1194 <&gcc GCC_APSS_TCU_CLK>;
1195 clock-names = "iface", "bus";
1196
1197 qcom,iommu-secure-id = <17>;
1198
1199 #address-cells = <1>;
1200 #size-cells = <1>;
1201 #iommu-cells = <1>;
1202
1203 /* VFE */
1204 iommu-ctx@15000 {
1205 compatible = "qcom,msm-iommu-v2-ns";
1206 reg = <0x15000 0x1000>;
1207 qcom,ctx-asid = <20>;
1208 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1209 };
1210
1211 /* VENUS NS */
1212 iommu-ctx@16000 {
1213 compatible = "qcom,msm-iommu-v2-ns";
1214 reg = <0x16000 0x1000>;
1215 qcom,ctx-asid = <21>;
1216 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1217 };
1218
1219 /* MDP0 */
1220 iommu-ctx@17000 {
1221 compatible = "qcom,msm-iommu-v2-ns";
1222 reg = <0x17000 0x1000>;
1223 qcom,ctx-asid = <22>;
1224 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1225 };
1226 };
1227
1228 gpu_iommu: iommu@1f08000 {
1229 compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
1230 ranges = <0 0x01f08000 0x8000>;
1231
1232 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1233 <&gcc GCC_GFX3D_TCU_CLK>;
1234 clock-names = "iface", "bus";
1235
1236 power-domains = <&gcc OXILI_CX_GDSC>;
1237
1238 qcom,iommu-secure-id = <18>;
1239
1240 #address-cells = <1>;
1241 #size-cells = <1>;
1242 #iommu-cells = <1>;
1243
1244 /* gfx3d user */
1245 iommu-ctx@0 {
1246 compatible = "qcom,msm-iommu-v2-ns";
1247 reg = <0x0 0x1000>;
1248 qcom,ctx-asid = <0>;
1249 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1250 };
1251
1252 /* gfx3d secure */
1253 iommu-ctx@1000 {
1254 compatible = "qcom,msm-iommu-v2-sec";
1255 reg = <0x1000 0x1000>;
1256 qcom,ctx-asid = <2>;
1257 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1258 };
1259
1260 /* gfx3d priv */
1261 iommu-ctx@2000 {
1262 compatible = "qcom,msm-iommu-v2-sec";
1263 reg = <0x2000 0x1000>;
1264 qcom,ctx-asid = <1>;
1265 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1266 };
1267 };
1268
1269 spmi_bus: spmi@200f000 {
1270 compatible = "qcom,spmi-pmic-arb";
1271 reg = <0x0200f000 0x1000>,
1272 <0x02400000 0x800000>,
1273 <0x02c00000 0x800000>,
1274 <0x03800000 0x200000>,
1275 <0x0200a000 0x2100>;
1276 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1277 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1278 interrupt-names = "periph_irq";
1279 qcom,channel = <0>;
1280 qcom,ee = <0>;
1281
1282 #address-cells = <2>;
1283 #size-cells = <0>;
1284 interrupt-controller;
1285 #interrupt-cells = <4>;
1286 };
1287
1288 sdhc_1: mmc@7824900 {
1289 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1290 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1291 reg-names = "hc", "core";
1292
1293 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1295 interrupt-names = "hc_irq", "pwr_irq";
1296
1297 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1298 <&gcc GCC_SDCC1_APPS_CLK>,
1299 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1300 clock-names = "iface", "core", "xo";
1301 status = "disabled";
1302 };
1303
1304 sdhc_2: mmc@7864900 {
1305 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1306 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1307 reg-names = "hc", "core";
1308
1309 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1311 interrupt-names = "hc_irq", "pwr_irq";
1312
1313 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1314 <&gcc GCC_SDCC2_APPS_CLK>,
1315 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1316 clock-names = "iface", "core", "xo";
1317 status = "disabled";
1318 };
1319
1320 blsp1_dma: dma-controller@7884000 {
1321 compatible = "qcom,bam-v1.7.0";
1322 reg = <0x07884000 0x1f000>;
1323 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1325 clock-names = "bam_clk";
1326 #dma-cells = <1>;
1327 qcom,ee = <0>;
1328 };
1329
1330 blsp1_uart1: serial@78af000 {
1331 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1332 reg = <0x078af000 0x200>;
1333 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1334 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1335 clock-names = "core", "iface";
1336 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1337 dma-names = "tx", "rx";
1338 status = "disabled";
1339 };
1340
1341 blsp1_uart2: serial@78b0000 {
1342 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1343 reg = <0x078b0000 0x200>;
1344 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1346 clock-names = "core", "iface";
1347 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1348 dma-names = "tx", "rx";
1349 status = "disabled";
1350 };
1351
1352 blsp1_spi1: spi@78b5000 {
1353 compatible = "qcom,spi-qup-v2.2.1";
1354 reg = <0x078b5000 0x500>;
1355 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1356 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1357 clock-names = "core", "iface";
1358 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1359 dma-names = "tx", "rx";
1360 pinctrl-names = "default", "sleep";
1361 pinctrl-0 = <&spi1_default>;
1362 pinctrl-1 = <&spi1_sleep>;
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1365 status = "disabled";
1366 };
1367
1368 blsp1_i2c2: i2c@78b6000 {
1369 compatible = "qcom,i2c-qup-v2.2.1";
1370 reg = <0x078b6000 0x500>;
1371 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1372 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1373 clock-names = "core", "iface";
1374 clock-frequency = <400000>;
1375 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1376 dma-names = "tx", "rx";
1377 pinctrl-names = "default", "sleep";
1378 pinctrl-0 = <&blsp1_i2c2_default>;
1379 pinctrl-1 = <&blsp1_i2c2_default>;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 status = "disabled";
1383 };
1384
1385 blsp1_i2c4: i2c@78b8000 {
1386 compatible = "qcom,i2c-qup-v2.2.1";
1387 reg = <0x078b8000 0x500>;
1388 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1390 clock-names = "core", "iface";
1391 clock-frequency = <400000>;
1392 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1393 dma-names = "tx", "rx";
1394 pinctrl-names = "default", "sleep";
1395 pinctrl-0 = <&blsp1_i2c4_default>;
1396 pinctrl-1 = <&blsp1_i2c4_sleep>;
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1399 status = "disabled";
1400 };
1401
1402 otg: usb@78db000 {
1403 compatible = "qcom,ci-hdrc";
1404 reg = <0x078db000 0x200>,
1405 <0x078db200 0x200>;
1406 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
1409 clock-names = "iface", "core";
1410 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1411 assigned-clock-rates = <80000000>;
1412 resets = <&gcc RST_USB_HS_BCR>;
1413 reset-names = "core";
1414 ahb-burst-config = <0>;
1415 dr_mode = "peripheral";
1416 phy_type = "ulpi";
1417 phy-names = "usb-phy";
1418 phys = <&usb_hs_phy>;
1419 status = "disabled";
1420 #reset-cells = <1>;
1421 };
1422
1423 sdhc_3: mmc@7a24900 {
1424 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
1425 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
1426 reg-names = "hc", "core";
1427
1428 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1430 interrupt-names = "hc_irq", "pwr_irq";
1431
1432 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
1433 <&gcc GCC_SDCC3_APPS_CLK>,
1434 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1435 clock-names = "iface", "core", "xo";
1436
1437 status = "disabled";
1438 };
1439
1440 blsp2_dma: dma-controller@7ac4000 {
1441 compatible = "qcom,bam-v1.7.0";
1442 reg = <0x07ac4000 0x1f000>;
1443 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1445 clock-names = "bam_clk";
1446 #dma-cells = <1>;
1447 qcom,ee = <0>;
1448 };
1449
1450 blsp2_uart2: serial@7af0000 {
1451 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1452 reg = <0x07af0000 0x200>;
1453 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1454 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1455 clock-names = "core", "iface";
1456 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1457 dma-names = "tx", "rx";
1458 status = "disabled";
1459 };
1460
1461 blsp2_i2c2: i2c@7af6000 {
1462 compatible = "qcom,i2c-qup-v2.2.1";
1463 reg = <0x07af6000 0x600>;
1464 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1465 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1466 clock-names = "core", "iface";
1467 clock-frequency = <400000>;
1468 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1469 dma-names = "tx", "rx";
1470 pinctrl-names = "default", "sleep";
1471 pinctrl-0 = <&blsp2_i2c2_default>;
1472 pinctrl-1 = <&blsp2_i2c2_sleep>;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1475 status = "disabled";
1476 };
1477
1478 blsp2_i2c4: i2c@7af8000 {
1479 compatible = "qcom,i2c-qup-v2.2.1";
1480 reg = <0x07af8000 0x600>;
1481 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1483 clock-names = "core", "iface";
1484 clock-frequency = <400000>;
1485 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1486 dma-names = "tx", "rx";
1487 pinctrl-names = "default", "sleep";
1488 pinctrl-0 = <&blsp2_i2c4_default>;
1489 pinctrl-1 = <&blsp2_i2c4_sleep>;
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1492 status = "disabled";
1493 };
1494
1495 wcnss: remoteproc@a204000 {
1496 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1497 reg = <0x0a204000 0x2000>,
1498 <0x0a202000 0x1000>,
1499 <0x0a21b000 0x3000>;
1500 reg-names = "ccu",
1501 "dxe",
1502 "pmu";
1503
1504 memory-region = <&wcnss_fw_mem>;
1505
1506 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1507 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1508 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1509 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1510 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1511 interrupt-names = "wdog",
1512 "fatal",
1513 "ready",
1514 "handover",
1515 "stop-ack";
1516
1517 power-domains = <&rpmpd MSM8976_VDDCX>,
1518 <&rpmpd MSM8976_VDDMX>;
1519 power-domain-names = "cx", "mx";
1520
1521 qcom,smem-states = <&wcnss_smp2p_out 0>;
1522 qcom,smem-state-names = "stop";
1523
1524 pinctrl-0 = <&wcss_wlan_default>;
1525 pinctrl-names = "default";
1526
1527 status = "disabled";
1528
1529 wcnss_iris: iris {
1530 /* Separate chip, compatible is board-specific */
1531 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1532 clock-names = "xo";
1533 };
1534
1535 smd-edge {
1536 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1537
1538 mboxes = <&apcs 17>;
1539 qcom,smd-edge = <6>;
1540 qcom,remote-pid = <4>;
1541
1542 label = "pronto";
1543
1544 wcnss_ctrl: wcnss {
1545 compatible = "qcom,wcnss";
1546 qcom,smd-channels = "WCNSS_CTRL";
1547
1548 qcom,mmio = <&wcnss>;
1549
1550 wcnss_bt: bluetooth {
1551 compatible = "qcom,wcnss-bt";
1552 };
1553
1554 wcnss_wifi: wifi {
1555 compatible = "qcom,wcnss-wlan";
1556
1557 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1559 interrupt-names = "tx", "rx";
1560
1561 qcom,smem-states = <&apps_smsm 10>,
1562 <&apps_smsm 9>;
1563 qcom,smem-state-names = "tx-enable",
1564 "tx-rings-empty";
1565 };
1566 };
1567 };
1568 };
1569
1570 intc: interrupt-controller@b000000 {
1571 compatible = "qcom,msm-qgic2";
1572 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1573 interrupt-controller;
1574 #interrupt-cells = <3>;
1575 };
1576
1577 apcs: mailbox@b011000 {
1578 compatible = "qcom,msm8976-apcs-kpss-global",
1579 "qcom,msm8994-apcs-kpss-global", "syscon";
1580 reg = <0x0b011000 0x1000>;
1581 #mbox-cells = <1>;
1582 };
1583
1584 timer@b120000 {
1585 compatible = "arm,armv7-timer-mem";
1586 reg = <0x0b120000 0x1000>;
1587 #address-cells = <1>;
1588 #size-cells = <1>;
1589 ranges;
1590 clock-frequency = <19200000>;
1591
1592 frame@b121000 {
1593 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
1594 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1595 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1596 frame-number = <0>;
1597 };
1598
1599 frame@b123000 {
1600 reg = <0x0b123000 0x1000>;
1601 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1602 frame-number = <1>;
1603 status = "disabled";
1604 };
1605
1606 frame@b124000 {
1607 reg = <0x0b124000 0x1000>;
1608 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1609 frame-number = <2>;
1610 status = "disabled";
1611 };
1612
1613 frame@b125000 {
1614 reg = <0x0b125000 0x1000>;
1615 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1616 frame-number = <3>;
1617 status = "disabled";
1618 };
1619
1620 frame@b126000 {
1621 reg = <0x0b126000 0x1000>;
1622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1623 frame-number = <4>;
1624 status = "disabled";
1625 };
1626
1627 frame@b127000 {
1628 reg = <0x0b127000 0x1000>;
1629 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1630 frame-number = <5>;
1631 status = "disabled";
1632 };
1633
1634 frame@b128000 {
1635 reg = <0x0b128000 0x1000>;
1636 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1637 frame-number = <6>;
1638 status = "disabled";
1639 };
1640 };
1641
1642 imem: sram@8600000 {
1643 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1644 reg = <0x08600000 0x1000>;
1645 #address-cells = <1>;
1646 #size-cells = <1>;
1647
1648 ranges = <0 0x08600000 0x1000>;
1649
1650 pil-reloc@94c {
1651 compatible = "qcom,pil-reloc-info";
1652 reg = <0x94c 0xc8>;
1653 };
1654 };
1655 };
1656
1657 thermal-zones {
1658 aoss0-thermal {
1659 polling-delay-passive = <250>;
1660
1661 thermal-sensors = <&tsens 0>;
1662
1663 trips {
1664 aoss0_alert0: trip-point0 {
1665 temperature = <75000>;
1666 hysteresis = <2000>;
1667 type = "hot";
1668 };
1669 };
1670 };
1671
1672 modem-thermal {
1673 polling-delay-passive = <250>;
1674
1675 thermal-sensors = <&tsens 1>;
1676 trips {
1677 modem_alert0: trip-point0 {
1678 temperature = <75000>;
1679 hysteresis = <2000>;
1680 type = "hot";
1681 };
1682 };
1683 };
1684
1685 qdsp-thermal {
1686 polling-delay-passive = <250>;
1687
1688 thermal-sensors = <&tsens 2>;
1689 trips {
1690 qdsp_alert0: trip-point0 {
1691 temperature = <75000>;
1692 hysteresis = <2000>;
1693 type = "hot";
1694 };
1695 };
1696 };
1697
1698 cam-isp-thermal {
1699 polling-delay-passive = <250>;
1700
1701 thermal-sensors = <&tsens 3>;
1702 trips {
1703 cam_isp_alert0: trip-point0 {
1704 temperature = <75000>;
1705 hysteresis = <2000>;
1706 type = "hot";
1707 };
1708 };
1709 };
1710
1711 cpu4-thermal {
1712 polling-delay-passive = <250>;
1713
1714 thermal-sensors = <&tsens 4>;
1715
1716 trips {
1717 cpu4_alert0: trip-point0 {
1718 temperature = <50000>;
1719 hysteresis = <2000>;
1720 type = "hot";
1721 };
1722 cpu4_alert1: trip-point1 {
1723 temperature = <55000>;
1724 hysteresis = <2000>;
1725 type = "passive";
1726 };
1727 cpu4_crit: cpu-crit {
1728 temperature = <75000>;
1729 hysteresis = <2000>;
1730 type = "critical";
1731 };
1732 };
1733 };
1734
1735 cpu5-thermal {
1736 polling-delay-passive = <250>;
1737
1738 thermal-sensors = <&tsens 5>;
1739
1740 trips {
1741 cpu5_alert0: trip-point0 {
1742 temperature = <50000>;
1743 hysteresis = <2000>;
1744 type = "hot";
1745 };
1746 cpu5_alert1: trip-point1 {
1747 temperature = <55000>;
1748 hysteresis = <2000>;
1749 type = "passive";
1750 };
1751 cpu5_crit: cpu-crit {
1752 temperature = <75000>;
1753 hysteresis = <2000>;
1754 type = "critical";
1755 };
1756 };
1757 };
1758
1759 cpu6-thermal {
1760 polling-delay-passive = <250>;
1761
1762 thermal-sensors = <&tsens 6>;
1763
1764 trips {
1765 cpu6_alert0: trip-point0 {
1766 temperature = <50000>;
1767 hysteresis = <2000>;
1768 type = "hot";
1769 };
1770 cpu6_alert1: trip-point1 {
1771 temperature = <55000>;
1772 hysteresis = <2000>;
1773 type = "passive";
1774 };
1775 cpu6_crit: cpu-crit {
1776 temperature = <75000>;
1777 hysteresis = <2000>;
1778 type = "critical";
1779 };
1780 };
1781 };
1782
1783 cpu7-thermal {
1784 polling-delay-passive = <250>;
1785
1786 thermal-sensors = <&tsens 7>;
1787
1788 trips {
1789 cpu7_alert0: trip-point0 {
1790 temperature = <50000>;
1791 hysteresis = <2000>;
1792 type = "hot";
1793 };
1794 cpu7_alert1: trip-point1 {
1795 temperature = <55000>;
1796 hysteresis = <2000>;
1797 type = "passive";
1798 };
1799 cpu7_crit: cpu-crit {
1800 temperature = <75000>;
1801 hysteresis = <2000>;
1802 type = "critical";
1803 };
1804 };
1805 };
1806
1807 big-l2-thermal {
1808 polling-delay-passive = <250>;
1809
1810 thermal-sensors = <&tsens 8>;
1811
1812 trips {
1813 l2_alert0: trip-point0 {
1814 temperature = <50000>;
1815 hysteresis = <2000>;
1816 type = "hot";
1817 };
1818 l2_alert1: trip-point1 {
1819 temperature = <55000>;
1820 hysteresis = <2000>;
1821 type = "passive";
1822 };
1823 l2_crit: l2-crit {
1824 temperature = <75000>;
1825 hysteresis = <2000>;
1826 type = "critical";
1827 };
1828 };
1829 };
1830
1831 cpu0-thermal {
1832 polling-delay-passive = <250>;
1833
1834 thermal-sensors = <&tsens 9>;
1835
1836 trips {
1837 cpu0_alert0: trip-point0 {
1838 temperature = <50000>;
1839 hysteresis = <2000>;
1840 type = "hot";
1841 };
1842 cpu0_alert1: trip-point1 {
1843 temperature = <55000>;
1844 hysteresis = <2000>;
1845 type = "passive";
1846 };
1847 cpu0_crit: cpu-crit {
1848 temperature = <75000>;
1849 hysteresis = <2000>;
1850 type = "critical";
1851 };
1852 };
1853 };
1854
1855 gpu-thermal {
1856 polling-delay-passive = <250>;
1857
1858 thermal-sensors = <&tsens 10>;
1859
1860 trips {
1861 gpu_alert0: trip-point0 {
1862 temperature = <50000>;
1863 hysteresis = <2000>;
1864 type = "hot";
1865 };
1866 gpu_alert1: trip-point1 {
1867 temperature = <55000>;
1868 hysteresis = <2000>;
1869 type = "passive";
1870 };
1871 gpu_crit: gpu-crit {
1872 temperature = <75000>;
1873 hysteresis = <2000>;
1874 type = "critical";
1875 };
1876 };
1877 };
1878 };
1879
1880 timer {
1881 compatible = "arm,armv8-timer";
1882 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1883 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1884 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1885 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1886 clock-frequency = <19200000>;
1887 };
1888 };
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