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TOMOYO Linux Cross Reference
Linux/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts

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  1 // SPDX-License-Identifier: BSD-3-Clause
  2 /*
  3  * Xiaomi Mi 6 (sagit) device tree source based on msm8998-mtp.dtsi
  4  *
  5  * Copyright (c) 2022, The Linux Foundation. All rights reserved.
  6  * Copyright (c) 2022, Degdag Mohamed <degdagmohamed@gmail.com>
  7  * Copyright (c) 2022, Dzmitry Sankouski <dsankouski@gmail.com>
  8  */
  9 
 10 /dts-v1/;
 11 
 12 #include "msm8998.dtsi"
 13 #include "pm8005.dtsi"
 14 #include "pm8998.dtsi"
 15 #include "pmi8998.dtsi"
 16 #include <dt-bindings/input/input.h>
 17 #include <dt-bindings/leds/common.h>
 18 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 19 
 20 /*
 21  * Delete following upstream (msm8998.dtsi) reserved
 22  * memory mappings which are different in this device.
 23  */
 24 /delete-node/ &adsp_mem;
 25 /delete-node/ &mpss_mem;
 26 /delete-node/ &venus_mem;
 27 /delete-node/ &mba_mem;
 28 /delete-node/ &slpi_mem;
 29 /delete-node/ &ipa_fw_mem;
 30 /delete-node/ &ipa_gsi_mem;
 31 /delete-node/ &gpu_mem;
 32 /delete-node/ &wlan_msa_mem;
 33 
 34 / {
 35         model = "Xiaomi Mi 6";
 36         compatible = "xiaomi,sagit", "qcom,msm8998";
 37         chassis-type = "handset";
 38         /* Required for bootloader to select correct board */
 39         qcom,board-id = <30 0>;
 40 
 41         reserved-memory {
 42                 /*
 43                  * Xiaomi's ADSP firmware requires 30 MiB in total, so increase the adsp_mem
 44                  * region by 4 MiB to account for this while relocating the other now
 45                  * conflicting memory nodes accordingly.
 46                  */
 47                 adsp_mem: memory@8b200000 {
 48                         reg = <0x0 0x8b200000 0x0 0x1e00000>;
 49                         no-map;
 50                 };
 51 
 52                 mpss_mem: memory@8d000000 {
 53                         reg = <0x0 0x8d000000 0x0 0x7000000>;
 54                         no-map;
 55                 };
 56 
 57                 venus_mem: memory@94000000 {
 58                         reg = <0x0 0x94000000 0x0 0x500000>;
 59                         no-map;
 60                 };
 61 
 62                 mba_mem: memory@94500000 {
 63                         reg = <0x0 0x94500000 0x0 0x200000>;
 64                         no-map;
 65                 };
 66 
 67                 slpi_mem: memory@94700000 {
 68                         reg = <0x0 0x94700000 0x0 0xf00000>;
 69                         no-map;
 70                 };
 71 
 72                 ipa_fw_mem: memory@95600000 {
 73                         reg = <0x0 0x95600000 0x0 0x10000>;
 74                         no-map;
 75                 };
 76 
 77                 ipa_gsi_mem: memory@95610000 {
 78                         reg = <0x0 0x95610000 0x0 0x5000>;
 79                         no-map;
 80                 };
 81 
 82                 gpu_mem: memory@95615000 {
 83                         reg = <0x0 0x95615000 0x0 0x100000>;
 84                         no-map;
 85                 };
 86 
 87                 wlan_msa_mem: memory@95715000 {
 88                         reg = <0x0 0x95715000 0x0 0x100000>;
 89                         no-map;
 90                 };
 91 
 92                 /* Bootloader display framebuffer region */
 93                 cont_splash_mem: memory@9d400000 {
 94                         reg = <0x0 0x9d400000 0x0 0x2400000>;
 95                         no-map;
 96                 };
 97 
 98                 /* For getting crash logs using Android downstream kernels */
 99                 ramoops@ac000000 {
100                         compatible = "ramoops";
101                         reg = <0x0 0xac000000 0x0 0x200000>;
102                         console-size = <0x80000>;
103                         pmsg-size = <0x40000>;
104                         record-size = <0x8000>;
105                         ftrace-size = <0x20000>;
106                 };
107 
108                 /*
109                  * The following memory regions on downstream are "dynamically allocated"
110                  * but given the same addresses every time. Hard code them as these addresses
111                  * are where the Xiaomi signed firmware expects them to be.
112                  */
113                 ipa_fws_region: memory@f7800000 {
114                         compatible = "shared-dma-pool";
115                         reg = <0x0 0xf7800000 0x0 0x5000>;
116                         no-map;
117                 };
118 
119                 zap_shader_region: memory@f7900000 {
120                         compatible = "shared-dma-pool";
121                         reg = <0x0 0xf7900000 0x0 0x2000>;
122                         no-map;
123                 };
124         };
125 
126         gpio-keys {
127                 compatible = "gpio-keys";
128                 label = "Volume buttons";
129                 autorepeat;
130 
131                 pinctrl-names = "default";
132                 pinctrl-0 = <&vol_up_key_default>;
133 
134                 key-vol-up {
135                         label = "Volume up";
136                         gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
137                         linux,code = <KEY_VOLUMEUP>;
138                         debounce-interval = <15>;
139                         wakeup-source;
140                 };
141         };
142 
143         gpio-hall-sensor {
144                 compatible = "gpio-keys";
145                 label = "Hall effect sensor";
146 
147                 pinctrl-names = "default";
148                 pinctrl-0 = <&hall_sensor_default_state>;
149 
150                 event-hall-sensor {
151                         label = "Hall Effect Sensor";
152                         gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
153                         linux,input-type = <EV_SW>;
154                         linux,code = <SW_LID>;
155                         linux,can-disable;
156                         wakeup-source;
157                 };
158         };
159 
160         vph_pwr: vph-pwr-regulator {
161                 compatible = "regulator-fixed";
162                 regulator-name = "vph_pwr";
163                 regulator-min-microvolt = <3700000>;
164                 regulator-max-microvolt = <3700000>;
165                 regulator-always-on;
166                 regulator-boot-on;
167         };
168 
169         disp_vddts_vreg: disp-vddts-regulator {
170                 compatible = "regulator-fixed";
171                 regulator-name = "disp-vddts-regulator";
172                 gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>;
173                 enable-active-high;
174                 regulator-boot-on;
175         };
176 };
177 
178 &blsp1_i2c5 {
179         pinctrl-names = "default", "sleep";
180         status = "okay";
181 
182         touchscreen@20 {
183                 compatible = "syna,rmi4-i2c";
184                 reg = <0x20>;
185                 #address-cells = <1>;
186                 #size-cells = <0>;
187 
188                 interrupt-parent = <&tlmm>;
189                 interrupts = <125 IRQ_TYPE_EDGE_FALLING>;
190 
191                 pinctrl-names = "default", "sleep";
192                 pinctrl-0 = <&ts_active_state>;
193                 pinctrl-1 = <&ts_int_suspend_state &ts_reset_suspend_state>;
194 
195                 vdd-supply = <&disp_vddts_vreg>;
196                 vio-supply = <&vreg_l6a_1p8>;
197 
198                 syna,reset-delay-ms = <20>;
199                 syna,startup-delay-ms = <20>;
200 
201                 rmi4-f01@1 {
202                         reg = <0x01>;
203                         syna,nosleep-mode = <1>;
204                 };
205 
206                 rmi4-f12@12 {
207                         reg = <0x12>;
208                         touchscreen-x-mm = <64>;
209                         touchscreen-y-mm = <114>;
210                         syna,sensor-type = <1>;
211                         syna,rezero-wait-ms = <20>;
212                 };
213 
214                 rmi4-f1a@1a {
215                         reg = <0x1a>;
216                 };
217         };
218 };
219 
220 &blsp1_i2c5_sleep {
221         /delete-property/ bias-pull-up;
222         bias-disable;
223 };
224 
225 &blsp1_uart3 {
226         status = "okay";
227 
228         bluetooth {
229                 compatible = "qcom,wcn3990-bt";
230 
231                 vddio-supply = <&vreg_s4a_1p8>;
232                 vddxo-supply = <&vreg_l7a_1p8>;
233                 vddrf-supply = <&vreg_l17a_1p3>;
234                 vddch0-supply = <&vreg_l25a_3p3>;
235                 max-speed = <3200000>;
236         };
237 };
238 
239 &blsp1_uart3_on {
240         rx-pins {
241                 /delete-property/ bias-disable;
242                 /*
243                  * Configure a pull-up on 46 (RX). This is needed to
244                  * avoid garbage data when the TX pin of the Bluetooth
245                  * module is in tri-state (module powered off or not
246                  * driving the signal yet).
247                  */
248                 bias-pull-up;
249         };
250 
251         cts-pins {
252                 /delete-property/ bias-disable;
253                 /*
254                  * Configure a pull-down on 47 (CTS) to match the pull
255                  * of the Bluetooth module.
256                  */
257                 bias-pull-down;
258         };
259 };
260 
261 &blsp2_uart1 {
262         status = "okay";
263 };
264 
265 &pm8005_regulators {
266         compatible = "qcom,pm8005-regulators";
267 
268         vdd_s1-supply = <&vph_pwr>;
269 
270         pm8005_s1: s1 { /* VDD_GFX supply */
271                 regulator-min-microvolt = <524000>;
272                 regulator-max-microvolt = <1100000>;
273                 regulator-enable-ramp-delay = <500>;
274 
275                 /* hack until we rig up the gpu consumer */
276                 regulator-always-on;
277         };
278 };
279 
280 &pm8998_gpios {
281         vol_up_key_default: vol-up-key-default-state {
282                 pins = "gpio6";
283                 function = "normal";
284                 bias-pull-up;
285                 input-enable;
286                 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
287         };
288 
289         audio_mclk_pin: audio-mclk-pin-active-state {
290                 pins = "gpio13";
291                 function = "func2";
292                 power-source = <0>;
293         };
294 };
295 
296 &qusb2phy {
297         vdd-supply = <&vreg_l1a_0p875>;
298         vdda-pll-supply = <&vreg_l12a_1p8>;
299         vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
300         status = "okay";
301 };
302 
303 &rpm_requests {
304         regulators-0 {
305                 compatible = "qcom,rpm-pm8998-regulators";
306 
307                 vdd_s1-supply = <&vph_pwr>;
308                 vdd_s2-supply = <&vph_pwr>;
309                 vdd_s3-supply = <&vph_pwr>;
310                 vdd_s4-supply = <&vph_pwr>;
311                 vdd_s5-supply = <&vph_pwr>;
312                 vdd_s6-supply = <&vph_pwr>;
313                 vdd_s7-supply = <&vph_pwr>;
314                 vdd_s8-supply = <&vph_pwr>;
315                 vdd_s9-supply = <&vph_pwr>;
316                 vdd_s10-supply = <&vph_pwr>;
317                 vdd_s11-supply = <&vph_pwr>;
318                 vdd_s12-supply = <&vph_pwr>;
319                 vdd_s13-supply = <&vph_pwr>;
320                 vdd_l1_l27-supply = <&vreg_s7a_1p025>;
321                 vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
322                 vdd_l3_l11-supply = <&vreg_s7a_1p025>;
323                 vdd_l4_l5-supply = <&vreg_s7a_1p025>;
324                 vdd_l6-supply = <&vreg_s5a_2p04>;
325                 vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
326                 vdd_l9-supply = <&vreg_bob>;
327                 vdd_l10_l23_l25-supply = <&vreg_bob>;
328                 vdd_l13_l19_l21-supply = <&vreg_bob>;
329                 vdd_l16_l28-supply = <&vreg_bob>;
330                 vdd_l18_l22-supply = <&vreg_bob>;
331                 vdd_l20_l24-supply = <&vreg_bob>;
332                 vdd_l26-supply = <&vreg_s3a_1p35>;
333                 vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
334 
335                 vreg_s3a_1p35: s3 {
336                         regulator-min-microvolt = <1352000>;
337                         regulator-max-microvolt = <1352000>;
338                 };
339 
340                 vreg_s4a_1p8: s4 {
341                         regulator-min-microvolt = <1800000>;
342                         regulator-max-microvolt = <1800000>;
343                         regulator-allow-set-load;
344                 };
345 
346                 vreg_s5a_2p04: s5 {
347                         regulator-min-microvolt = <1904000>;
348                         regulator-max-microvolt = <2040000>;
349                 };
350 
351                 vreg_s7a_1p025: s7 {
352                         regulator-min-microvolt = <900000>;
353                         regulator-max-microvolt = <1028000>;
354                 };
355 
356                 vreg_l1a_0p875: l1 {
357                         regulator-min-microvolt = <880000>;
358                         regulator-max-microvolt = <880000>;
359                 };
360 
361                 vreg_l2a_1p2: l2 {
362                         regulator-min-microvolt = <1200000>;
363                         regulator-max-microvolt = <1200000>;
364                 };
365 
366                 vreg_l3a_1p0: l3 {
367                         regulator-min-microvolt = <1000000>;
368                         regulator-max-microvolt = <1000000>;
369                 };
370 
371                 vreg_l5a_0p8: l5 {
372                         regulator-min-microvolt = <800000>;
373                         regulator-max-microvolt = <800000>;
374                 };
375 
376                 vreg_l6a_1p8: l6 {
377                         regulator-min-microvolt = <1800000>;
378                         regulator-max-microvolt = <1800000>;
379                 };
380 
381                 vreg_l7a_1p8: l7 {
382                         regulator-min-microvolt = <1800000>;
383                         regulator-max-microvolt = <1800000>;
384                 };
385 
386                 vreg_l8a_1p2: l8 {
387                         regulator-min-microvolt = <1200000>;
388                         regulator-max-microvolt = <1200000>;
389                 };
390 
391                 vreg_l9a_1p8: l9 {
392                         regulator-min-microvolt = <1808000>;
393                         regulator-max-microvolt = <2960000>;
394                 };
395 
396                 vreg_l10a_1p8: l10 {
397                         regulator-min-microvolt = <1808000>;
398                         regulator-max-microvolt = <2960000>;
399                 };
400 
401                 vreg_l11a_1p0: l11 {
402                         regulator-min-microvolt = <1000000>;
403                         regulator-max-microvolt = <1000000>;
404                 };
405 
406                 vreg_l12a_1p8: l12 {
407                         regulator-min-microvolt = <1800000>;
408                         regulator-max-microvolt = <1800000>;
409                 };
410 
411                 vreg_l13a_2p95: l13 {
412                         regulator-min-microvolt = <1808000>;
413                         regulator-max-microvolt = <2960000>;
414                 };
415 
416                 vreg_l14a_1p8: l14 {
417                         regulator-min-microvolt = <1800000>;
418                         regulator-max-microvolt = <1800000>;
419                 };
420 
421                 vreg_l15a_1p8: l15 {
422                         regulator-min-microvolt = <1800000>;
423                         regulator-max-microvolt = <1800000>;
424                 };
425 
426                 vreg_l16a_2p7: l16 {
427                         regulator-min-microvolt = <2704000>;
428                         regulator-max-microvolt = <2704000>;
429                 };
430 
431                 vreg_l17a_1p3: l17 {
432                         regulator-min-microvolt = <1304000>;
433                         regulator-max-microvolt = <1304000>;
434                 };
435 
436                 vreg_l18a_2p7: l18 {
437                         regulator-min-microvolt = <2704000>;
438                         regulator-max-microvolt = <2704000>;
439                 };
440 
441                 vreg_l19a_3p0: l19 {
442                         regulator-min-microvolt = <3008000>;
443                         regulator-max-microvolt = <3008000>;
444                 };
445 
446                 vreg_l20a_2p95: l20 {
447                         regulator-min-microvolt = <2960000>;
448                         regulator-max-microvolt = <2960000>;
449                         regulator-allow-set-load;
450                 };
451 
452                 vreg_l21a_2p95: l21 {
453                         regulator-min-microvolt = <2960000>;
454                         regulator-max-microvolt = <2960000>;
455                         regulator-system-load = <800000>;
456                         regulator-allow-set-load;
457                 };
458 
459                 vreg_l22a_2p85: l22 {
460                         regulator-min-microvolt = <2864000>;
461                         regulator-max-microvolt = <2864000>;
462                 };
463 
464                 vreg_l23a_3p3: l23 {
465                         regulator-min-microvolt = <3312000>;
466                         regulator-max-microvolt = <3312000>;
467                 };
468 
469                 vreg_l24a_3p075: l24 {
470                         regulator-min-microvolt = <3088000>;
471                         regulator-max-microvolt = <3088000>;
472                 };
473 
474                 vreg_l25a_3p3: l25 {
475                         regulator-min-microvolt = <3104000>;
476                         regulator-max-microvolt = <3312000>;
477                 };
478 
479                 vreg_l26a_1p2: l26 {
480                         regulator-min-microvolt = <1200000>;
481                         regulator-max-microvolt = <1200000>;
482                         regulator-allow-set-load;
483                 };
484 
485                 vreg_l28_3p0: l28 {
486                         regulator-min-microvolt = <3008000>;
487                         regulator-max-microvolt = <3008000>;
488                 };
489 
490                 vreg_lvs1a_1p8: lvs1 { };
491 
492                 vreg_lvs2a_1p8: lvs2 { };
493         };
494 
495         regulators-1 {
496                 compatible = "qcom,rpm-pmi8998-regulators";
497 
498                 vdd_bob-supply = <&vph_pwr>;
499 
500                 vreg_bob: bob {
501                         regulator-min-microvolt = <3312000>;
502                         regulator-max-microvolt = <3600000>;
503                 };
504         };
505 };
506 
507 &tlmm {
508         gpio-reserved-ranges = <0 4>, <81 4>;
509 
510         cci1_default_state: cci1-default-state {
511                 pins = "gpio19", "gpio20";
512                 function = "cci_i2c";
513                 bias-disable;
514                 drive-strength = <2>;
515         };
516 
517         cdc_reset_n_state: cdc-reset-n-state {
518                 pins = "gpio64";
519                 function = "gpio";
520                 bias-pull-down;
521                 drive-strength = <16>;
522                 output-high;
523         };
524 
525         hall_sensor_default_state: hall-sensor-default-state {
526                 pins = "gpio124";
527                 function = "gpio";
528                 drive-strength = <2>;
529                 bias-disable;
530         };
531 
532         mdss_dsi_active_state: mdss-dsi-active-state {
533                 pins = "gpio94";
534                 function = "gpio";
535                 drive-strength = <8>;
536                 bias-disable;
537         };
538 
539         mdss_dsi_suspend_state: mdss-dsi-suspend-state {
540                 pins = "gpio94";
541                 function = "gpio";
542                 drive-strength = <2>;
543                 bias-pull-down;
544         };
545 
546         mdss_te_active_state: mdss-te-active-state {
547                 pins = "gpio10";
548                 function = "mdp_vsync_a";
549                 drive-strength = <2>;
550                 bias-pull-down;
551         };
552 
553         mdss_te_suspend_state: mdss-te-suspend-state {
554                 pins = "gpio10";
555                 function = "mdp_vsync_a";
556                 drive-strength = <2>;
557                 bias-pull-down;
558         };
559 
560         msm_mclk0_active_state: msm-mclk0-active-state {
561                 pins = "gpio13";
562                 function = "cam_mclk";
563                 drive-strength = <2>;
564                 bias-disable;
565         };
566 
567         msm_mclk0_suspend_state: msm-mclk0-suspend-state {
568                 pins = "gpio13";
569                 function = "cam_mclk";
570                 drive-strength = <2>;
571                 bias-pull-down;
572         };
573 
574         msm_mclk1_active_state: msm-mclk1-active-state {
575                 pins = "gpio14";
576                 function = "cam_mclk";
577                 drive-strength = <2>;
578                 bias-disable;
579         };
580 
581         msm_mclk1_suspend_state: msm-mclk1-suspend-state {
582                 pins = "gpio14";
583                 function = "cam_mclk";
584                 drive-strength = <2>;
585                 bias-pull-down;
586         };
587 
588         nfc_int_active_state: nfc-int-active-state {
589                 pins = "gpio92";
590                 function = "gpio";
591                 drive-strength = <6>;
592                 bias-pull-up;
593         };
594 
595         nfc_int_suspend_state: nfc-int-suspend-state {
596                 pins = "gpio92";
597                 function = "gpio";
598                 drive-strength = <6>;
599                 bias-pull-up;
600         };
601 
602         nfc_enable_active_state: nfc-enable-active-state {
603                 pins = "gpio12", "gpio116";
604                 function = "gpio";
605                 drive-strength = <6>;
606                 bias-pull-up;
607         };
608 
609         nfc_enable_suspend_state: nfc-enable-suspend-state {
610                 pins = "gpio12", "gpio116";
611                 function = "gpio";
612                 drive-strength = <6>;
613                 bias-disable;
614         };
615 
616         ts_active_state: ts-active-state {
617                 pins = "gpio89", "gpio125";
618                 function = "gpio";
619                 drive-strength = <16>;
620                 bias-pull-up;
621         };
622 
623         ts_int_suspend_state: ts-int-suspend-state {
624                 pins = "gpio125";
625                 function = "gpio";
626                 drive-strength = <2>;
627                 bias-disable;
628         };
629 
630         ts_reset_suspend_state: ts-reset-suspend-state {
631                 pins = "gpio89";
632                 function = "gpio";
633                 drive-strength = <2>;
634                 bias-disable;
635         };
636 
637         wcd_int_n_state: wcd-int-n-state {
638                 pins = "gpio54";
639                 function = "gpio";
640                 bias-pull-down;
641                 drive-strength = <2>;
642         };
643 
644         wsa_leftspk_pwr_n_state: wsa-leftspk-pwr-n-state {
645                 pins = "gpio65";
646                 function = "gpio";
647                 bias-disable;
648                 drive-strength = <2>;
649                 output-low;
650         };
651 
652         wsa_rightspk_pwr_n_state: wsa-rightspk-pwr-n-state {
653                 pins = "gpio66";
654                 function = "gpio";
655                 bias-disable;
656                 drive-strength = <2>;
657                 output-low;
658         };
659 };
660 
661 &pm8998_resin {
662         linux,code = <KEY_VOLUMEDOWN>;
663         status = "okay";
664 };
665 
666 &ufshc {
667         vcc-supply = <&vreg_l20a_2p95>;
668         vccq-supply = <&vreg_l26a_1p2>;
669         vccq2-supply = <&vreg_s4a_1p8>;
670         vdd-hba-supply = <&vreg_l26a_1p2>;
671         vcc-max-microamp = <750000>;
672         vccq-max-microamp = <560000>;
673         vccq2-max-microamp = <750000>;
674         status = "okay";
675 };
676 
677 &ufsphy {
678         vdda-phy-supply = <&vreg_l1a_0p875>;
679         vdda-pll-supply = <&vreg_l2a_1p2>;
680         status = "okay";
681 };
682 
683 &usb3 {
684         /* Disable USB3 clock requirement as the device only supports USB2 */
685         qcom,select-utmi-as-pipe-clk;
686         status = "okay";
687 };
688 
689 &usb3_dwc3 {
690         /* Drop the unused USB 3 PHY */
691         phys = <&qusb2phy>;
692         phy-names = "usb2-phy";
693 
694         /* Fastest mode for USB 2 */
695         maximum-speed = "high-speed";
696 
697         /* Force to peripheral until we can switch modes */
698         dr_mode = "peripheral";
699 };
700 
701 &wifi {
702         vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
703         vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
704         vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
705         vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
706         status = "okay";
707 };

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