1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SC7180 SoC device tree source
4 *
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
6 */
7
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/interconnect/qcom,icc.h>
16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
17 #include <dt-bindings/interconnect/qcom,sc7180.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/sound/qcom,q6afe.h>
27 #include <dt-bindings/thermal/thermal.h>
28
29 / {
30 interrupt-parent = <&intc>;
31
32 #address-cells = <2>;
33 #size-cells = <2>;
34
35 aliases {
36 mmc1 = &sdhc_1;
37 mmc2 = &sdhc_2;
38 i2c0 = &i2c0;
39 i2c1 = &i2c1;
40 i2c2 = &i2c2;
41 i2c3 = &i2c3;
42 i2c4 = &i2c4;
43 i2c5 = &i2c5;
44 i2c6 = &i2c6;
45 i2c7 = &i2c7;
46 i2c8 = &i2c8;
47 i2c9 = &i2c9;
48 i2c10 = &i2c10;
49 i2c11 = &i2c11;
50 spi0 = &spi0;
51 spi1 = &spi1;
52 spi3 = &spi3;
53 spi5 = &spi5;
54 spi6 = &spi6;
55 spi8 = &spi8;
56 spi10 = &spi10;
57 spi11 = &spi11;
58 };
59
60 chosen { };
61
62 clocks {
63 xo_board: xo-board {
64 compatible = "fixed-clock";
65 clock-frequency = <38400000>;
66 #clock-cells = <0>;
67 };
68
69 sleep_clk: sleep-clk {
70 compatible = "fixed-clock";
71 clock-frequency = <32764>;
72 #clock-cells = <0>;
73 };
74 };
75
76 cpus {
77 #address-cells = <2>;
78 #size-cells = <0>;
79
80 CPU0: cpu@0 {
81 device_type = "cpu";
82 compatible = "qcom,kryo468";
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci";
86 power-domains = <&CPU_PD0>;
87 power-domain-names = "psci";
88 capacity-dmips-mhz = <415>;
89 dynamic-power-coefficient = <137>;
90 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
92 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 next-level-cache = <&L2_0>;
94 #cooling-cells = <2>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 L2_0: l2-cache {
97 compatible = "cache";
98 cache-level = <2>;
99 cache-unified;
100 next-level-cache = <&L3_0>;
101 L3_0: l3-cache {
102 compatible = "cache";
103 cache-level = <3>;
104 cache-unified;
105 };
106 };
107 };
108
109 CPU1: cpu@100 {
110 device_type = "cpu";
111 compatible = "qcom,kryo468";
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci";
115 power-domains = <&CPU_PD1>;
116 power-domain-names = "psci";
117 capacity-dmips-mhz = <415>;
118 dynamic-power-coefficient = <137>;
119 next-level-cache = <&L2_100>;
120 operating-points-v2 = <&cpu0_opp_table>;
121 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
122 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
123 #cooling-cells = <2>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 L2_100: l2-cache {
126 compatible = "cache";
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&L3_0>;
130 };
131 };
132
133 CPU2: cpu@200 {
134 device_type = "cpu";
135 compatible = "qcom,kryo468";
136 reg = <0x0 0x200>;
137 clocks = <&cpufreq_hw 0>;
138 enable-method = "psci";
139 power-domains = <&CPU_PD2>;
140 power-domain-names = "psci";
141 capacity-dmips-mhz = <415>;
142 dynamic-power-coefficient = <137>;
143 next-level-cache = <&L2_200>;
144 operating-points-v2 = <&cpu0_opp_table>;
145 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
146 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
147 #cooling-cells = <2>;
148 qcom,freq-domain = <&cpufreq_hw 0>;
149 L2_200: l2-cache {
150 compatible = "cache";
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&L3_0>;
154 };
155 };
156
157 CPU3: cpu@300 {
158 device_type = "cpu";
159 compatible = "qcom,kryo468";
160 reg = <0x0 0x300>;
161 clocks = <&cpufreq_hw 0>;
162 enable-method = "psci";
163 power-domains = <&CPU_PD3>;
164 power-domain-names = "psci";
165 capacity-dmips-mhz = <415>;
166 dynamic-power-coefficient = <137>;
167 next-level-cache = <&L2_300>;
168 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
173 L2_300: l2-cache {
174 compatible = "cache";
175 cache-level = <2>;
176 cache-unified;
177 next-level-cache = <&L3_0>;
178 };
179 };
180
181 CPU4: cpu@400 {
182 device_type = "cpu";
183 compatible = "qcom,kryo468";
184 reg = <0x0 0x400>;
185 clocks = <&cpufreq_hw 0>;
186 enable-method = "psci";
187 power-domains = <&CPU_PD4>;
188 power-domain-names = "psci";
189 capacity-dmips-mhz = <415>;
190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L2_400>;
192 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
197 L2_400: l2-cache {
198 compatible = "cache";
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&L3_0>;
202 };
203 };
204
205 CPU5: cpu@500 {
206 device_type = "cpu";
207 compatible = "qcom,kryo468";
208 reg = <0x0 0x500>;
209 clocks = <&cpufreq_hw 0>;
210 enable-method = "psci";
211 power-domains = <&CPU_PD5>;
212 power-domain-names = "psci";
213 capacity-dmips-mhz = <415>;
214 dynamic-power-coefficient = <137>;
215 next-level-cache = <&L2_500>;
216 operating-points-v2 = <&cpu0_opp_table>;
217 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
218 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 L2_500: l2-cache {
222 compatible = "cache";
223 cache-level = <2>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
226 };
227 };
228
229 CPU6: cpu@600 {
230 device_type = "cpu";
231 compatible = "qcom,kryo468";
232 reg = <0x0 0x600>;
233 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci";
235 power-domains = <&CPU_PD6>;
236 power-domain-names = "psci";
237 capacity-dmips-mhz = <1024>;
238 dynamic-power-coefficient = <480>;
239 next-level-cache = <&L2_600>;
240 operating-points-v2 = <&cpu6_opp_table>;
241 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
242 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
243 #cooling-cells = <2>;
244 qcom,freq-domain = <&cpufreq_hw 1>;
245 L2_600: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
250 };
251 };
252
253 CPU7: cpu@700 {
254 device_type = "cpu";
255 compatible = "qcom,kryo468";
256 reg = <0x0 0x700>;
257 clocks = <&cpufreq_hw 1>;
258 enable-method = "psci";
259 power-domains = <&CPU_PD7>;
260 power-domain-names = "psci";
261 capacity-dmips-mhz = <1024>;
262 dynamic-power-coefficient = <480>;
263 next-level-cache = <&L2_700>;
264 operating-points-v2 = <&cpu6_opp_table>;
265 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
266 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>;
268 qcom,freq-domain = <&cpufreq_hw 1>;
269 L2_700: l2-cache {
270 compatible = "cache";
271 cache-level = <2>;
272 cache-unified;
273 next-level-cache = <&L3_0>;
274 };
275 };
276
277 cpu-map {
278 cluster0 {
279 core0 {
280 cpu = <&CPU0>;
281 };
282
283 core1 {
284 cpu = <&CPU1>;
285 };
286
287 core2 {
288 cpu = <&CPU2>;
289 };
290
291 core3 {
292 cpu = <&CPU3>;
293 };
294
295 core4 {
296 cpu = <&CPU4>;
297 };
298
299 core5 {
300 cpu = <&CPU5>;
301 };
302
303 core6 {
304 cpu = <&CPU6>;
305 };
306
307 core7 {
308 cpu = <&CPU7>;
309 };
310 };
311 };
312
313 idle_states: idle-states {
314 entry-method = "psci";
315
316 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
317 compatible = "arm,idle-state";
318 idle-state-name = "little-power-down";
319 arm,psci-suspend-param = <0x40000003>;
320 entry-latency-us = <549>;
321 exit-latency-us = <901>;
322 min-residency-us = <1774>;
323 local-timer-stop;
324 };
325
326 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
327 compatible = "arm,idle-state";
328 idle-state-name = "little-rail-power-down";
329 arm,psci-suspend-param = <0x40000004>;
330 entry-latency-us = <702>;
331 exit-latency-us = <915>;
332 min-residency-us = <4001>;
333 local-timer-stop;
334 };
335
336 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
337 compatible = "arm,idle-state";
338 idle-state-name = "big-power-down";
339 arm,psci-suspend-param = <0x40000003>;
340 entry-latency-us = <523>;
341 exit-latency-us = <1244>;
342 min-residency-us = <2207>;
343 local-timer-stop;
344 };
345
346 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
347 compatible = "arm,idle-state";
348 idle-state-name = "big-rail-power-down";
349 arm,psci-suspend-param = <0x40000004>;
350 entry-latency-us = <526>;
351 exit-latency-us = <1854>;
352 min-residency-us = <5555>;
353 local-timer-stop;
354 };
355 };
356
357 domain_idle_states: domain-idle-states {
358 CLUSTER_SLEEP_PC: cluster-sleep-0 {
359 compatible = "domain-idle-state";
360 idle-state-name = "cluster-l3-power-collapse";
361 arm,psci-suspend-param = <0x41000044>;
362 entry-latency-us = <2752>;
363 exit-latency-us = <3048>;
364 min-residency-us = <6118>;
365 };
366
367 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
368 compatible = "domain-idle-state";
369 idle-state-name = "cluster-cx-retention";
370 arm,psci-suspend-param = <0x41001244>;
371 entry-latency-us = <3638>;
372 exit-latency-us = <4562>;
373 min-residency-us = <8467>;
374 };
375
376 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
377 compatible = "domain-idle-state";
378 idle-state-name = "cluster-power-down";
379 arm,psci-suspend-param = <0x4100b244>;
380 entry-latency-us = <3263>;
381 exit-latency-us = <6562>;
382 min-residency-us = <9826>;
383 };
384 };
385 };
386
387 firmware {
388 scm: scm {
389 compatible = "qcom,scm-sc7180", "qcom,scm";
390 };
391 };
392
393 memory@80000000 {
394 device_type = "memory";
395 /* We expect the bootloader to fill in the size */
396 reg = <0 0x80000000 0 0>;
397 };
398
399 cpu0_opp_table: opp-table-cpu0 {
400 compatible = "operating-points-v2";
401 opp-shared;
402
403 cpu0_opp1: opp-300000000 {
404 opp-hz = /bits/ 64 <300000000>;
405 opp-peak-kBps = <1200000 4800000>;
406 };
407
408 cpu0_opp2: opp-576000000 {
409 opp-hz = /bits/ 64 <576000000>;
410 opp-peak-kBps = <1200000 4800000>;
411 };
412
413 cpu0_opp3: opp-768000000 {
414 opp-hz = /bits/ 64 <768000000>;
415 opp-peak-kBps = <1200000 4800000>;
416 };
417
418 cpu0_opp4: opp-1017600000 {
419 opp-hz = /bits/ 64 <1017600000>;
420 opp-peak-kBps = <1804000 8908800>;
421 };
422
423 cpu0_opp5: opp-1248000000 {
424 opp-hz = /bits/ 64 <1248000000>;
425 opp-peak-kBps = <2188000 12902400>;
426 };
427
428 cpu0_opp6: opp-1324800000 {
429 opp-hz = /bits/ 64 <1324800000>;
430 opp-peak-kBps = <2188000 12902400>;
431 };
432
433 cpu0_opp7: opp-1516800000 {
434 opp-hz = /bits/ 64 <1516800000>;
435 opp-peak-kBps = <3072000 15052800>;
436 };
437
438 cpu0_opp8: opp-1612800000 {
439 opp-hz = /bits/ 64 <1612800000>;
440 opp-peak-kBps = <3072000 15052800>;
441 };
442
443 cpu0_opp9: opp-1708800000 {
444 opp-hz = /bits/ 64 <1708800000>;
445 opp-peak-kBps = <3072000 15052800>;
446 };
447
448 cpu0_opp10: opp-1804800000 {
449 opp-hz = /bits/ 64 <1804800000>;
450 opp-peak-kBps = <4068000 22425600>;
451 };
452 };
453
454 cpu6_opp_table: opp-table-cpu6 {
455 compatible = "operating-points-v2";
456 opp-shared;
457
458 cpu6_opp1: opp-300000000 {
459 opp-hz = /bits/ 64 <300000000>;
460 opp-peak-kBps = <2188000 8908800>;
461 };
462
463 cpu6_opp2: opp-652800000 {
464 opp-hz = /bits/ 64 <652800000>;
465 opp-peak-kBps = <2188000 8908800>;
466 };
467
468 cpu6_opp3: opp-825600000 {
469 opp-hz = /bits/ 64 <825600000>;
470 opp-peak-kBps = <2188000 8908800>;
471 };
472
473 cpu6_opp4: opp-979200000 {
474 opp-hz = /bits/ 64 <979200000>;
475 opp-peak-kBps = <2188000 8908800>;
476 };
477
478 cpu6_opp5: opp-1113600000 {
479 opp-hz = /bits/ 64 <1113600000>;
480 opp-peak-kBps = <2188000 8908800>;
481 };
482
483 cpu6_opp6: opp-1267200000 {
484 opp-hz = /bits/ 64 <1267200000>;
485 opp-peak-kBps = <4068000 12902400>;
486 };
487
488 cpu6_opp7: opp-1555200000 {
489 opp-hz = /bits/ 64 <1555200000>;
490 opp-peak-kBps = <4068000 15052800>;
491 };
492
493 cpu6_opp8: opp-1708800000 {
494 opp-hz = /bits/ 64 <1708800000>;
495 opp-peak-kBps = <6220000 19353600>;
496 };
497
498 cpu6_opp9: opp-1843200000 {
499 opp-hz = /bits/ 64 <1843200000>;
500 opp-peak-kBps = <6220000 19353600>;
501 };
502
503 cpu6_opp10: opp-1900800000 {
504 opp-hz = /bits/ 64 <1900800000>;
505 opp-peak-kBps = <6220000 22425600>;
506 };
507
508 cpu6_opp11: opp-1996800000 {
509 opp-hz = /bits/ 64 <1996800000>;
510 opp-peak-kBps = <6220000 22425600>;
511 };
512
513 cpu6_opp12: opp-2112000000 {
514 opp-hz = /bits/ 64 <2112000000>;
515 opp-peak-kBps = <6220000 22425600>;
516 };
517
518 cpu6_opp13: opp-2208000000 {
519 opp-hz = /bits/ 64 <2208000000>;
520 opp-peak-kBps = <7216000 22425600>;
521 };
522
523 cpu6_opp14: opp-2323200000 {
524 opp-hz = /bits/ 64 <2323200000>;
525 opp-peak-kBps = <7216000 22425600>;
526 };
527
528 cpu6_opp15: opp-2400000000 {
529 opp-hz = /bits/ 64 <2400000000>;
530 opp-peak-kBps = <8532000 23347200>;
531 };
532
533 cpu6_opp16: opp-2553600000 {
534 opp-hz = /bits/ 64 <2553600000>;
535 opp-peak-kBps = <8532000 23347200>;
536 };
537 };
538
539 qspi_opp_table: opp-table-qspi {
540 compatible = "operating-points-v2";
541
542 opp-75000000 {
543 opp-hz = /bits/ 64 <75000000>;
544 required-opps = <&rpmhpd_opp_low_svs>;
545 };
546
547 opp-150000000 {
548 opp-hz = /bits/ 64 <150000000>;
549 required-opps = <&rpmhpd_opp_svs>;
550 };
551
552 opp-300000000 {
553 opp-hz = /bits/ 64 <300000000>;
554 required-opps = <&rpmhpd_opp_nom>;
555 };
556 };
557
558 qup_opp_table: opp-table-qup {
559 compatible = "operating-points-v2";
560
561 opp-75000000 {
562 opp-hz = /bits/ 64 <75000000>;
563 required-opps = <&rpmhpd_opp_low_svs>;
564 };
565
566 opp-100000000 {
567 opp-hz = /bits/ 64 <100000000>;
568 required-opps = <&rpmhpd_opp_svs>;
569 };
570
571 opp-128000000 {
572 opp-hz = /bits/ 64 <128000000>;
573 required-opps = <&rpmhpd_opp_nom>;
574 };
575 };
576
577 pmu {
578 compatible = "arm,armv8-pmuv3";
579 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
580 };
581
582 psci {
583 compatible = "arm,psci-1.0";
584 method = "smc";
585
586 CPU_PD0: cpu0 {
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
590 };
591
592 CPU_PD1: cpu1 {
593 #power-domain-cells = <0>;
594 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
596 };
597
598 CPU_PD2: cpu2 {
599 #power-domain-cells = <0>;
600 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
602 };
603
604 CPU_PD3: cpu3 {
605 #power-domain-cells = <0>;
606 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
608 };
609
610 CPU_PD4: cpu4 {
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
614 };
615
616 CPU_PD5: cpu5 {
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
620 };
621
622 CPU_PD6: cpu6 {
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
626 };
627
628 CPU_PD7: cpu7 {
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
632 };
633
634 CLUSTER_PD: cpu-cluster0 {
635 #power-domain-cells = <0>;
636 domain-idle-states = <&CLUSTER_SLEEP_PC
637 &CLUSTER_SLEEP_CX_RET
638 &CLUSTER_AOSS_SLEEP>;
639 };
640 };
641
642 reserved_memory: reserved-memory {
643 #address-cells = <2>;
644 #size-cells = <2>;
645 ranges;
646
647 hyp_mem: memory@80000000 {
648 reg = <0x0 0x80000000 0x0 0x600000>;
649 no-map;
650 };
651
652 xbl_mem: memory@80600000 {
653 reg = <0x0 0x80600000 0x0 0x200000>;
654 no-map;
655 };
656
657 aop_mem: memory@80800000 {
658 reg = <0x0 0x80800000 0x0 0x20000>;
659 no-map;
660 };
661
662 aop_cmd_db_mem: memory@80820000 {
663 reg = <0x0 0x80820000 0x0 0x20000>;
664 compatible = "qcom,cmd-db";
665 no-map;
666 };
667
668 sec_apps_mem: memory@808ff000 {
669 reg = <0x0 0x808ff000 0x0 0x1000>;
670 no-map;
671 };
672
673 smem_mem: memory@80900000 {
674 reg = <0x0 0x80900000 0x0 0x200000>;
675 no-map;
676 };
677
678 tz_mem: memory@80b00000 {
679 reg = <0x0 0x80b00000 0x0 0x3900000>;
680 no-map;
681 };
682
683 ipa_fw_mem: memory@8b700000 {
684 reg = <0 0x8b700000 0 0x10000>;
685 no-map;
686 };
687
688 rmtfs_mem: memory@94600000 {
689 compatible = "qcom,rmtfs-mem";
690 reg = <0x0 0x94600000 0x0 0x200000>;
691 no-map;
692
693 qcom,client-id = <1>;
694 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
695 };
696 };
697
698 smem {
699 compatible = "qcom,smem";
700 memory-region = <&smem_mem>;
701 hwlocks = <&tcsr_mutex 3>;
702 };
703
704 smp2p-cdsp {
705 compatible = "qcom,smp2p";
706 qcom,smem = <94>, <432>;
707
708 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
709
710 mboxes = <&apss_shared 6>;
711
712 qcom,local-pid = <0>;
713 qcom,remote-pid = <5>;
714
715 cdsp_smp2p_out: master-kernel {
716 qcom,entry-name = "master-kernel";
717 #qcom,smem-state-cells = <1>;
718 };
719
720 cdsp_smp2p_in: slave-kernel {
721 qcom,entry-name = "slave-kernel";
722
723 interrupt-controller;
724 #interrupt-cells = <2>;
725 };
726 };
727
728 smp2p-lpass {
729 compatible = "qcom,smp2p";
730 qcom,smem = <443>, <429>;
731
732 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
733
734 mboxes = <&apss_shared 10>;
735
736 qcom,local-pid = <0>;
737 qcom,remote-pid = <2>;
738
739 adsp_smp2p_out: master-kernel {
740 qcom,entry-name = "master-kernel";
741 #qcom,smem-state-cells = <1>;
742 };
743
744 adsp_smp2p_in: slave-kernel {
745 qcom,entry-name = "slave-kernel";
746
747 interrupt-controller;
748 #interrupt-cells = <2>;
749 };
750 };
751
752 smp2p-mpss {
753 compatible = "qcom,smp2p";
754 qcom,smem = <435>, <428>;
755 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
756 mboxes = <&apss_shared 14>;
757 qcom,local-pid = <0>;
758 qcom,remote-pid = <1>;
759
760 modem_smp2p_out: master-kernel {
761 qcom,entry-name = "master-kernel";
762 #qcom,smem-state-cells = <1>;
763 };
764
765 modem_smp2p_in: slave-kernel {
766 qcom,entry-name = "slave-kernel";
767 interrupt-controller;
768 #interrupt-cells = <2>;
769 };
770
771 ipa_smp2p_out: ipa-ap-to-modem {
772 qcom,entry-name = "ipa";
773 #qcom,smem-state-cells = <1>;
774 };
775
776 ipa_smp2p_in: ipa-modem-to-ap {
777 qcom,entry-name = "ipa";
778 interrupt-controller;
779 #interrupt-cells = <2>;
780 };
781 };
782
783 soc: soc@0 {
784 #address-cells = <2>;
785 #size-cells = <2>;
786 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>;
788 compatible = "simple-bus";
789
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-sc7180";
792 reg = <0 0x00100000 0 0x1f0000>;
793 clocks = <&rpmhcc RPMH_CXO_CLK>,
794 <&rpmhcc RPMH_CXO_CLK_A>,
795 <&sleep_clk>;
796 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
797 #clock-cells = <1>;
798 #reset-cells = <1>;
799 #power-domain-cells = <1>;
800 power-domains = <&rpmhpd SC7180_CX>;
801 };
802
803 qfprom: efuse@784000 {
804 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
805 reg = <0 0x00784000 0 0x7a0>,
806 <0 0x00780000 0 0x7a0>,
807 <0 0x00782000 0 0x100>,
808 <0 0x00786000 0 0x1fff>;
809
810 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
811 clock-names = "core";
812 #address-cells = <1>;
813 #size-cells = <1>;
814
815 qusb2p_hstx_trim: hstx-trim-primary@25b {
816 reg = <0x25b 0x1>;
817 bits = <1 3>;
818 };
819
820 gpu_speed_bin: gpu-speed-bin@1d2 {
821 reg = <0x1d2 0x2>;
822 bits = <5 8>;
823 };
824 };
825
826 sdhc_1: mmc@7c4000 {
827 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
828 reg = <0 0x007c4000 0 0x1000>,
829 <0 0x007c5000 0 0x1000>;
830 reg-names = "hc", "cqhci";
831
832 iommus = <&apps_smmu 0x60 0x0>;
833 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "hc_irq", "pwr_irq";
836
837 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
838 <&gcc GCC_SDCC1_APPS_CLK>,
839 <&rpmhcc RPMH_CXO_CLK>;
840 clock-names = "iface", "core", "xo";
841 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
842 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
843 interconnect-names = "sdhc-ddr","cpu-sdhc";
844 power-domains = <&rpmhpd SC7180_CX>;
845 operating-points-v2 = <&sdhc1_opp_table>;
846
847 bus-width = <8>;
848 non-removable;
849 supports-cqe;
850
851 mmc-ddr-1_8v;
852 mmc-hs200-1_8v;
853 mmc-hs400-1_8v;
854 mmc-hs400-enhanced-strobe;
855
856 status = "disabled";
857
858 sdhc1_opp_table: opp-table {
859 compatible = "operating-points-v2";
860
861 opp-100000000 {
862 opp-hz = /bits/ 64 <100000000>;
863 required-opps = <&rpmhpd_opp_low_svs>;
864 opp-peak-kBps = <1800000 600000>;
865 opp-avg-kBps = <100000 0>;
866 };
867
868 opp-384000000 {
869 opp-hz = /bits/ 64 <384000000>;
870 required-opps = <&rpmhpd_opp_nom>;
871 opp-peak-kBps = <5400000 1600000>;
872 opp-avg-kBps = <390000 0>;
873 };
874 };
875 };
876
877 qupv3_id_0: geniqup@8c0000 {
878 compatible = "qcom,geni-se-qup";
879 reg = <0 0x008c0000 0 0x6000>;
880 clock-names = "m-ahb", "s-ahb";
881 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
882 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
883 #address-cells = <2>;
884 #size-cells = <2>;
885 ranges;
886 iommus = <&apps_smmu 0x43 0x0>;
887 status = "disabled";
888
889 i2c0: i2c@880000 {
890 compatible = "qcom,geni-i2c";
891 reg = <0 0x00880000 0 0x4000>;
892 clock-names = "se";
893 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&qup_i2c0_default>;
896 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
897 #address-cells = <1>;
898 #size-cells = <0>;
899 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
900 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
901 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
902 interconnect-names = "qup-core", "qup-config",
903 "qup-memory";
904 power-domains = <&rpmhpd SC7180_CX>;
905 required-opps = <&rpmhpd_opp_low_svs>;
906 status = "disabled";
907 };
908
909 spi0: spi@880000 {
910 compatible = "qcom,geni-spi";
911 reg = <0 0x00880000 0 0x4000>;
912 clock-names = "se";
913 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
916 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
917 #address-cells = <1>;
918 #size-cells = <0>;
919 power-domains = <&rpmhpd SC7180_CX>;
920 operating-points-v2 = <&qup_opp_table>;
921 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
923 interconnect-names = "qup-core", "qup-config";
924 status = "disabled";
925 };
926
927 uart0: serial@880000 {
928 compatible = "qcom,geni-uart";
929 reg = <0 0x00880000 0 0x4000>;
930 clock-names = "se";
931 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
932 pinctrl-names = "default";
933 pinctrl-0 = <&qup_uart0_default>;
934 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
935 power-domains = <&rpmhpd SC7180_CX>;
936 operating-points-v2 = <&qup_opp_table>;
937 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
938 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
939 interconnect-names = "qup-core", "qup-config";
940 status = "disabled";
941 };
942
943 i2c1: i2c@884000 {
944 compatible = "qcom,geni-i2c";
945 reg = <0 0x00884000 0 0x4000>;
946 clock-names = "se";
947 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_i2c1_default>;
950 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
955 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
956 interconnect-names = "qup-core", "qup-config",
957 "qup-memory";
958 power-domains = <&rpmhpd SC7180_CX>;
959 required-opps = <&rpmhpd_opp_low_svs>;
960 status = "disabled";
961 };
962
963 spi1: spi@884000 {
964 compatible = "qcom,geni-spi";
965 reg = <0 0x00884000 0 0x4000>;
966 clock-names = "se";
967 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
970 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells = <1>;
972 #size-cells = <0>;
973 power-domains = <&rpmhpd SC7180_CX>;
974 operating-points-v2 = <&qup_opp_table>;
975 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
977 interconnect-names = "qup-core", "qup-config";
978 status = "disabled";
979 };
980
981 uart1: serial@884000 {
982 compatible = "qcom,geni-uart";
983 reg = <0 0x00884000 0 0x4000>;
984 clock-names = "se";
985 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&qup_uart1_default>;
988 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
989 power-domains = <&rpmhpd SC7180_CX>;
990 operating-points-v2 = <&qup_opp_table>;
991 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
993 interconnect-names = "qup-core", "qup-config";
994 status = "disabled";
995 };
996
997 i2c2: i2c@888000 {
998 compatible = "qcom,geni-i2c";
999 reg = <0 0x00888000 0 0x4000>;
1000 clock-names = "se";
1001 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c2_default>;
1004 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010 interconnect-names = "qup-core", "qup-config",
1011 "qup-memory";
1012 power-domains = <&rpmhpd SC7180_CX>;
1013 required-opps = <&rpmhpd_opp_low_svs>;
1014 status = "disabled";
1015 };
1016
1017 uart2: serial@888000 {
1018 compatible = "qcom,geni-uart";
1019 reg = <0 0x00888000 0 0x4000>;
1020 clock-names = "se";
1021 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_uart2_default>;
1024 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025 power-domains = <&rpmhpd SC7180_CX>;
1026 operating-points-v2 = <&qup_opp_table>;
1027 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029 interconnect-names = "qup-core", "qup-config";
1030 status = "disabled";
1031 };
1032
1033 i2c3: i2c@88c000 {
1034 compatible = "qcom,geni-i2c";
1035 reg = <0 0x0088c000 0 0x4000>;
1036 clock-names = "se";
1037 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_i2c3_default>;
1040 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046 interconnect-names = "qup-core", "qup-config",
1047 "qup-memory";
1048 power-domains = <&rpmhpd SC7180_CX>;
1049 required-opps = <&rpmhpd_opp_low_svs>;
1050 status = "disabled";
1051 };
1052
1053 spi3: spi@88c000 {
1054 compatible = "qcom,geni-spi";
1055 reg = <0 0x0088c000 0 0x4000>;
1056 clock-names = "se";
1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 power-domains = <&rpmhpd SC7180_CX>;
1064 operating-points-v2 = <&qup_opp_table>;
1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect-names = "qup-core", "qup-config";
1068 status = "disabled";
1069 };
1070
1071 uart3: serial@88c000 {
1072 compatible = "qcom,geni-uart";
1073 reg = <0 0x0088c000 0 0x4000>;
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_uart3_default>;
1078 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079 power-domains = <&rpmhpd SC7180_CX>;
1080 operating-points-v2 = <&qup_opp_table>;
1081 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083 interconnect-names = "qup-core", "qup-config";
1084 status = "disabled";
1085 };
1086
1087 i2c4: i2c@890000 {
1088 compatible = "qcom,geni-i2c";
1089 reg = <0 0x00890000 0 0x4000>;
1090 clock-names = "se";
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&qup_i2c4_default>;
1094 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100 interconnect-names = "qup-core", "qup-config",
1101 "qup-memory";
1102 power-domains = <&rpmhpd SC7180_CX>;
1103 required-opps = <&rpmhpd_opp_low_svs>;
1104 status = "disabled";
1105 };
1106
1107 uart4: serial@890000 {
1108 compatible = "qcom,geni-uart";
1109 reg = <0 0x00890000 0 0x4000>;
1110 clock-names = "se";
1111 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_uart4_default>;
1114 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains = <&rpmhpd SC7180_CX>;
1116 operating-points-v2 = <&qup_opp_table>;
1117 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect-names = "qup-core", "qup-config";
1120 status = "disabled";
1121 };
1122
1123 i2c5: i2c@894000 {
1124 compatible = "qcom,geni-i2c";
1125 reg = <0 0x00894000 0 0x4000>;
1126 clock-names = "se";
1127 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&qup_i2c5_default>;
1130 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136 interconnect-names = "qup-core", "qup-config",
1137 "qup-memory";
1138 power-domains = <&rpmhpd SC7180_CX>;
1139 required-opps = <&rpmhpd_opp_low_svs>;
1140 status = "disabled";
1141 };
1142
1143 spi5: spi@894000 {
1144 compatible = "qcom,geni-spi";
1145 reg = <0 0x00894000 0 0x4000>;
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153 power-domains = <&rpmhpd SC7180_CX>;
1154 operating-points-v2 = <&qup_opp_table>;
1155 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157 interconnect-names = "qup-core", "qup-config";
1158 status = "disabled";
1159 };
1160
1161 uart5: serial@894000 {
1162 compatible = "qcom,geni-uart";
1163 reg = <0 0x00894000 0 0x4000>;
1164 clock-names = "se";
1165 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_uart5_default>;
1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169 power-domains = <&rpmhpd SC7180_CX>;
1170 operating-points-v2 = <&qup_opp_table>;
1171 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173 interconnect-names = "qup-core", "qup-config";
1174 status = "disabled";
1175 };
1176 };
1177
1178 qupv3_id_1: geniqup@ac0000 {
1179 compatible = "qcom,geni-se-qup";
1180 reg = <0 0x00ac0000 0 0x6000>;
1181 clock-names = "m-ahb", "s-ahb";
1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184 #address-cells = <2>;
1185 #size-cells = <2>;
1186 ranges;
1187 iommus = <&apps_smmu 0x4c3 0x0>;
1188 status = "disabled";
1189
1190 i2c6: i2c@a80000 {
1191 compatible = "qcom,geni-i2c";
1192 reg = <0 0x00a80000 0 0x4000>;
1193 clock-names = "se";
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_i2c6_default>;
1197 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203 interconnect-names = "qup-core", "qup-config",
1204 "qup-memory";
1205 power-domains = <&rpmhpd SC7180_CX>;
1206 required-opps = <&rpmhpd_opp_low_svs>;
1207 status = "disabled";
1208 };
1209
1210 spi6: spi@a80000 {
1211 compatible = "qcom,geni-spi";
1212 reg = <0 0x00a80000 0 0x4000>;
1213 clock-names = "se";
1214 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 power-domains = <&rpmhpd SC7180_CX>;
1221 operating-points-v2 = <&qup_opp_table>;
1222 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224 interconnect-names = "qup-core", "qup-config";
1225 status = "disabled";
1226 };
1227
1228 uart6: serial@a80000 {
1229 compatible = "qcom,geni-uart";
1230 reg = <0 0x00a80000 0 0x4000>;
1231 clock-names = "se";
1232 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&qup_uart6_default>;
1235 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236 power-domains = <&rpmhpd SC7180_CX>;
1237 operating-points-v2 = <&qup_opp_table>;
1238 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240 interconnect-names = "qup-core", "qup-config";
1241 status = "disabled";
1242 };
1243
1244 i2c7: i2c@a84000 {
1245 compatible = "qcom,geni-i2c";
1246 reg = <0 0x00a84000 0 0x4000>;
1247 clock-names = "se";
1248 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_i2c7_default>;
1251 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257 interconnect-names = "qup-core", "qup-config",
1258 "qup-memory";
1259 power-domains = <&rpmhpd SC7180_CX>;
1260 required-opps = <&rpmhpd_opp_low_svs>;
1261 status = "disabled";
1262 };
1263
1264 uart7: serial@a84000 {
1265 compatible = "qcom,geni-uart";
1266 reg = <0 0x00a84000 0 0x4000>;
1267 clock-names = "se";
1268 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart7_default>;
1271 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains = <&rpmhpd SC7180_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1274 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276 interconnect-names = "qup-core", "qup-config";
1277 status = "disabled";
1278 };
1279
1280 i2c8: i2c@a88000 {
1281 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00a88000 0 0x4000>;
1283 clock-names = "se";
1284 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_i2c8_default>;
1287 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293 interconnect-names = "qup-core", "qup-config",
1294 "qup-memory";
1295 power-domains = <&rpmhpd SC7180_CX>;
1296 required-opps = <&rpmhpd_opp_low_svs>;
1297 status = "disabled";
1298 };
1299
1300 spi8: spi@a88000 {
1301 compatible = "qcom,geni-spi";
1302 reg = <0 0x00a88000 0 0x4000>;
1303 clock-names = "se";
1304 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305 pinctrl-names = "default";
1306 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 power-domains = <&rpmhpd SC7180_CX>;
1311 operating-points-v2 = <&qup_opp_table>;
1312 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314 interconnect-names = "qup-core", "qup-config";
1315 status = "disabled";
1316 };
1317
1318 uart8: serial@a88000 {
1319 compatible = "qcom,geni-debug-uart";
1320 reg = <0 0x00a88000 0 0x4000>;
1321 clock-names = "se";
1322 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323 pinctrl-names = "default";
1324 pinctrl-0 = <&qup_uart8_default>;
1325 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326 power-domains = <&rpmhpd SC7180_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1328 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330 interconnect-names = "qup-core", "qup-config";
1331 status = "disabled";
1332 };
1333
1334 i2c9: i2c@a8c000 {
1335 compatible = "qcom,geni-i2c";
1336 reg = <0 0x00a8c000 0 0x4000>;
1337 clock-names = "se";
1338 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 interconnect-names = "qup-core", "qup-config",
1348 "qup-memory";
1349 power-domains = <&rpmhpd SC7180_CX>;
1350 required-opps = <&rpmhpd_opp_low_svs>;
1351 status = "disabled";
1352 };
1353
1354 uart9: serial@a8c000 {
1355 compatible = "qcom,geni-uart";
1356 reg = <0 0x00a8c000 0 0x4000>;
1357 clock-names = "se";
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_uart9_default>;
1361 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362 power-domains = <&rpmhpd SC7180_CX>;
1363 operating-points-v2 = <&qup_opp_table>;
1364 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366 interconnect-names = "qup-core", "qup-config";
1367 status = "disabled";
1368 };
1369
1370 i2c10: i2c@a90000 {
1371 compatible = "qcom,geni-i2c";
1372 reg = <0 0x00a90000 0 0x4000>;
1373 clock-names = "se";
1374 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375 pinctrl-names = "default";
1376 pinctrl-0 = <&qup_i2c10_default>;
1377 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383 interconnect-names = "qup-core", "qup-config",
1384 "qup-memory";
1385 power-domains = <&rpmhpd SC7180_CX>;
1386 required-opps = <&rpmhpd_opp_low_svs>;
1387 status = "disabled";
1388 };
1389
1390 spi10: spi@a90000 {
1391 compatible = "qcom,geni-spi";
1392 reg = <0 0x00a90000 0 0x4000>;
1393 clock-names = "se";
1394 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395 pinctrl-names = "default";
1396 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 power-domains = <&rpmhpd SC7180_CX>;
1401 operating-points-v2 = <&qup_opp_table>;
1402 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404 interconnect-names = "qup-core", "qup-config";
1405 status = "disabled";
1406 };
1407
1408 uart10: serial@a90000 {
1409 compatible = "qcom,geni-uart";
1410 reg = <0 0x00a90000 0 0x4000>;
1411 clock-names = "se";
1412 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_uart10_default>;
1415 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416 power-domains = <&rpmhpd SC7180_CX>;
1417 operating-points-v2 = <&qup_opp_table>;
1418 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420 interconnect-names = "qup-core", "qup-config";
1421 status = "disabled";
1422 };
1423
1424 i2c11: i2c@a94000 {
1425 compatible = "qcom,geni-i2c";
1426 reg = <0 0x00a94000 0 0x4000>;
1427 clock-names = "se";
1428 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_i2c11_default>;
1431 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cells = <1>;
1433 #size-cells = <0>;
1434 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 interconnect-names = "qup-core", "qup-config",
1438 "qup-memory";
1439 power-domains = <&rpmhpd SC7180_CX>;
1440 required-opps = <&rpmhpd_opp_low_svs>;
1441 status = "disabled";
1442 };
1443
1444 spi11: spi@a94000 {
1445 compatible = "qcom,geni-spi";
1446 reg = <0 0x00a94000 0 0x4000>;
1447 clock-names = "se";
1448 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 power-domains = <&rpmhpd SC7180_CX>;
1455 operating-points-v2 = <&qup_opp_table>;
1456 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458 interconnect-names = "qup-core", "qup-config";
1459 status = "disabled";
1460 };
1461
1462 uart11: serial@a94000 {
1463 compatible = "qcom,geni-uart";
1464 reg = <0 0x00a94000 0 0x4000>;
1465 clock-names = "se";
1466 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&qup_uart11_default>;
1469 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470 power-domains = <&rpmhpd SC7180_CX>;
1471 operating-points-v2 = <&qup_opp_table>;
1472 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474 interconnect-names = "qup-core", "qup-config";
1475 status = "disabled";
1476 };
1477 };
1478
1479 config_noc: interconnect@1500000 {
1480 compatible = "qcom,sc7180-config-noc";
1481 reg = <0 0x01500000 0 0x28000>;
1482 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&apps_bcm_voter>;
1484 };
1485
1486 system_noc: interconnect@1620000 {
1487 compatible = "qcom,sc7180-system-noc";
1488 reg = <0 0x01620000 0 0x17080>;
1489 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&apps_bcm_voter>;
1491 };
1492
1493 mc_virt: interconnect@1638000 {
1494 compatible = "qcom,sc7180-mc-virt";
1495 reg = <0 0x01638000 0 0x1000>;
1496 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&apps_bcm_voter>;
1498 };
1499
1500 qup_virt: interconnect@1650000 {
1501 compatible = "qcom,sc7180-qup-virt";
1502 reg = <0 0x01650000 0 0x1000>;
1503 #interconnect-cells = <2>;
1504 qcom,bcm-voters = <&apps_bcm_voter>;
1505 };
1506
1507 aggre1_noc: interconnect@16e0000 {
1508 compatible = "qcom,sc7180-aggre1-noc";
1509 reg = <0 0x016e0000 0 0x15080>;
1510 #interconnect-cells = <2>;
1511 qcom,bcm-voters = <&apps_bcm_voter>;
1512 };
1513
1514 aggre2_noc: interconnect@1705000 {
1515 compatible = "qcom,sc7180-aggre2-noc";
1516 reg = <0 0x01705000 0 0x9000>;
1517 #interconnect-cells = <2>;
1518 qcom,bcm-voters = <&apps_bcm_voter>;
1519 };
1520
1521 compute_noc: interconnect@170e000 {
1522 compatible = "qcom,sc7180-compute-noc";
1523 reg = <0 0x0170e000 0 0x6000>;
1524 #interconnect-cells = <2>;
1525 qcom,bcm-voters = <&apps_bcm_voter>;
1526 };
1527
1528 mmss_noc: interconnect@1740000 {
1529 compatible = "qcom,sc7180-mmss-noc";
1530 reg = <0 0x01740000 0 0x1c100>;
1531 #interconnect-cells = <2>;
1532 qcom,bcm-voters = <&apps_bcm_voter>;
1533 };
1534
1535 ufs_mem_hc: ufshc@1d84000 {
1536 compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
1537 "jedec,ufs-2.0";
1538 reg = <0 0x01d84000 0 0x3000>;
1539 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1540 phys = <&ufs_mem_phy>;
1541 phy-names = "ufsphy";
1542 lanes-per-direction = <1>;
1543 #reset-cells = <1>;
1544 resets = <&gcc GCC_UFS_PHY_BCR>;
1545 reset-names = "rst";
1546
1547 power-domains = <&gcc UFS_PHY_GDSC>;
1548
1549 iommus = <&apps_smmu 0xa0 0x0>;
1550
1551 clock-names = "core_clk",
1552 "bus_aggr_clk",
1553 "iface_clk",
1554 "core_clk_unipro",
1555 "ref_clk",
1556 "tx_lane0_sync_clk",
1557 "rx_lane0_sync_clk";
1558 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1559 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1560 <&gcc GCC_UFS_PHY_AHB_CLK>,
1561 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1562 <&rpmhcc RPMH_CXO_CLK>,
1563 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1564 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
1565 freq-table-hz = <50000000 200000000>,
1566 <0 0>,
1567 <0 0>,
1568 <37500000 150000000>,
1569 <0 0>,
1570 <0 0>,
1571 <0 0>;
1572
1573 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
1574 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1575 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1576 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
1577 interconnect-names = "ufs-ddr", "cpu-ufs";
1578
1579 qcom,ice = <&ice>;
1580
1581 status = "disabled";
1582 };
1583
1584 ufs_mem_phy: phy@1d87000 {
1585 compatible = "qcom,sc7180-qmp-ufs-phy";
1586 reg = <0 0x01d87000 0 0x1000>;
1587 clocks = <&rpmhcc RPMH_CXO_CLK>,
1588 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1589 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
1590 clock-names = "ref",
1591 "ref_aux",
1592 "qref";
1593 power-domains = <&gcc UFS_PHY_GDSC>;
1594 resets = <&ufs_mem_hc 0>;
1595 reset-names = "ufsphy";
1596 #phy-cells = <0>;
1597 status = "disabled";
1598 };
1599
1600 ice: crypto@1d90000 {
1601 compatible = "qcom,sc7180-inline-crypto-engine",
1602 "qcom,inline-crypto-engine";
1603 reg = <0 0x01d90000 0 0x8000>;
1604 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1605 };
1606
1607 ipa: ipa@1e40000 {
1608 compatible = "qcom,sc7180-ipa";
1609
1610 iommus = <&apps_smmu 0x440 0x0>,
1611 <&apps_smmu 0x442 0x0>;
1612 reg = <0 0x01e40000 0 0x7000>,
1613 <0 0x01e47000 0 0x2000>,
1614 <0 0x01e04000 0 0x2c000>;
1615 reg-names = "ipa-reg",
1616 "ipa-shared",
1617 "gsi";
1618
1619 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1620 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1621 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1623 interrupt-names = "ipa",
1624 "gsi",
1625 "ipa-clock-query",
1626 "ipa-setup-ready";
1627
1628 clocks = <&rpmhcc RPMH_IPA_CLK>;
1629 clock-names = "core";
1630
1631 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1632 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1633 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1634 interconnect-names = "memory",
1635 "imem",
1636 "config";
1637
1638 qcom,qmp = <&aoss_qmp>;
1639
1640 qcom,smem-states = <&ipa_smp2p_out 0>,
1641 <&ipa_smp2p_out 1>;
1642 qcom,smem-state-names = "ipa-clock-enabled-valid",
1643 "ipa-clock-enabled";
1644
1645 status = "disabled";
1646 };
1647
1648 tcsr_mutex: hwlock@1f40000 {
1649 compatible = "qcom,tcsr-mutex";
1650 reg = <0 0x01f40000 0 0x20000>;
1651 #hwlock-cells = <1>;
1652 };
1653
1654 tcsr_regs_1: syscon@1f60000 {
1655 compatible = "qcom,sc7180-tcsr", "syscon";
1656 reg = <0 0x01f60000 0 0x20000>;
1657 };
1658
1659 tcsr_regs_2: syscon@1fc0000 {
1660 compatible = "qcom,sc7180-tcsr", "syscon";
1661 reg = <0 0x01fc0000 0 0x40000>;
1662 };
1663
1664 tlmm: pinctrl@3500000 {
1665 compatible = "qcom,sc7180-pinctrl";
1666 reg = <0 0x03500000 0 0x300000>,
1667 <0 0x03900000 0 0x300000>,
1668 <0 0x03d00000 0 0x300000>;
1669 reg-names = "west", "north", "south";
1670 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1671 gpio-controller;
1672 #gpio-cells = <2>;
1673 interrupt-controller;
1674 #interrupt-cells = <2>;
1675 gpio-ranges = <&tlmm 0 0 120>;
1676 wakeup-parent = <&pdc>;
1677
1678 dp_hot_plug_det: dp-hot-plug-det-state {
1679 pins = "gpio117";
1680 function = "dp_hot";
1681 };
1682
1683 qspi_clk: qspi-clk-state {
1684 pins = "gpio63";
1685 function = "qspi_clk";
1686 };
1687
1688 qspi_cs0: qspi-cs0-state {
1689 pins = "gpio68";
1690 function = "qspi_cs";
1691 };
1692
1693 qspi_cs1: qspi-cs1-state {
1694 pins = "gpio72";
1695 function = "qspi_cs";
1696 };
1697
1698 qspi_data0: qspi-data0-state {
1699 pins = "gpio64";
1700 function = "qspi_data";
1701 };
1702
1703 qspi_data1: qspi-data1-state {
1704 pins = "gpio65";
1705 function = "qspi_data";
1706 };
1707
1708 qspi_data23: qspi-data23-state {
1709 pins = "gpio66", "gpio67";
1710 function = "qspi_data";
1711 };
1712
1713 qup_i2c0_default: qup-i2c0-default-state {
1714 pins = "gpio34", "gpio35";
1715 function = "qup00";
1716 };
1717
1718 qup_i2c1_default: qup-i2c1-default-state {
1719 pins = "gpio0", "gpio1";
1720 function = "qup01";
1721 };
1722
1723 qup_i2c2_default: qup-i2c2-default-state {
1724 pins = "gpio15", "gpio16";
1725 function = "qup02_i2c";
1726 };
1727
1728 qup_i2c3_default: qup-i2c3-default-state {
1729 pins = "gpio38", "gpio39";
1730 function = "qup03";
1731 };
1732
1733 qup_i2c4_default: qup-i2c4-default-state {
1734 pins = "gpio115", "gpio116";
1735 function = "qup04_i2c";
1736 };
1737
1738 qup_i2c5_default: qup-i2c5-default-state {
1739 pins = "gpio25", "gpio26";
1740 function = "qup05";
1741 };
1742
1743 qup_i2c6_default: qup-i2c6-default-state {
1744 pins = "gpio59", "gpio60";
1745 function = "qup10";
1746 };
1747
1748 qup_i2c7_default: qup-i2c7-default-state {
1749 pins = "gpio6", "gpio7";
1750 function = "qup11_i2c";
1751 };
1752
1753 qup_i2c8_default: qup-i2c8-default-state {
1754 pins = "gpio42", "gpio43";
1755 function = "qup12";
1756 };
1757
1758 qup_i2c9_default: qup-i2c9-default-state {
1759 pins = "gpio46", "gpio47";
1760 function = "qup13_i2c";
1761 };
1762
1763 qup_i2c10_default: qup-i2c10-default-state {
1764 pins = "gpio86", "gpio87";
1765 function = "qup14";
1766 };
1767
1768 qup_i2c11_default: qup-i2c11-default-state {
1769 pins = "gpio53", "gpio54";
1770 function = "qup15";
1771 };
1772
1773 qup_spi0_spi: qup-spi0-spi-state {
1774 pins = "gpio34", "gpio35", "gpio36";
1775 function = "qup00";
1776 };
1777
1778 qup_spi0_cs: qup-spi0-cs-state {
1779 pins = "gpio37";
1780 function = "qup00";
1781 };
1782
1783 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1784 pins = "gpio37";
1785 function = "gpio";
1786 };
1787
1788 qup_spi1_spi: qup-spi1-spi-state {
1789 pins = "gpio0", "gpio1", "gpio2";
1790 function = "qup01";
1791 };
1792
1793 qup_spi1_cs: qup-spi1-cs-state {
1794 pins = "gpio3";
1795 function = "qup01";
1796 };
1797
1798 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1799 pins = "gpio3";
1800 function = "gpio";
1801 };
1802
1803 qup_spi3_spi: qup-spi3-spi-state {
1804 pins = "gpio38", "gpio39", "gpio40";
1805 function = "qup03";
1806 };
1807
1808 qup_spi3_cs: qup-spi3-cs-state {
1809 pins = "gpio41";
1810 function = "qup03";
1811 };
1812
1813 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1814 pins = "gpio41";
1815 function = "gpio";
1816 };
1817
1818 qup_spi5_spi: qup-spi5-spi-state {
1819 pins = "gpio25", "gpio26", "gpio27";
1820 function = "qup05";
1821 };
1822
1823 qup_spi5_cs: qup-spi5-cs-state {
1824 pins = "gpio28";
1825 function = "qup05";
1826 };
1827
1828 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1829 pins = "gpio28";
1830 function = "gpio";
1831 };
1832
1833 qup_spi6_spi: qup-spi6-spi-state {
1834 pins = "gpio59", "gpio60", "gpio61";
1835 function = "qup10";
1836 };
1837
1838 qup_spi6_cs: qup-spi6-cs-state {
1839 pins = "gpio62";
1840 function = "qup10";
1841 };
1842
1843 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1844 pins = "gpio62";
1845 function = "gpio";
1846 };
1847
1848 qup_spi8_spi: qup-spi8-spi-state {
1849 pins = "gpio42", "gpio43", "gpio44";
1850 function = "qup12";
1851 };
1852
1853 qup_spi8_cs: qup-spi8-cs-state {
1854 pins = "gpio45";
1855 function = "qup12";
1856 };
1857
1858 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1859 pins = "gpio45";
1860 function = "gpio";
1861 };
1862
1863 qup_spi10_spi: qup-spi10-spi-state {
1864 pins = "gpio86", "gpio87", "gpio88";
1865 function = "qup14";
1866 };
1867
1868 qup_spi10_cs: qup-spi10-cs-state {
1869 pins = "gpio89";
1870 function = "qup14";
1871 };
1872
1873 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1874 pins = "gpio89";
1875 function = "gpio";
1876 };
1877
1878 qup_spi11_spi: qup-spi11-spi-state {
1879 pins = "gpio53", "gpio54", "gpio55";
1880 function = "qup15";
1881 };
1882
1883 qup_spi11_cs: qup-spi11-cs-state {
1884 pins = "gpio56";
1885 function = "qup15";
1886 };
1887
1888 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1889 pins = "gpio56";
1890 function = "gpio";
1891 };
1892
1893 qup_uart0_default: qup-uart0-default-state {
1894 qup_uart0_cts: cts-pins {
1895 pins = "gpio34";
1896 function = "qup00";
1897 };
1898
1899 qup_uart0_rts: rts-pins {
1900 pins = "gpio35";
1901 function = "qup00";
1902 };
1903
1904 qup_uart0_tx: tx-pins {
1905 pins = "gpio36";
1906 function = "qup00";
1907 };
1908
1909 qup_uart0_rx: rx-pins {
1910 pins = "gpio37";
1911 function = "qup00";
1912 };
1913 };
1914
1915 qup_uart1_default: qup-uart1-default-state {
1916 qup_uart1_cts: cts-pins {
1917 pins = "gpio0";
1918 function = "qup01";
1919 };
1920
1921 qup_uart1_rts: rts-pins {
1922 pins = "gpio1";
1923 function = "qup01";
1924 };
1925
1926 qup_uart1_tx: tx-pins {
1927 pins = "gpio2";
1928 function = "qup01";
1929 };
1930
1931 qup_uart1_rx: rx-pins {
1932 pins = "gpio3";
1933 function = "qup01";
1934 };
1935 };
1936
1937 qup_uart2_default: qup-uart2-default-state {
1938 qup_uart2_tx: tx-pins {
1939 pins = "gpio15";
1940 function = "qup02_uart";
1941 };
1942
1943 qup_uart2_rx: rx-pins {
1944 pins = "gpio16";
1945 function = "qup02_uart";
1946 };
1947 };
1948
1949 qup_uart3_default: qup-uart3-default-state {
1950 qup_uart3_cts: cts-pins {
1951 pins = "gpio38";
1952 function = "qup03";
1953 };
1954
1955 qup_uart3_rts: rts-pins {
1956 pins = "gpio39";
1957 function = "qup03";
1958 };
1959
1960 qup_uart3_tx: tx-pins {
1961 pins = "gpio40";
1962 function = "qup03";
1963 };
1964
1965 qup_uart3_rx: rx-pins {
1966 pins = "gpio41";
1967 function = "qup03";
1968 };
1969 };
1970
1971 qup_uart4_default: qup-uart4-default-state {
1972 qup_uart4_tx: tx-pins {
1973 pins = "gpio115";
1974 function = "qup04_uart";
1975 };
1976
1977 qup_uart4_rx: rx-pins {
1978 pins = "gpio116";
1979 function = "qup04_uart";
1980 };
1981 };
1982
1983 qup_uart5_default: qup-uart5-default-state {
1984 qup_uart5_cts: cts-pins {
1985 pins = "gpio25";
1986 function = "qup05";
1987 };
1988
1989 qup_uart5_rts: rts-pins {
1990 pins = "gpio26";
1991 function = "qup05";
1992 };
1993
1994 qup_uart5_tx: tx-pins {
1995 pins = "gpio27";
1996 function = "qup05";
1997 };
1998
1999 qup_uart5_rx: rx-pins {
2000 pins = "gpio28";
2001 function = "qup05";
2002 };
2003 };
2004
2005 qup_uart6_default: qup-uart6-default-state {
2006 qup_uart6_cts: cts-pins {
2007 pins = "gpio59";
2008 function = "qup10";
2009 };
2010
2011 qup_uart6_rts: rts-pins {
2012 pins = "gpio60";
2013 function = "qup10";
2014 };
2015
2016 qup_uart6_tx: tx-pins {
2017 pins = "gpio61";
2018 function = "qup10";
2019 };
2020
2021 qup_uart6_rx: rx-pins {
2022 pins = "gpio62";
2023 function = "qup10";
2024 };
2025 };
2026
2027 qup_uart7_default: qup-uart7-default-state {
2028 qup_uart7_tx: tx-pins {
2029 pins = "gpio6";
2030 function = "qup11_uart";
2031 };
2032
2033 qup_uart7_rx: rx-pins {
2034 pins = "gpio7";
2035 function = "qup11_uart";
2036 };
2037 };
2038
2039 qup_uart8_default: qup-uart8-default-state {
2040 qup_uart8_tx: tx-pins {
2041 pins = "gpio44";
2042 function = "qup12";
2043 };
2044
2045 qup_uart8_rx: rx-pins {
2046 pins = "gpio45";
2047 function = "qup12";
2048 };
2049 };
2050
2051 qup_uart9_default: qup-uart9-default-state {
2052 qup_uart9_tx: tx-pins {
2053 pins = "gpio46";
2054 function = "qup13_uart";
2055 };
2056
2057 qup_uart9_rx: rx-pins {
2058 pins = "gpio47";
2059 function = "qup13_uart";
2060 };
2061 };
2062
2063 qup_uart10_default: qup-uart10-default-state {
2064 qup_uart10_cts: cts-pins {
2065 pins = "gpio86";
2066 function = "qup14";
2067 };
2068
2069 qup_uart10_rts: rts-pins {
2070 pins = "gpio87";
2071 function = "qup14";
2072 };
2073
2074 qup_uart10_tx: tx-pins {
2075 pins = "gpio88";
2076 function = "qup14";
2077 };
2078
2079 qup_uart10_rx: rx-pins {
2080 pins = "gpio89";
2081 function = "qup14";
2082 };
2083 };
2084
2085 qup_uart11_default: qup-uart11-default-state {
2086 qup_uart11_cts: cts-pins {
2087 pins = "gpio53";
2088 function = "qup15";
2089 };
2090
2091 qup_uart11_rts: rts-pins {
2092 pins = "gpio54";
2093 function = "qup15";
2094 };
2095
2096 qup_uart11_tx: tx-pins {
2097 pins = "gpio55";
2098 function = "qup15";
2099 };
2100
2101 qup_uart11_rx: rx-pins {
2102 pins = "gpio56";
2103 function = "qup15";
2104 };
2105 };
2106
2107 sec_mi2s_active: sec-mi2s-active-state {
2108 pins = "gpio49", "gpio50", "gpio51";
2109 function = "mi2s_1";
2110 };
2111
2112 pri_mi2s_active: pri-mi2s-active-state {
2113 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2114 function = "mi2s_0";
2115 };
2116
2117 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2118 pins = "gpio57";
2119 function = "lpass_ext";
2120 };
2121
2122 ter_mi2s_active: ter-mi2s-active-state {
2123 pins = "gpio63", "gpio64", "gpio65", "gpio66";
2124 function = "mi2s_2";
2125 };
2126 };
2127
2128 remoteproc_mpss: remoteproc@4080000 {
2129 compatible = "qcom,sc7180-mpss-pas";
2130 reg = <0 0x04080000 0 0x4040>;
2131
2132 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2133 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2134 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2135 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2136 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2137 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2138 interrupt-names = "wdog", "fatal", "ready", "handover",
2139 "stop-ack", "shutdown-ack";
2140
2141 clocks = <&rpmhcc RPMH_CXO_CLK>;
2142 clock-names = "xo";
2143
2144 power-domains = <&rpmhpd SC7180_CX>,
2145 <&rpmhpd SC7180_MX>,
2146 <&rpmhpd SC7180_MSS>;
2147 power-domain-names = "cx", "mx", "mss";
2148
2149 memory-region = <&mpss_mem>;
2150
2151 qcom,qmp = <&aoss_qmp>;
2152
2153 qcom,smem-states = <&modem_smp2p_out 0>;
2154 qcom,smem-state-names = "stop";
2155
2156 status = "disabled";
2157
2158 glink-edge {
2159 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2160 label = "modem";
2161 qcom,remote-pid = <1>;
2162 mboxes = <&apss_shared 12>;
2163 };
2164 };
2165
2166 gpu: gpu@5000000 {
2167 compatible = "qcom,adreno-618.0", "qcom,adreno";
2168 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2169 <0 0x05061000 0 0x800>;
2170 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2171 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&adreno_smmu 0>;
2173 operating-points-v2 = <&gpu_opp_table>;
2174 qcom,gmu = <&gmu>;
2175
2176 #cooling-cells = <2>;
2177
2178 nvmem-cells = <&gpu_speed_bin>;
2179 nvmem-cell-names = "speed_bin";
2180
2181 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2182 interconnect-names = "gfx-mem";
2183
2184 gpu_opp_table: opp-table {
2185 compatible = "operating-points-v2";
2186
2187 opp-825000000 {
2188 opp-hz = /bits/ 64 <825000000>;
2189 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2190 opp-peak-kBps = <8532000>;
2191 opp-supported-hw = <0x04>;
2192 };
2193
2194 opp-800000000 {
2195 opp-hz = /bits/ 64 <800000000>;
2196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2197 opp-peak-kBps = <8532000>;
2198 opp-supported-hw = <0x07>;
2199 };
2200
2201 opp-650000000 {
2202 opp-hz = /bits/ 64 <650000000>;
2203 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2204 opp-peak-kBps = <7216000>;
2205 opp-supported-hw = <0x07>;
2206 };
2207
2208 opp-565000000 {
2209 opp-hz = /bits/ 64 <565000000>;
2210 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2211 opp-peak-kBps = <5412000>;
2212 opp-supported-hw = <0x07>;
2213 };
2214
2215 opp-430000000 {
2216 opp-hz = /bits/ 64 <430000000>;
2217 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2218 opp-peak-kBps = <5412000>;
2219 opp-supported-hw = <0x07>;
2220 };
2221
2222 opp-355000000 {
2223 opp-hz = /bits/ 64 <355000000>;
2224 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2225 opp-peak-kBps = <3072000>;
2226 opp-supported-hw = <0x07>;
2227 };
2228
2229 opp-267000000 {
2230 opp-hz = /bits/ 64 <267000000>;
2231 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2232 opp-peak-kBps = <3072000>;
2233 opp-supported-hw = <0x07>;
2234 };
2235
2236 opp-180000000 {
2237 opp-hz = /bits/ 64 <180000000>;
2238 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2239 opp-peak-kBps = <1804000>;
2240 opp-supported-hw = <0x07>;
2241 };
2242 };
2243 };
2244
2245 adreno_smmu: iommu@5040000 {
2246 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2247 reg = <0 0x05040000 0 0x10000>;
2248 #iommu-cells = <1>;
2249 #global-interrupts = <2>;
2250 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2253 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2254 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2255 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2256 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2257 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2258 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2259 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2260
2261 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2262 <&gcc GCC_GPU_CFG_AHB_CLK>;
2263 clock-names = "bus", "iface";
2264
2265 power-domains = <&gpucc CX_GDSC>;
2266 };
2267
2268 gmu: gmu@506a000 {
2269 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2270 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2271 <0 0x0b490000 0 0x10000>;
2272 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2273 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275 interrupt-names = "hfi", "gmu";
2276 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2277 <&gpucc GPU_CC_CXO_CLK>,
2278 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2279 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2280 clock-names = "gmu", "cxo", "axi", "memnoc";
2281 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2282 power-domain-names = "cx", "gx";
2283 iommus = <&adreno_smmu 5>;
2284 operating-points-v2 = <&gmu_opp_table>;
2285
2286 gmu_opp_table: opp-table {
2287 compatible = "operating-points-v2";
2288
2289 opp-200000000 {
2290 opp-hz = /bits/ 64 <200000000>;
2291 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 };
2293 };
2294 };
2295
2296 gpucc: clock-controller@5090000 {
2297 compatible = "qcom,sc7180-gpucc";
2298 reg = <0 0x05090000 0 0x9000>;
2299 clocks = <&rpmhcc RPMH_CXO_CLK>,
2300 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302 clock-names = "bi_tcxo",
2303 "gcc_gpu_gpll0_clk_src",
2304 "gcc_gpu_gpll0_div_clk_src";
2305 #clock-cells = <1>;
2306 #reset-cells = <1>;
2307 #power-domain-cells = <1>;
2308 };
2309
2310 dma@10a2000 {
2311 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2312 reg = <0x0 0x010a2000 0x0 0x1000>,
2313 <0x0 0x010ae000 0x0 0x2000>;
2314 status = "disabled";
2315 };
2316
2317 stm@6002000 {
2318 compatible = "arm,coresight-stm", "arm,primecell";
2319 reg = <0 0x06002000 0 0x1000>,
2320 <0 0x16280000 0 0x180000>;
2321 reg-names = "stm-base", "stm-stimulus-base";
2322
2323 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pclk";
2325
2326 out-ports {
2327 port {
2328 stm_out: endpoint {
2329 remote-endpoint = <&funnel0_in7>;
2330 };
2331 };
2332 };
2333 };
2334
2335 funnel@6041000 {
2336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2337 reg = <0 0x06041000 0 0x1000>;
2338
2339 clocks = <&aoss_qmp>;
2340 clock-names = "apb_pclk";
2341
2342 out-ports {
2343 port {
2344 funnel0_out: endpoint {
2345 remote-endpoint = <&merge_funnel_in0>;
2346 };
2347 };
2348 };
2349
2350 in-ports {
2351 #address-cells = <1>;
2352 #size-cells = <0>;
2353
2354 port@7 {
2355 reg = <7>;
2356 funnel0_in7: endpoint {
2357 remote-endpoint = <&stm_out>;
2358 };
2359 };
2360 };
2361 };
2362
2363 funnel@6042000 {
2364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 reg = <0 0x06042000 0 0x1000>;
2366
2367 clocks = <&aoss_qmp>;
2368 clock-names = "apb_pclk";
2369
2370 out-ports {
2371 port {
2372 funnel1_out: endpoint {
2373 remote-endpoint = <&merge_funnel_in1>;
2374 };
2375 };
2376 };
2377
2378 in-ports {
2379 #address-cells = <1>;
2380 #size-cells = <0>;
2381
2382 port@4 {
2383 reg = <4>;
2384 funnel1_in4: endpoint {
2385 remote-endpoint = <&apss_merge_funnel_out>;
2386 };
2387 };
2388 };
2389 };
2390
2391 funnel@6045000 {
2392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 reg = <0 0x06045000 0 0x1000>;
2394
2395 clocks = <&aoss_qmp>;
2396 clock-names = "apb_pclk";
2397
2398 out-ports {
2399 port {
2400 merge_funnel_out: endpoint {
2401 remote-endpoint = <&swao_funnel_in>;
2402 };
2403 };
2404 };
2405
2406 in-ports {
2407 #address-cells = <1>;
2408 #size-cells = <0>;
2409
2410 port@0 {
2411 reg = <0>;
2412 merge_funnel_in0: endpoint {
2413 remote-endpoint = <&funnel0_out>;
2414 };
2415 };
2416
2417 port@1 {
2418 reg = <1>;
2419 merge_funnel_in1: endpoint {
2420 remote-endpoint = <&funnel1_out>;
2421 };
2422 };
2423 };
2424 };
2425
2426 replicator@6046000 {
2427 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2428 reg = <0 0x06046000 0 0x1000>;
2429
2430 clocks = <&aoss_qmp>;
2431 clock-names = "apb_pclk";
2432
2433 out-ports {
2434 port {
2435 replicator_out: endpoint {
2436 remote-endpoint = <&etr_in>;
2437 };
2438 };
2439 };
2440
2441 in-ports {
2442 port {
2443 replicator_in: endpoint {
2444 remote-endpoint = <&swao_replicator_out>;
2445 };
2446 };
2447 };
2448 };
2449
2450 etr@6048000 {
2451 compatible = "arm,coresight-tmc", "arm,primecell";
2452 reg = <0 0x06048000 0 0x1000>;
2453 iommus = <&apps_smmu 0x04a0 0x20>;
2454
2455 clocks = <&aoss_qmp>;
2456 clock-names = "apb_pclk";
2457 arm,scatter-gather;
2458
2459 in-ports {
2460 port {
2461 etr_in: endpoint {
2462 remote-endpoint = <&replicator_out>;
2463 };
2464 };
2465 };
2466 };
2467
2468 funnel@6b04000 {
2469 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2470 reg = <0 0x06b04000 0 0x1000>;
2471
2472 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pclk";
2474
2475 out-ports {
2476 port {
2477 swao_funnel_out: endpoint {
2478 remote-endpoint = <&etf_in>;
2479 };
2480 };
2481 };
2482
2483 in-ports {
2484 #address-cells = <1>;
2485 #size-cells = <0>;
2486
2487 port@7 {
2488 reg = <7>;
2489 swao_funnel_in: endpoint {
2490 remote-endpoint = <&merge_funnel_out>;
2491 };
2492 };
2493 };
2494 };
2495
2496 etf@6b05000 {
2497 compatible = "arm,coresight-tmc", "arm,primecell";
2498 reg = <0 0x06b05000 0 0x1000>;
2499
2500 clocks = <&aoss_qmp>;
2501 clock-names = "apb_pclk";
2502
2503 out-ports {
2504 port {
2505 etf_out: endpoint {
2506 remote-endpoint = <&swao_replicator_in>;
2507 };
2508 };
2509 };
2510
2511 in-ports {
2512 port {
2513 etf_in: endpoint {
2514 remote-endpoint = <&swao_funnel_out>;
2515 };
2516 };
2517 };
2518 };
2519
2520 replicator@6b06000 {
2521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2522 reg = <0 0x06b06000 0 0x1000>;
2523
2524 clocks = <&aoss_qmp>;
2525 clock-names = "apb_pclk";
2526 qcom,replicator-loses-context;
2527
2528 out-ports {
2529 port {
2530 swao_replicator_out: endpoint {
2531 remote-endpoint = <&replicator_in>;
2532 };
2533 };
2534 };
2535
2536 in-ports {
2537 port {
2538 swao_replicator_in: endpoint {
2539 remote-endpoint = <&etf_out>;
2540 };
2541 };
2542 };
2543 };
2544
2545 etm@7040000 {
2546 compatible = "arm,coresight-etm4x", "arm,primecell";
2547 reg = <0 0x07040000 0 0x1000>;
2548
2549 cpu = <&CPU0>;
2550
2551 clocks = <&aoss_qmp>;
2552 clock-names = "apb_pclk";
2553 arm,coresight-loses-context-with-cpu;
2554 qcom,skip-power-up;
2555
2556 out-ports {
2557 port {
2558 etm0_out: endpoint {
2559 remote-endpoint = <&apss_funnel_in0>;
2560 };
2561 };
2562 };
2563 };
2564
2565 etm@7140000 {
2566 compatible = "arm,coresight-etm4x", "arm,primecell";
2567 reg = <0 0x07140000 0 0x1000>;
2568
2569 cpu = <&CPU1>;
2570
2571 clocks = <&aoss_qmp>;
2572 clock-names = "apb_pclk";
2573 arm,coresight-loses-context-with-cpu;
2574 qcom,skip-power-up;
2575
2576 out-ports {
2577 port {
2578 etm1_out: endpoint {
2579 remote-endpoint = <&apss_funnel_in1>;
2580 };
2581 };
2582 };
2583 };
2584
2585 etm@7240000 {
2586 compatible = "arm,coresight-etm4x", "arm,primecell";
2587 reg = <0 0x07240000 0 0x1000>;
2588
2589 cpu = <&CPU2>;
2590
2591 clocks = <&aoss_qmp>;
2592 clock-names = "apb_pclk";
2593 arm,coresight-loses-context-with-cpu;
2594 qcom,skip-power-up;
2595
2596 out-ports {
2597 port {
2598 etm2_out: endpoint {
2599 remote-endpoint = <&apss_funnel_in2>;
2600 };
2601 };
2602 };
2603 };
2604
2605 etm@7340000 {
2606 compatible = "arm,coresight-etm4x", "arm,primecell";
2607 reg = <0 0x07340000 0 0x1000>;
2608
2609 cpu = <&CPU3>;
2610
2611 clocks = <&aoss_qmp>;
2612 clock-names = "apb_pclk";
2613 arm,coresight-loses-context-with-cpu;
2614 qcom,skip-power-up;
2615
2616 out-ports {
2617 port {
2618 etm3_out: endpoint {
2619 remote-endpoint = <&apss_funnel_in3>;
2620 };
2621 };
2622 };
2623 };
2624
2625 etm@7440000 {
2626 compatible = "arm,coresight-etm4x", "arm,primecell";
2627 reg = <0 0x07440000 0 0x1000>;
2628
2629 cpu = <&CPU4>;
2630
2631 clocks = <&aoss_qmp>;
2632 clock-names = "apb_pclk";
2633 arm,coresight-loses-context-with-cpu;
2634 qcom,skip-power-up;
2635
2636 out-ports {
2637 port {
2638 etm4_out: endpoint {
2639 remote-endpoint = <&apss_funnel_in4>;
2640 };
2641 };
2642 };
2643 };
2644
2645 etm@7540000 {
2646 compatible = "arm,coresight-etm4x", "arm,primecell";
2647 reg = <0 0x07540000 0 0x1000>;
2648
2649 cpu = <&CPU5>;
2650
2651 clocks = <&aoss_qmp>;
2652 clock-names = "apb_pclk";
2653 arm,coresight-loses-context-with-cpu;
2654 qcom,skip-power-up;
2655
2656 out-ports {
2657 port {
2658 etm5_out: endpoint {
2659 remote-endpoint = <&apss_funnel_in5>;
2660 };
2661 };
2662 };
2663 };
2664
2665 etm@7640000 {
2666 compatible = "arm,coresight-etm4x", "arm,primecell";
2667 reg = <0 0x07640000 0 0x1000>;
2668
2669 cpu = <&CPU6>;
2670
2671 clocks = <&aoss_qmp>;
2672 clock-names = "apb_pclk";
2673 arm,coresight-loses-context-with-cpu;
2674 qcom,skip-power-up;
2675
2676 out-ports {
2677 port {
2678 etm6_out: endpoint {
2679 remote-endpoint = <&apss_funnel_in6>;
2680 };
2681 };
2682 };
2683 };
2684
2685 etm@7740000 {
2686 compatible = "arm,coresight-etm4x", "arm,primecell";
2687 reg = <0 0x07740000 0 0x1000>;
2688
2689 cpu = <&CPU7>;
2690
2691 clocks = <&aoss_qmp>;
2692 clock-names = "apb_pclk";
2693 arm,coresight-loses-context-with-cpu;
2694 qcom,skip-power-up;
2695
2696 out-ports {
2697 port {
2698 etm7_out: endpoint {
2699 remote-endpoint = <&apss_funnel_in7>;
2700 };
2701 };
2702 };
2703 };
2704
2705 funnel@7800000 { /* APSS Funnel */
2706 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2707 reg = <0 0x07800000 0 0x1000>;
2708
2709 clocks = <&aoss_qmp>;
2710 clock-names = "apb_pclk";
2711
2712 out-ports {
2713 port {
2714 apss_funnel_out: endpoint {
2715 remote-endpoint = <&apss_merge_funnel_in>;
2716 };
2717 };
2718 };
2719
2720 in-ports {
2721 #address-cells = <1>;
2722 #size-cells = <0>;
2723
2724 port@0 {
2725 reg = <0>;
2726 apss_funnel_in0: endpoint {
2727 remote-endpoint = <&etm0_out>;
2728 };
2729 };
2730
2731 port@1 {
2732 reg = <1>;
2733 apss_funnel_in1: endpoint {
2734 remote-endpoint = <&etm1_out>;
2735 };
2736 };
2737
2738 port@2 {
2739 reg = <2>;
2740 apss_funnel_in2: endpoint {
2741 remote-endpoint = <&etm2_out>;
2742 };
2743 };
2744
2745 port@3 {
2746 reg = <3>;
2747 apss_funnel_in3: endpoint {
2748 remote-endpoint = <&etm3_out>;
2749 };
2750 };
2751
2752 port@4 {
2753 reg = <4>;
2754 apss_funnel_in4: endpoint {
2755 remote-endpoint = <&etm4_out>;
2756 };
2757 };
2758
2759 port@5 {
2760 reg = <5>;
2761 apss_funnel_in5: endpoint {
2762 remote-endpoint = <&etm5_out>;
2763 };
2764 };
2765
2766 port@6 {
2767 reg = <6>;
2768 apss_funnel_in6: endpoint {
2769 remote-endpoint = <&etm6_out>;
2770 };
2771 };
2772
2773 port@7 {
2774 reg = <7>;
2775 apss_funnel_in7: endpoint {
2776 remote-endpoint = <&etm7_out>;
2777 };
2778 };
2779 };
2780 };
2781
2782 funnel@7810000 {
2783 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2784 reg = <0 0x07810000 0 0x1000>;
2785
2786 clocks = <&aoss_qmp>;
2787 clock-names = "apb_pclk";
2788
2789 out-ports {
2790 port {
2791 apss_merge_funnel_out: endpoint {
2792 remote-endpoint = <&funnel1_in4>;
2793 };
2794 };
2795 };
2796
2797 in-ports {
2798 port {
2799 apss_merge_funnel_in: endpoint {
2800 remote-endpoint = <&apss_funnel_out>;
2801 };
2802 };
2803 };
2804 };
2805
2806 sdhc_2: mmc@8804000 {
2807 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2808 reg = <0 0x08804000 0 0x1000>;
2809
2810 iommus = <&apps_smmu 0x80 0>;
2811 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2813 interrupt-names = "hc_irq", "pwr_irq";
2814
2815 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2816 <&gcc GCC_SDCC2_APPS_CLK>,
2817 <&rpmhcc RPMH_CXO_CLK>;
2818 clock-names = "iface", "core", "xo";
2819
2820 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2822 interconnect-names = "sdhc-ddr","cpu-sdhc";
2823 power-domains = <&rpmhpd SC7180_CX>;
2824 operating-points-v2 = <&sdhc2_opp_table>;
2825
2826 bus-width = <4>;
2827
2828 status = "disabled";
2829
2830 sdhc2_opp_table: opp-table {
2831 compatible = "operating-points-v2";
2832
2833 opp-100000000 {
2834 opp-hz = /bits/ 64 <100000000>;
2835 required-opps = <&rpmhpd_opp_low_svs>;
2836 opp-peak-kBps = <1800000 600000>;
2837 opp-avg-kBps = <100000 0>;
2838 };
2839
2840 opp-202000000 {
2841 opp-hz = /bits/ 64 <202000000>;
2842 required-opps = <&rpmhpd_opp_nom>;
2843 opp-peak-kBps = <5400000 1600000>;
2844 opp-avg-kBps = <200000 0>;
2845 };
2846 };
2847 };
2848
2849 qspi: spi@88dc000 {
2850 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2851 reg = <0 0x088dc000 0 0x600>;
2852 iommus = <&apps_smmu 0x20 0x0>;
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2855 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2856 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2857 <&gcc GCC_QSPI_CORE_CLK>;
2858 clock-names = "iface", "core";
2859 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2860 &config_noc SLAVE_QSPI_0 0>;
2861 interconnect-names = "qspi-config";
2862 power-domains = <&rpmhpd SC7180_CX>;
2863 operating-points-v2 = <&qspi_opp_table>;
2864 status = "disabled";
2865 };
2866
2867 usb_1_hsphy: phy@88e3000 {
2868 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2869 reg = <0 0x088e3000 0 0x400>;
2870 status = "disabled";
2871 #phy-cells = <0>;
2872 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2873 <&rpmhcc RPMH_CXO_CLK>;
2874 clock-names = "cfg_ahb", "ref";
2875 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2876
2877 nvmem-cells = <&qusb2p_hstx_trim>;
2878 };
2879
2880 usb_1_qmpphy: phy@88e8000 {
2881 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2882 reg = <0 0x088e8000 0 0x3000>;
2883 status = "disabled";
2884
2885 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2886 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2887 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2888 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
2889 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2890 clock-names = "aux",
2891 "ref",
2892 "com_aux",
2893 "usb3_pipe",
2894 "cfg_ahb";
2895
2896 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2897 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2898 reset-names = "phy", "common";
2899
2900 #clock-cells = <1>;
2901 #phy-cells = <1>;
2902 };
2903
2904 pmu@90b6300 {
2905 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2906 reg = <0 0x090b6300 0 0x600>;
2907 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2908
2909 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2910 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
2911 operating-points-v2 = <&cpu_bwmon_opp_table>;
2912
2913 cpu_bwmon_opp_table: opp-table {
2914 compatible = "operating-points-v2";
2915
2916 opp-0 {
2917 opp-peak-kBps = <2288000>;
2918 };
2919
2920 opp-1 {
2921 opp-peak-kBps = <4577000>;
2922 };
2923
2924 opp-2 {
2925 opp-peak-kBps = <7110000>;
2926 };
2927
2928 opp-3 {
2929 opp-peak-kBps = <9155000>;
2930 };
2931
2932 opp-4 {
2933 opp-peak-kBps = <12298000>;
2934 };
2935
2936 opp-5 {
2937 opp-peak-kBps = <14236000>;
2938 };
2939 };
2940 };
2941
2942 pmu@90cd000 {
2943 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2944 reg = <0 0x090cd000 0 0x1000>;
2945 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2946
2947 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
2948 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2949 operating-points-v2 = <&llcc_bwmon_opp_table>;
2950
2951 llcc_bwmon_opp_table: opp-table {
2952 compatible = "operating-points-v2";
2953
2954 opp-0 {
2955 opp-peak-kBps = <1144000>;
2956 };
2957
2958 opp-1 {
2959 opp-peak-kBps = <1720000>;
2960 };
2961
2962 opp-2 {
2963 opp-peak-kBps = <2086000>;
2964 };
2965
2966 opp-3 {
2967 opp-peak-kBps = <2929000>;
2968 };
2969
2970 opp-4 {
2971 opp-peak-kBps = <3879000>;
2972 };
2973
2974 opp-5 {
2975 opp-peak-kBps = <5931000>;
2976 };
2977
2978 opp-6 {
2979 opp-peak-kBps = <6881000>;
2980 };
2981
2982 opp-7 {
2983 opp-peak-kBps = <8137000>;
2984 };
2985 };
2986 };
2987
2988 dc_noc: interconnect@9160000 {
2989 compatible = "qcom,sc7180-dc-noc";
2990 reg = <0 0x09160000 0 0x03200>;
2991 #interconnect-cells = <2>;
2992 qcom,bcm-voters = <&apps_bcm_voter>;
2993 };
2994
2995 system-cache-controller@9200000 {
2996 compatible = "qcom,sc7180-llcc";
2997 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2998 reg-names = "llcc0_base", "llcc_broadcast_base";
2999 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3000 };
3001
3002 gem_noc: interconnect@9680000 {
3003 compatible = "qcom,sc7180-gem-noc";
3004 reg = <0 0x09680000 0 0x3e200>;
3005 #interconnect-cells = <2>;
3006 qcom,bcm-voters = <&apps_bcm_voter>;
3007 };
3008
3009 npu_noc: interconnect@9990000 {
3010 compatible = "qcom,sc7180-npu-noc";
3011 reg = <0 0x09990000 0 0x1600>;
3012 #interconnect-cells = <2>;
3013 qcom,bcm-voters = <&apps_bcm_voter>;
3014 };
3015
3016 usb_1: usb@a6f8800 {
3017 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
3018 reg = <0 0x0a6f8800 0 0x400>;
3019 status = "disabled";
3020 #address-cells = <2>;
3021 #size-cells = <2>;
3022 ranges;
3023 dma-ranges;
3024
3025 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3026 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3027 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3028 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3029 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3030 clock-names = "cfg_noc",
3031 "core",
3032 "iface",
3033 "sleep",
3034 "mock_utmi";
3035
3036 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3037 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3038 assigned-clock-rates = <19200000>, <150000000>;
3039
3040 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3041 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3042 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3043 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3044 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3045 interrupt-names = "pwr_event",
3046 "hs_phy_irq",
3047 "dp_hs_phy_irq",
3048 "dm_hs_phy_irq",
3049 "ss_phy_irq";
3050
3051 power-domains = <&gcc USB30_PRIM_GDSC>;
3052 required-opps = <&rpmhpd_opp_nom>;
3053
3054 resets = <&gcc GCC_USB30_PRIM_BCR>;
3055
3056 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3057 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3058 interconnect-names = "usb-ddr", "apps-usb";
3059
3060 wakeup-source;
3061
3062 usb_1_dwc3: usb@a600000 {
3063 compatible = "snps,dwc3";
3064 reg = <0 0x0a600000 0 0xe000>;
3065 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3066 iommus = <&apps_smmu 0x540 0>;
3067 snps,dis_u2_susphy_quirk;
3068 snps,dis_enblslpm_quirk;
3069 snps,parkmode-disable-ss-quirk;
3070 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3071 phy-names = "usb2-phy", "usb3-phy";
3072 maximum-speed = "super-speed";
3073 };
3074 };
3075
3076 venus: video-codec@aa00000 {
3077 compatible = "qcom,sc7180-venus";
3078 reg = <0 0x0aa00000 0 0xff000>;
3079 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3080 power-domains = <&videocc VENUS_GDSC>,
3081 <&videocc VCODEC0_GDSC>,
3082 <&rpmhpd SC7180_CX>;
3083 power-domain-names = "venus", "vcodec0", "cx";
3084 operating-points-v2 = <&venus_opp_table>;
3085 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3086 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3087 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3088 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3089 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3090 clock-names = "core", "iface", "bus",
3091 "vcodec0_core", "vcodec0_bus";
3092 iommus = <&apps_smmu 0x0c00 0x60>;
3093 memory-region = <&venus_mem>;
3094 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3096 interconnect-names = "video-mem", "cpu-cfg";
3097
3098 video-decoder {
3099 compatible = "venus-decoder";
3100 };
3101
3102 video-encoder {
3103 compatible = "venus-encoder";
3104 };
3105
3106 venus_opp_table: opp-table {
3107 compatible = "operating-points-v2";
3108
3109 opp-150000000 {
3110 opp-hz = /bits/ 64 <150000000>;
3111 required-opps = <&rpmhpd_opp_low_svs>;
3112 };
3113
3114 opp-270000000 {
3115 opp-hz = /bits/ 64 <270000000>;
3116 required-opps = <&rpmhpd_opp_svs>;
3117 };
3118
3119 opp-340000000 {
3120 opp-hz = /bits/ 64 <340000000>;
3121 required-opps = <&rpmhpd_opp_svs_l1>;
3122 };
3123
3124 opp-434000000 {
3125 opp-hz = /bits/ 64 <434000000>;
3126 required-opps = <&rpmhpd_opp_nom>;
3127 };
3128
3129 opp-500000097 {
3130 opp-hz = /bits/ 64 <500000097>;
3131 required-opps = <&rpmhpd_opp_turbo>;
3132 };
3133 };
3134 };
3135
3136 videocc: clock-controller@ab00000 {
3137 compatible = "qcom,sc7180-videocc";
3138 reg = <0 0x0ab00000 0 0x10000>;
3139 clocks = <&rpmhcc RPMH_CXO_CLK>;
3140 clock-names = "bi_tcxo";
3141 #clock-cells = <1>;
3142 #reset-cells = <1>;
3143 #power-domain-cells = <1>;
3144 };
3145
3146 camnoc_virt: interconnect@ac00000 {
3147 compatible = "qcom,sc7180-camnoc-virt";
3148 reg = <0 0x0ac00000 0 0x1000>;
3149 #interconnect-cells = <2>;
3150 qcom,bcm-voters = <&apps_bcm_voter>;
3151 };
3152
3153 camcc: clock-controller@ad00000 {
3154 compatible = "qcom,sc7180-camcc";
3155 reg = <0 0x0ad00000 0 0x10000>;
3156 clocks = <&rpmhcc RPMH_CXO_CLK>,
3157 <&gcc GCC_CAMERA_AHB_CLK>,
3158 <&gcc GCC_CAMERA_XO_CLK>;
3159 clock-names = "bi_tcxo", "iface", "xo";
3160 #clock-cells = <1>;
3161 #reset-cells = <1>;
3162 #power-domain-cells = <1>;
3163 };
3164
3165 mdss: display-subsystem@ae00000 {
3166 compatible = "qcom,sc7180-mdss";
3167 reg = <0 0x0ae00000 0 0x1000>;
3168 reg-names = "mdss";
3169
3170 power-domains = <&dispcc MDSS_GDSC>;
3171
3172 clocks = <&gcc GCC_DISP_AHB_CLK>,
3173 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3174 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3175 clock-names = "iface", "ahb", "core";
3176
3177 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3178 interrupt-controller;
3179 #interrupt-cells = <1>;
3180
3181 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
3182 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3183 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3184 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
3185 interconnect-names = "mdp0-mem",
3186 "cpu-cfg";
3187
3188 iommus = <&apps_smmu 0x800 0x2>;
3189
3190 #address-cells = <2>;
3191 #size-cells = <2>;
3192 ranges;
3193
3194 status = "disabled";
3195
3196 mdp: display-controller@ae01000 {
3197 compatible = "qcom,sc7180-dpu";
3198 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0aeb0000 0 0x2008>;
3200 reg-names = "mdp", "vbif";
3201
3202 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3203 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3204 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3205 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3206 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3207 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3208 clock-names = "bus", "iface", "rot", "lut", "core",
3209 "vsync";
3210 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3211 <&dispcc DISP_CC_MDSS_ROT_CLK>,
3212 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3213 assigned-clock-rates = <19200000>,
3214 <19200000>,
3215 <19200000>;
3216 operating-points-v2 = <&mdp_opp_table>;
3217 power-domains = <&rpmhpd SC7180_CX>;
3218
3219 interrupt-parent = <&mdss>;
3220 interrupts = <0>;
3221
3222 ports {
3223 #address-cells = <1>;
3224 #size-cells = <0>;
3225
3226 port@0 {
3227 reg = <0>;
3228 dpu_intf1_out: endpoint {
3229 remote-endpoint = <&mdss_dsi0_in>;
3230 };
3231 };
3232
3233 port@2 {
3234 reg = <2>;
3235 dpu_intf0_out: endpoint {
3236 remote-endpoint = <&dp_in>;
3237 };
3238 };
3239 };
3240
3241 mdp_opp_table: opp-table {
3242 compatible = "operating-points-v2";
3243
3244 opp-200000000 {
3245 opp-hz = /bits/ 64 <200000000>;
3246 required-opps = <&rpmhpd_opp_low_svs>;
3247 };
3248
3249 opp-300000000 {
3250 opp-hz = /bits/ 64 <300000000>;
3251 required-opps = <&rpmhpd_opp_svs>;
3252 };
3253
3254 opp-345000000 {
3255 opp-hz = /bits/ 64 <345000000>;
3256 required-opps = <&rpmhpd_opp_svs_l1>;
3257 };
3258
3259 opp-460000000 {
3260 opp-hz = /bits/ 64 <460000000>;
3261 required-opps = <&rpmhpd_opp_nom>;
3262 };
3263 };
3264 };
3265
3266 mdss_dsi0: dsi@ae94000 {
3267 compatible = "qcom,sc7180-dsi-ctrl",
3268 "qcom,mdss-dsi-ctrl";
3269 reg = <0 0x0ae94000 0 0x400>;
3270 reg-names = "dsi_ctrl";
3271
3272 interrupt-parent = <&mdss>;
3273 interrupts = <4>;
3274
3275 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3276 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3277 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3278 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3279 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3280 <&gcc GCC_DISP_HF_AXI_CLK>;
3281 clock-names = "byte",
3282 "byte_intf",
3283 "pixel",
3284 "core",
3285 "iface",
3286 "bus";
3287
3288 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3289 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3290
3291 operating-points-v2 = <&dsi_opp_table>;
3292 power-domains = <&rpmhpd SC7180_CX>;
3293
3294 phys = <&mdss_dsi0_phy>;
3295
3296 #address-cells = <1>;
3297 #size-cells = <0>;
3298
3299 status = "disabled";
3300
3301 ports {
3302 #address-cells = <1>;
3303 #size-cells = <0>;
3304
3305 port@0 {
3306 reg = <0>;
3307 mdss_dsi0_in: endpoint {
3308 remote-endpoint = <&dpu_intf1_out>;
3309 };
3310 };
3311
3312 port@1 {
3313 reg = <1>;
3314 mdss_dsi0_out: endpoint {
3315 };
3316 };
3317 };
3318
3319 dsi_opp_table: opp-table {
3320 compatible = "operating-points-v2";
3321
3322 opp-187500000 {
3323 opp-hz = /bits/ 64 <187500000>;
3324 required-opps = <&rpmhpd_opp_low_svs>;
3325 };
3326
3327 opp-300000000 {
3328 opp-hz = /bits/ 64 <300000000>;
3329 required-opps = <&rpmhpd_opp_svs>;
3330 };
3331
3332 opp-358000000 {
3333 opp-hz = /bits/ 64 <358000000>;
3334 required-opps = <&rpmhpd_opp_svs_l1>;
3335 };
3336 };
3337 };
3338
3339 mdss_dsi0_phy: phy@ae94400 {
3340 compatible = "qcom,dsi-phy-10nm";
3341 reg = <0 0x0ae94400 0 0x200>,
3342 <0 0x0ae94600 0 0x280>,
3343 <0 0x0ae94a00 0 0x1e0>;
3344 reg-names = "dsi_phy",
3345 "dsi_phy_lane",
3346 "dsi_pll";
3347
3348 #clock-cells = <1>;
3349 #phy-cells = <0>;
3350
3351 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3352 <&rpmhcc RPMH_CXO_CLK>;
3353 clock-names = "iface", "ref";
3354
3355 status = "disabled";
3356 };
3357
3358 mdss_dp: displayport-controller@ae90000 {
3359 compatible = "qcom,sc7180-dp";
3360 status = "disabled";
3361
3362 reg = <0 0x0ae90000 0 0x200>,
3363 <0 0x0ae90200 0 0x200>,
3364 <0 0x0ae90400 0 0xc00>,
3365 <0 0x0ae91000 0 0x400>,
3366 <0 0x0ae91400 0 0x400>;
3367
3368 interrupt-parent = <&mdss>;
3369 interrupts = <12>;
3370
3371 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3372 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3373 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3374 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3375 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3376 clock-names = "core_iface", "core_aux", "ctrl_link",
3377 "ctrl_link_iface", "stream_pixel";
3378 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3379 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3380 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3381 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3382 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3383 phy-names = "dp";
3384
3385 operating-points-v2 = <&dp_opp_table>;
3386 power-domains = <&rpmhpd SC7180_CX>;
3387
3388 #sound-dai-cells = <0>;
3389
3390 ports {
3391 #address-cells = <1>;
3392 #size-cells = <0>;
3393 port@0 {
3394 reg = <0>;
3395 dp_in: endpoint {
3396 remote-endpoint = <&dpu_intf0_out>;
3397 };
3398 };
3399
3400 port@1 {
3401 reg = <1>;
3402 mdss_dp_out: endpoint { };
3403 };
3404 };
3405
3406 dp_opp_table: opp-table {
3407 compatible = "operating-points-v2";
3408
3409 opp-160000000 {
3410 opp-hz = /bits/ 64 <160000000>;
3411 required-opps = <&rpmhpd_opp_low_svs>;
3412 };
3413
3414 opp-270000000 {
3415 opp-hz = /bits/ 64 <270000000>;
3416 required-opps = <&rpmhpd_opp_svs>;
3417 };
3418
3419 opp-540000000 {
3420 opp-hz = /bits/ 64 <540000000>;
3421 required-opps = <&rpmhpd_opp_svs_l1>;
3422 };
3423
3424 opp-810000000 {
3425 opp-hz = /bits/ 64 <810000000>;
3426 required-opps = <&rpmhpd_opp_nom>;
3427 };
3428 };
3429 };
3430 };
3431
3432 dispcc: clock-controller@af00000 {
3433 compatible = "qcom,sc7180-dispcc";
3434 reg = <0 0x0af00000 0 0x200000>;
3435 clocks = <&rpmhcc RPMH_CXO_CLK>,
3436 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3437 <&mdss_dsi0_phy 0>,
3438 <&mdss_dsi0_phy 1>,
3439 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3440 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3441 clock-names = "bi_tcxo",
3442 "gcc_disp_gpll0_clk_src",
3443 "dsi0_phy_pll_out_byteclk",
3444 "dsi0_phy_pll_out_dsiclk",
3445 "dp_phy_pll_link_clk",
3446 "dp_phy_pll_vco_div_clk";
3447 #clock-cells = <1>;
3448 #reset-cells = <1>;
3449 #power-domain-cells = <1>;
3450 };
3451
3452 pdc: interrupt-controller@b220000 {
3453 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3454 reg = <0 0x0b220000 0 0x30000>;
3455 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3456 #interrupt-cells = <2>;
3457 interrupt-parent = <&intc>;
3458 interrupt-controller;
3459 };
3460
3461 pdc_reset: reset-controller@b2e0000 {
3462 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3463 reg = <0 0x0b2e0000 0 0x20000>;
3464 #reset-cells = <1>;
3465 };
3466
3467 tsens0: thermal-sensor@c263000 {
3468 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3469 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3470 <0 0x0c222000 0 0x1ff>; /* SROT */
3471 #qcom,sensors = <15>;
3472 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3474 interrupt-names = "uplow","critical";
3475 #thermal-sensor-cells = <1>;
3476 };
3477
3478 tsens1: thermal-sensor@c265000 {
3479 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3480 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3481 <0 0x0c223000 0 0x1ff>; /* SROT */
3482 #qcom,sensors = <10>;
3483 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3485 interrupt-names = "uplow","critical";
3486 #thermal-sensor-cells = <1>;
3487 };
3488
3489 aoss_reset: reset-controller@c2a0000 {
3490 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3491 reg = <0 0x0c2a0000 0 0x31000>;
3492 #reset-cells = <1>;
3493 };
3494
3495 aoss_qmp: power-management@c300000 {
3496 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3497 reg = <0 0x0c300000 0 0x400>;
3498 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3499 mboxes = <&apss_shared 0>;
3500
3501 #clock-cells = <0>;
3502 };
3503
3504 sram@c3f0000 {
3505 compatible = "qcom,rpmh-stats";
3506 reg = <0 0x0c3f0000 0 0x400>;
3507 };
3508
3509 spmi_bus: spmi@c440000 {
3510 compatible = "qcom,spmi-pmic-arb";
3511 reg = <0 0x0c440000 0 0x1100>,
3512 <0 0x0c600000 0 0x2000000>,
3513 <0 0x0e600000 0 0x100000>,
3514 <0 0x0e700000 0 0xa0000>,
3515 <0 0x0c40a000 0 0x26000>;
3516 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3517 interrupt-names = "periph_irq";
3518 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3519 qcom,ee = <0>;
3520 qcom,channel = <0>;
3521 #address-cells = <2>;
3522 #size-cells = <0>;
3523 interrupt-controller;
3524 #interrupt-cells = <4>;
3525 };
3526
3527 sram@146aa000 {
3528 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3529 reg = <0 0x146aa000 0 0x2000>;
3530
3531 #address-cells = <1>;
3532 #size-cells = <1>;
3533
3534 ranges = <0 0 0x146aa000 0x2000>;
3535
3536 pil-reloc@94c {
3537 compatible = "qcom,pil-reloc-info";
3538 reg = <0x94c 0xc8>;
3539 };
3540 };
3541
3542 apps_smmu: iommu@15000000 {
3543 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3544 reg = <0 0x15000000 0 0x100000>;
3545 #iommu-cells = <2>;
3546 #global-interrupts = <1>;
3547 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3628 };
3629
3630 intc: interrupt-controller@17a00000 {
3631 compatible = "arm,gic-v3";
3632 #address-cells = <2>;
3633 #size-cells = <2>;
3634 ranges;
3635 #interrupt-cells = <3>;
3636 interrupt-controller;
3637 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3638 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3639 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3640
3641 msi-controller@17a40000 {
3642 compatible = "arm,gic-v3-its";
3643 msi-controller;
3644 #msi-cells = <1>;
3645 reg = <0 0x17a40000 0 0x20000>;
3646 status = "disabled";
3647 };
3648 };
3649
3650 apss_shared: mailbox@17c00000 {
3651 compatible = "qcom,sc7180-apss-shared",
3652 "qcom,sdm845-apss-shared";
3653 reg = <0 0x17c00000 0 0x10000>;
3654 #mbox-cells = <1>;
3655 };
3656
3657 watchdog@17c10000 {
3658 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3659 reg = <0 0x17c10000 0 0x1000>;
3660 clocks = <&sleep_clk>;
3661 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3662 };
3663
3664 timer@17c20000 {
3665 #address-cells = <1>;
3666 #size-cells = <1>;
3667 ranges = <0 0 0 0x20000000>;
3668 compatible = "arm,armv7-timer-mem";
3669 reg = <0 0x17c20000 0 0x1000>;
3670
3671 frame@17c21000 {
3672 frame-number = <0>;
3673 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3675 reg = <0x17c21000 0x1000>,
3676 <0x17c22000 0x1000>;
3677 };
3678
3679 frame@17c23000 {
3680 frame-number = <1>;
3681 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3682 reg = <0x17c23000 0x1000>;
3683 status = "disabled";
3684 };
3685
3686 frame@17c25000 {
3687 frame-number = <2>;
3688 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3689 reg = <0x17c25000 0x1000>;
3690 status = "disabled";
3691 };
3692
3693 frame@17c27000 {
3694 frame-number = <3>;
3695 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3696 reg = <0x17c27000 0x1000>;
3697 status = "disabled";
3698 };
3699
3700 frame@17c29000 {
3701 frame-number = <4>;
3702 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3703 reg = <0x17c29000 0x1000>;
3704 status = "disabled";
3705 };
3706
3707 frame@17c2b000 {
3708 frame-number = <5>;
3709 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3710 reg = <0x17c2b000 0x1000>;
3711 status = "disabled";
3712 };
3713
3714 frame@17c2d000 {
3715 frame-number = <6>;
3716 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3717 reg = <0x17c2d000 0x1000>;
3718 status = "disabled";
3719 };
3720 };
3721
3722 apps_rsc: rsc@18200000 {
3723 compatible = "qcom,rpmh-rsc";
3724 reg = <0 0x18200000 0 0x10000>,
3725 <0 0x18210000 0 0x10000>,
3726 <0 0x18220000 0 0x10000>;
3727 reg-names = "drv-0", "drv-1", "drv-2";
3728 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3731 qcom,tcs-offset = <0xd00>;
3732 qcom,drv-id = <2>;
3733 qcom,tcs-config = <ACTIVE_TCS 2>,
3734 <SLEEP_TCS 3>,
3735 <WAKE_TCS 3>,
3736 <CONTROL_TCS 1>;
3737 power-domains = <&CLUSTER_PD>;
3738
3739 rpmhcc: clock-controller {
3740 compatible = "qcom,sc7180-rpmh-clk";
3741 clocks = <&xo_board>;
3742 clock-names = "xo";
3743 #clock-cells = <1>;
3744 };
3745
3746 rpmhpd: power-controller {
3747 compatible = "qcom,sc7180-rpmhpd";
3748 #power-domain-cells = <1>;
3749 operating-points-v2 = <&rpmhpd_opp_table>;
3750
3751 rpmhpd_opp_table: opp-table {
3752 compatible = "operating-points-v2";
3753
3754 rpmhpd_opp_ret: opp1 {
3755 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3756 };
3757
3758 rpmhpd_opp_min_svs: opp2 {
3759 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3760 };
3761
3762 rpmhpd_opp_low_svs: opp3 {
3763 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3764 };
3765
3766 rpmhpd_opp_svs: opp4 {
3767 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3768 };
3769
3770 rpmhpd_opp_svs_l1: opp5 {
3771 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3772 };
3773
3774 rpmhpd_opp_svs_l2: opp6 {
3775 opp-level = <224>;
3776 };
3777
3778 rpmhpd_opp_nom: opp7 {
3779 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3780 };
3781
3782 rpmhpd_opp_nom_l1: opp8 {
3783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3784 };
3785
3786 rpmhpd_opp_nom_l2: opp9 {
3787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3788 };
3789
3790 rpmhpd_opp_turbo: opp10 {
3791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3792 };
3793
3794 rpmhpd_opp_turbo_l1: opp11 {
3795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3796 };
3797 };
3798 };
3799
3800 apps_bcm_voter: bcm-voter {
3801 compatible = "qcom,bcm-voter";
3802 };
3803 };
3804
3805 osm_l3: interconnect@18321000 {
3806 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3807 reg = <0 0x18321000 0 0x1400>;
3808
3809 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3810 clock-names = "xo", "alternate";
3811
3812 #interconnect-cells = <1>;
3813 };
3814
3815 cpufreq_hw: cpufreq@18323000 {
3816 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3817 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3818 reg-names = "freq-domain0", "freq-domain1";
3819
3820 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3821 clock-names = "xo", "alternate";
3822
3823 #freq-domain-cells = <1>;
3824 #clock-cells = <1>;
3825 };
3826
3827 wifi: wifi@18800000 {
3828 compatible = "qcom,wcn3990-wifi";
3829 reg = <0 0x18800000 0 0x800000>;
3830 reg-names = "membase";
3831 iommus = <&apps_smmu 0xc0 0x1>;
3832 interrupts =
3833 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3834 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3835 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3836 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3837 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3838 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3839 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3840 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3841 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3842 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3843 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3844 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3845 memory-region = <&wlan_mem>;
3846 qcom,msa-fixed-perm;
3847 status = "disabled";
3848 };
3849
3850 remoteproc_adsp: remoteproc@62400000 {
3851 compatible = "qcom,sc7180-adsp-pas";
3852 reg = <0 0x62400000 0 0x100>;
3853
3854 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3855 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3856 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3857 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3858 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3859 interrupt-names = "wdog",
3860 "fatal",
3861 "ready",
3862 "handover",
3863 "stop-ack";
3864
3865 clocks = <&rpmhcc RPMH_CXO_CLK>;
3866 clock-names = "xo";
3867
3868 power-domains = <&rpmhpd SC7180_LCX>,
3869 <&rpmhpd SC7180_LMX>;
3870 power-domain-names = "lcx", "lmx";
3871
3872 qcom,qmp = <&aoss_qmp>;
3873 qcom,smem-states = <&adsp_smp2p_out 0>;
3874 qcom,smem-state-names = "stop";
3875
3876 status = "disabled";
3877
3878 glink-edge {
3879 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3880 label = "lpass";
3881 qcom,remote-pid = <2>;
3882 mboxes = <&apss_shared 8>;
3883
3884 apr {
3885 compatible = "qcom,apr-v2";
3886 qcom,glink-channels = "apr_audio_svc";
3887 qcom,domain = <APR_DOMAIN_ADSP>;
3888 #address-cells = <1>;
3889 #size-cells = <0>;
3890
3891 service@3 {
3892 compatible = "qcom,q6core";
3893 reg = <APR_SVC_ADSP_CORE>;
3894 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3895 };
3896
3897 q6afe: service@4 {
3898 compatible = "qcom,q6afe";
3899 reg = <APR_SVC_AFE>;
3900 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3901
3902 q6afedai: dais {
3903 compatible = "qcom,q6afe-dais";
3904 #address-cells = <1>;
3905 #size-cells = <0>;
3906 #sound-dai-cells = <1>;
3907 };
3908
3909 q6afecc: clock-controller {
3910 compatible = "qcom,q6afe-clocks";
3911 #clock-cells = <2>;
3912 };
3913 };
3914
3915 q6asm: service@7 {
3916 compatible = "qcom,q6asm";
3917 reg = <APR_SVC_ASM>;
3918 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3919
3920 q6asmdai: dais {
3921 compatible = "qcom,q6asm-dais";
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3924 #sound-dai-cells = <1>;
3925 iommus = <&apps_smmu 0x1001 0x0>;
3926 };
3927 };
3928
3929 q6adm: service@8 {
3930 compatible = "qcom,q6adm";
3931 reg = <APR_SVC_ADM>;
3932 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3933
3934 q6routing: routing {
3935 compatible = "qcom,q6adm-routing";
3936 #sound-dai-cells = <0>;
3937 };
3938 };
3939 };
3940
3941 fastrpc {
3942 compatible = "qcom,fastrpc";
3943 qcom,glink-channels = "fastrpcglink-apps-dsp";
3944 label = "adsp";
3945 #address-cells = <1>;
3946 #size-cells = <0>;
3947
3948 compute-cb@3 {
3949 compatible = "qcom,fastrpc-compute-cb";
3950 reg = <3>;
3951 iommus = <&apps_smmu 0x1003 0x0>;
3952 };
3953
3954 compute-cb@4 {
3955 compatible = "qcom,fastrpc-compute-cb";
3956 reg = <4>;
3957 iommus = <&apps_smmu 0x1004 0x0>;
3958 };
3959
3960 compute-cb@5 {
3961 compatible = "qcom,fastrpc-compute-cb";
3962 reg = <5>;
3963 iommus = <&apps_smmu 0x1005 0x0>;
3964 qcom,nsessions = <5>;
3965 };
3966 };
3967 };
3968 };
3969
3970 lpasscc: clock-controller@62d00000 {
3971 compatible = "qcom,sc7180-lpasscorecc";
3972 reg = <0 0x62d00000 0 0x50000>,
3973 <0 0x62780000 0 0x30000>;
3974 reg-names = "lpass_core_cc", "lpass_audio_cc";
3975 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3976 <&rpmhcc RPMH_CXO_CLK>;
3977 clock-names = "iface", "bi_tcxo";
3978 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3979 #clock-cells = <1>;
3980 #power-domain-cells = <1>;
3981
3982 status = "reserved"; /* Controlled by ADSP */
3983 };
3984
3985 lpass_cpu: lpass@62d87000 {
3986 compatible = "qcom,sc7180-lpass-cpu";
3987
3988 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3989 reg-names = "lpass-hdmiif", "lpass-lpaif";
3990
3991 iommus = <&apps_smmu 0x1020 0>,
3992 <&apps_smmu 0x1021 0>,
3993 <&apps_smmu 0x1032 0>;
3994
3995 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3996 required-opps = <&rpmhpd_opp_nom>;
3997
3998 status = "disabled";
3999
4000 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4001 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
4002 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
4003 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
4004 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
4005 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
4006
4007 clock-names = "pcnoc-sway-clk", "audio-core",
4008 "mclk0", "pcnoc-mport-clk",
4009 "mi2s-bit-clk0", "mi2s-bit-clk1";
4010
4011
4012 #sound-dai-cells = <1>;
4013 #address-cells = <1>;
4014 #size-cells = <0>;
4015
4016 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4017 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
4018 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
4019 };
4020
4021 lpass_hm: clock-controller@63000000 {
4022 compatible = "qcom,sc7180-lpasshm";
4023 reg = <0 0x63000000 0 0x28>;
4024 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
4025 <&rpmhcc RPMH_CXO_CLK>;
4026 clock-names = "iface", "bi_tcxo";
4027 power-domains = <&rpmhpd SC7180_CX>;
4028
4029 #clock-cells = <1>;
4030 #power-domain-cells = <1>;
4031
4032 status = "reserved"; /* Controlled by ADSP */
4033 };
4034 };
4035
4036 thermal-zones {
4037 cpu0_thermal: cpu0-thermal {
4038 polling-delay-passive = <250>;
4039
4040 thermal-sensors = <&tsens0 1>;
4041 sustainable-power = <1052>;
4042
4043 trips {
4044 cpu0_alert0: trip-point0 {
4045 temperature = <90000>;
4046 hysteresis = <2000>;
4047 type = "passive";
4048 };
4049
4050 cpu0_alert1: trip-point1 {
4051 temperature = <95000>;
4052 hysteresis = <2000>;
4053 type = "passive";
4054 };
4055
4056 cpu0_crit: cpu-crit {
4057 temperature = <110000>;
4058 hysteresis = <1000>;
4059 type = "critical";
4060 };
4061 };
4062
4063 cooling-maps {
4064 map0 {
4065 trip = <&cpu0_alert0>;
4066 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4068 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4069 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4070 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4071 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072 };
4073 map1 {
4074 trip = <&cpu0_alert1>;
4075 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4077 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4078 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4080 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4081 };
4082 };
4083 };
4084
4085 cpu1_thermal: cpu1-thermal {
4086 polling-delay-passive = <250>;
4087
4088 thermal-sensors = <&tsens0 2>;
4089 sustainable-power = <1052>;
4090
4091 trips {
4092 cpu1_alert0: trip-point0 {
4093 temperature = <90000>;
4094 hysteresis = <2000>;
4095 type = "passive";
4096 };
4097
4098 cpu1_alert1: trip-point1 {
4099 temperature = <95000>;
4100 hysteresis = <2000>;
4101 type = "passive";
4102 };
4103
4104 cpu1_crit: cpu-crit {
4105 temperature = <110000>;
4106 hysteresis = <1000>;
4107 type = "critical";
4108 };
4109 };
4110
4111 cooling-maps {
4112 map0 {
4113 trip = <&cpu1_alert0>;
4114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4115 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4116 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4117 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4118 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4119 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4120 };
4121 map1 {
4122 trip = <&cpu1_alert1>;
4123 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4124 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4125 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129 };
4130 };
4131 };
4132
4133 cpu2_thermal: cpu2-thermal {
4134 polling-delay-passive = <250>;
4135
4136 thermal-sensors = <&tsens0 3>;
4137 sustainable-power = <1052>;
4138
4139 trips {
4140 cpu2_alert0: trip-point0 {
4141 temperature = <90000>;
4142 hysteresis = <2000>;
4143 type = "passive";
4144 };
4145
4146 cpu2_alert1: trip-point1 {
4147 temperature = <95000>;
4148 hysteresis = <2000>;
4149 type = "passive";
4150 };
4151
4152 cpu2_crit: cpu-crit {
4153 temperature = <110000>;
4154 hysteresis = <1000>;
4155 type = "critical";
4156 };
4157 };
4158
4159 cooling-maps {
4160 map0 {
4161 trip = <&cpu2_alert0>;
4162 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4163 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4164 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4165 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4166 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4167 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168 };
4169 map1 {
4170 trip = <&cpu2_alert1>;
4171 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4173 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4174 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4176 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4177 };
4178 };
4179 };
4180
4181 cpu3_thermal: cpu3-thermal {
4182 polling-delay-passive = <250>;
4183
4184 thermal-sensors = <&tsens0 4>;
4185 sustainable-power = <1052>;
4186
4187 trips {
4188 cpu3_alert0: trip-point0 {
4189 temperature = <90000>;
4190 hysteresis = <2000>;
4191 type = "passive";
4192 };
4193
4194 cpu3_alert1: trip-point1 {
4195 temperature = <95000>;
4196 hysteresis = <2000>;
4197 type = "passive";
4198 };
4199
4200 cpu3_crit: cpu-crit {
4201 temperature = <110000>;
4202 hysteresis = <1000>;
4203 type = "critical";
4204 };
4205 };
4206
4207 cooling-maps {
4208 map0 {
4209 trip = <&cpu3_alert0>;
4210 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4211 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4212 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4213 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4216 };
4217 map1 {
4218 trip = <&cpu3_alert1>;
4219 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4220 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4224 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4225 };
4226 };
4227 };
4228
4229 cpu4_thermal: cpu4-thermal {
4230 polling-delay-passive = <250>;
4231
4232 thermal-sensors = <&tsens0 5>;
4233 sustainable-power = <1052>;
4234
4235 trips {
4236 cpu4_alert0: trip-point0 {
4237 temperature = <90000>;
4238 hysteresis = <2000>;
4239 type = "passive";
4240 };
4241
4242 cpu4_alert1: trip-point1 {
4243 temperature = <95000>;
4244 hysteresis = <2000>;
4245 type = "passive";
4246 };
4247
4248 cpu4_crit: cpu-crit {
4249 temperature = <110000>;
4250 hysteresis = <1000>;
4251 type = "critical";
4252 };
4253 };
4254
4255 cooling-maps {
4256 map0 {
4257 trip = <&cpu4_alert0>;
4258 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4261 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4262 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4264 };
4265 map1 {
4266 trip = <&cpu4_alert1>;
4267 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4268 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4269 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4273 };
4274 };
4275 };
4276
4277 cpu5_thermal: cpu5-thermal {
4278 polling-delay-passive = <250>;
4279
4280 thermal-sensors = <&tsens0 6>;
4281 sustainable-power = <1052>;
4282
4283 trips {
4284 cpu5_alert0: trip-point0 {
4285 temperature = <90000>;
4286 hysteresis = <2000>;
4287 type = "passive";
4288 };
4289
4290 cpu5_alert1: trip-point1 {
4291 temperature = <95000>;
4292 hysteresis = <2000>;
4293 type = "passive";
4294 };
4295
4296 cpu5_crit: cpu-crit {
4297 temperature = <110000>;
4298 hysteresis = <1000>;
4299 type = "critical";
4300 };
4301 };
4302
4303 cooling-maps {
4304 map0 {
4305 trip = <&cpu5_alert0>;
4306 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4307 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4308 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312 };
4313 map1 {
4314 trip = <&cpu5_alert1>;
4315 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4317 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4318 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4319 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4320 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4321 };
4322 };
4323 };
4324
4325 cpu6_thermal: cpu6-thermal {
4326 polling-delay-passive = <250>;
4327
4328 thermal-sensors = <&tsens0 9>;
4329 sustainable-power = <1425>;
4330
4331 trips {
4332 cpu6_alert0: trip-point0 {
4333 temperature = <90000>;
4334 hysteresis = <2000>;
4335 type = "passive";
4336 };
4337
4338 cpu6_alert1: trip-point1 {
4339 temperature = <95000>;
4340 hysteresis = <2000>;
4341 type = "passive";
4342 };
4343
4344 cpu6_crit: cpu-crit {
4345 temperature = <110000>;
4346 hysteresis = <1000>;
4347 type = "critical";
4348 };
4349 };
4350
4351 cooling-maps {
4352 map0 {
4353 trip = <&cpu6_alert0>;
4354 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356 };
4357 map1 {
4358 trip = <&cpu6_alert1>;
4359 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4361 };
4362 };
4363 };
4364
4365 cpu7_thermal: cpu7-thermal {
4366 polling-delay-passive = <250>;
4367
4368 thermal-sensors = <&tsens0 10>;
4369 sustainable-power = <1425>;
4370
4371 trips {
4372 cpu7_alert0: trip-point0 {
4373 temperature = <90000>;
4374 hysteresis = <2000>;
4375 type = "passive";
4376 };
4377
4378 cpu7_alert1: trip-point1 {
4379 temperature = <95000>;
4380 hysteresis = <2000>;
4381 type = "passive";
4382 };
4383
4384 cpu7_crit: cpu-crit {
4385 temperature = <110000>;
4386 hysteresis = <1000>;
4387 type = "critical";
4388 };
4389 };
4390
4391 cooling-maps {
4392 map0 {
4393 trip = <&cpu7_alert0>;
4394 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4395 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4396 };
4397 map1 {
4398 trip = <&cpu7_alert1>;
4399 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4400 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4401 };
4402 };
4403 };
4404
4405 cpu8_thermal: cpu8-thermal {
4406 polling-delay-passive = <250>;
4407
4408 thermal-sensors = <&tsens0 11>;
4409 sustainable-power = <1425>;
4410
4411 trips {
4412 cpu8_alert0: trip-point0 {
4413 temperature = <90000>;
4414 hysteresis = <2000>;
4415 type = "passive";
4416 };
4417
4418 cpu8_alert1: trip-point1 {
4419 temperature = <95000>;
4420 hysteresis = <2000>;
4421 type = "passive";
4422 };
4423
4424 cpu8_crit: cpu-crit {
4425 temperature = <110000>;
4426 hysteresis = <1000>;
4427 type = "critical";
4428 };
4429 };
4430
4431 cooling-maps {
4432 map0 {
4433 trip = <&cpu8_alert0>;
4434 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4435 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4436 };
4437 map1 {
4438 trip = <&cpu8_alert1>;
4439 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4440 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4441 };
4442 };
4443 };
4444
4445 cpu9_thermal: cpu9-thermal {
4446 polling-delay-passive = <250>;
4447
4448 thermal-sensors = <&tsens0 12>;
4449 sustainable-power = <1425>;
4450
4451 trips {
4452 cpu9_alert0: trip-point0 {
4453 temperature = <90000>;
4454 hysteresis = <2000>;
4455 type = "passive";
4456 };
4457
4458 cpu9_alert1: trip-point1 {
4459 temperature = <95000>;
4460 hysteresis = <2000>;
4461 type = "passive";
4462 };
4463
4464 cpu9_crit: cpu-crit {
4465 temperature = <110000>;
4466 hysteresis = <1000>;
4467 type = "critical";
4468 };
4469 };
4470
4471 cooling-maps {
4472 map0 {
4473 trip = <&cpu9_alert0>;
4474 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4476 };
4477 map1 {
4478 trip = <&cpu9_alert1>;
4479 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4480 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4481 };
4482 };
4483 };
4484
4485 aoss0-thermal {
4486 polling-delay-passive = <250>;
4487
4488 thermal-sensors = <&tsens0 0>;
4489
4490 trips {
4491 aoss0_alert0: trip-point0 {
4492 temperature = <90000>;
4493 hysteresis = <2000>;
4494 type = "hot";
4495 };
4496
4497 aoss0_crit: aoss0-crit {
4498 temperature = <110000>;
4499 hysteresis = <2000>;
4500 type = "critical";
4501 };
4502 };
4503 };
4504
4505 cpuss0-thermal {
4506 polling-delay-passive = <250>;
4507
4508 thermal-sensors = <&tsens0 7>;
4509
4510 trips {
4511 cpuss0_alert0: trip-point0 {
4512 temperature = <90000>;
4513 hysteresis = <2000>;
4514 type = "hot";
4515 };
4516 cpuss0_crit: cluster0-crit {
4517 temperature = <110000>;
4518 hysteresis = <2000>;
4519 type = "critical";
4520 };
4521 };
4522 };
4523
4524 cpuss1-thermal {
4525 polling-delay-passive = <250>;
4526
4527 thermal-sensors = <&tsens0 8>;
4528
4529 trips {
4530 cpuss1_alert0: trip-point0 {
4531 temperature = <90000>;
4532 hysteresis = <2000>;
4533 type = "hot";
4534 };
4535 cpuss1_crit: cluster0-crit {
4536 temperature = <110000>;
4537 hysteresis = <2000>;
4538 type = "critical";
4539 };
4540 };
4541 };
4542
4543 gpuss0-thermal {
4544 polling-delay-passive = <250>;
4545
4546 thermal-sensors = <&tsens0 13>;
4547
4548 trips {
4549 gpuss0_alert0: trip-point0 {
4550 temperature = <95000>;
4551 hysteresis = <2000>;
4552 type = "passive";
4553 };
4554
4555 gpuss0_crit: gpuss0-crit {
4556 temperature = <110000>;
4557 hysteresis = <2000>;
4558 type = "critical";
4559 };
4560 };
4561
4562 cooling-maps {
4563 map0 {
4564 trip = <&gpuss0_alert0>;
4565 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4566 };
4567 };
4568 };
4569
4570 gpuss1-thermal {
4571 polling-delay-passive = <250>;
4572
4573 thermal-sensors = <&tsens0 14>;
4574
4575 trips {
4576 gpuss1_alert0: trip-point0 {
4577 temperature = <95000>;
4578 hysteresis = <2000>;
4579 type = "passive";
4580 };
4581
4582 gpuss1_crit: gpuss1-crit {
4583 temperature = <110000>;
4584 hysteresis = <2000>;
4585 type = "critical";
4586 };
4587 };
4588
4589 cooling-maps {
4590 map0 {
4591 trip = <&gpuss1_alert0>;
4592 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593 };
4594 };
4595 };
4596
4597 aoss1-thermal {
4598 polling-delay-passive = <250>;
4599
4600 thermal-sensors = <&tsens1 0>;
4601
4602 trips {
4603 aoss1_alert0: trip-point0 {
4604 temperature = <90000>;
4605 hysteresis = <2000>;
4606 type = "hot";
4607 };
4608
4609 aoss1_crit: aoss1-crit {
4610 temperature = <110000>;
4611 hysteresis = <2000>;
4612 type = "critical";
4613 };
4614 };
4615 };
4616
4617 cwlan-thermal {
4618 polling-delay-passive = <250>;
4619
4620 thermal-sensors = <&tsens1 1>;
4621
4622 trips {
4623 cwlan_alert0: trip-point0 {
4624 temperature = <90000>;
4625 hysteresis = <2000>;
4626 type = "hot";
4627 };
4628
4629 cwlan_crit: cwlan-crit {
4630 temperature = <110000>;
4631 hysteresis = <2000>;
4632 type = "critical";
4633 };
4634 };
4635 };
4636
4637 audio-thermal {
4638 polling-delay-passive = <250>;
4639
4640 thermal-sensors = <&tsens1 2>;
4641
4642 trips {
4643 audio_alert0: trip-point0 {
4644 temperature = <90000>;
4645 hysteresis = <2000>;
4646 type = "hot";
4647 };
4648
4649 audio_crit: audio-crit {
4650 temperature = <110000>;
4651 hysteresis = <2000>;
4652 type = "critical";
4653 };
4654 };
4655 };
4656
4657 ddr-thermal {
4658 polling-delay-passive = <250>;
4659
4660 thermal-sensors = <&tsens1 3>;
4661
4662 trips {
4663 ddr_alert0: trip-point0 {
4664 temperature = <90000>;
4665 hysteresis = <2000>;
4666 type = "hot";
4667 };
4668
4669 ddr_crit: ddr-crit {
4670 temperature = <110000>;
4671 hysteresis = <2000>;
4672 type = "critical";
4673 };
4674 };
4675 };
4676
4677 q6-hvx-thermal {
4678 polling-delay-passive = <250>;
4679
4680 thermal-sensors = <&tsens1 4>;
4681
4682 trips {
4683 q6_hvx_alert0: trip-point0 {
4684 temperature = <90000>;
4685 hysteresis = <2000>;
4686 type = "hot";
4687 };
4688
4689 q6_hvx_crit: q6-hvx-crit {
4690 temperature = <110000>;
4691 hysteresis = <2000>;
4692 type = "critical";
4693 };
4694 };
4695 };
4696
4697 camera-thermal {
4698 polling-delay-passive = <250>;
4699
4700 thermal-sensors = <&tsens1 5>;
4701
4702 trips {
4703 camera_alert0: trip-point0 {
4704 temperature = <90000>;
4705 hysteresis = <2000>;
4706 type = "hot";
4707 };
4708
4709 camera_crit: camera-crit {
4710 temperature = <110000>;
4711 hysteresis = <2000>;
4712 type = "critical";
4713 };
4714 };
4715 };
4716
4717 mdm-core-thermal {
4718 polling-delay-passive = <250>;
4719
4720 thermal-sensors = <&tsens1 6>;
4721
4722 trips {
4723 mdm_alert0: trip-point0 {
4724 temperature = <90000>;
4725 hysteresis = <2000>;
4726 type = "hot";
4727 };
4728
4729 mdm_crit: mdm-crit {
4730 temperature = <110000>;
4731 hysteresis = <2000>;
4732 type = "critical";
4733 };
4734 };
4735 };
4736
4737 mdm-dsp-thermal {
4738 polling-delay-passive = <250>;
4739
4740 thermal-sensors = <&tsens1 7>;
4741
4742 trips {
4743 mdm_dsp_alert0: trip-point0 {
4744 temperature = <90000>;
4745 hysteresis = <2000>;
4746 type = "hot";
4747 };
4748
4749 mdm_dsp_crit: mdm-dsp-crit {
4750 temperature = <110000>;
4751 hysteresis = <2000>;
4752 type = "critical";
4753 };
4754 };
4755 };
4756
4757 npu-thermal {
4758 polling-delay-passive = <250>;
4759
4760 thermal-sensors = <&tsens1 8>;
4761
4762 trips {
4763 npu_alert0: trip-point0 {
4764 temperature = <90000>;
4765 hysteresis = <2000>;
4766 type = "hot";
4767 };
4768
4769 npu_crit: npu-crit {
4770 temperature = <110000>;
4771 hysteresis = <2000>;
4772 type = "critical";
4773 };
4774 };
4775 };
4776
4777 video-thermal {
4778 polling-delay-passive = <250>;
4779
4780 thermal-sensors = <&tsens1 9>;
4781
4782 trips {
4783 video_alert0: trip-point0 {
4784 temperature = <90000>;
4785 hysteresis = <2000>;
4786 type = "hot";
4787 };
4788
4789 video_crit: video-crit {
4790 temperature = <110000>;
4791 hysteresis = <2000>;
4792 type = "critical";
4793 };
4794 };
4795 };
4796 };
4797
4798 timer {
4799 compatible = "arm,armv8-timer";
4800 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4801 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4802 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4803 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4804 };
4805 };
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