1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23
24 / {
25 interrupt-parent = <&intc>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29
30 clocks {
31 xo_board_clk: xo-board-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32764>;
40 };
41 };
42
43 cpus {
44 #address-cells = <2>;
45 #size-cells = <0>;
46
47 CPU0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a78c";
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
52 enable-method = "psci";
53 capacity-dmips-mhz = <981>;
54 dynamic-power-coefficient = <549>;
55 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 operating-points-v2 = <&cpu0_opp_table>;
60 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
61 #cooling-cells = <2>;
62 L2_0: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
68 compatible = "cache";
69 cache-level = <3>;
70 cache-unified;
71 };
72 };
73 };
74
75 CPU1: cpu@100 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a78c";
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci";
81 capacity-dmips-mhz = <981>;
82 dynamic-power-coefficient = <549>;
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
88 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
89 #cooling-cells = <2>;
90 L2_100: l2-cache {
91 compatible = "cache";
92 cache-level = <2>;
93 cache-unified;
94 next-level-cache = <&L3_0>;
95 };
96 };
97
98 CPU2: cpu@200 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a78c";
101 reg = <0x0 0x200>;
102 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <981>;
105 dynamic-power-coefficient = <549>;
106 next-level-cache = <&L2_200>;
107 power-domains = <&CPU_PD2>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
112 #cooling-cells = <2>;
113 L2_200: l2-cache {
114 compatible = "cache";
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&L3_0>;
118 };
119 };
120
121 CPU3: cpu@300 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a78c";
124 reg = <0x0 0x300>;
125 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci";
127 capacity-dmips-mhz = <981>;
128 dynamic-power-coefficient = <549>;
129 next-level-cache = <&L2_300>;
130 power-domains = <&CPU_PD3>;
131 power-domain-names = "psci";
132 qcom,freq-domain = <&cpufreq_hw 0>;
133 operating-points-v2 = <&cpu0_opp_table>;
134 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
135 #cooling-cells = <2>;
136 L2_300: l2-cache {
137 compatible = "cache";
138 cache-level = <2>;
139 cache-unified;
140 next-level-cache = <&L3_0>;
141 };
142 };
143
144 CPU4: cpu@400 {
145 device_type = "cpu";
146 compatible = "arm,cortex-x1c";
147 reg = <0x0 0x400>;
148 clocks = <&cpufreq_hw 1>;
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 dynamic-power-coefficient = <590>;
152 next-level-cache = <&L2_400>;
153 power-domains = <&CPU_PD4>;
154 power-domain-names = "psci";
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = <&cpu4_opp_table>;
157 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
158 #cooling-cells = <2>;
159 L2_400: l2-cache {
160 compatible = "cache";
161 cache-level = <2>;
162 cache-unified;
163 next-level-cache = <&L3_0>;
164 };
165 };
166
167 CPU5: cpu@500 {
168 device_type = "cpu";
169 compatible = "arm,cortex-x1c";
170 reg = <0x0 0x500>;
171 clocks = <&cpufreq_hw 1>;
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
174 dynamic-power-coefficient = <590>;
175 next-level-cache = <&L2_500>;
176 power-domains = <&CPU_PD5>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 #cooling-cells = <2>;
182 L2_500: l2-cache {
183 compatible = "cache";
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&L3_0>;
187 };
188 };
189
190 CPU6: cpu@600 {
191 device_type = "cpu";
192 compatible = "arm,cortex-x1c";
193 reg = <0x0 0x600>;
194 clocks = <&cpufreq_hw 1>;
195 enable-method = "psci";
196 capacity-dmips-mhz = <1024>;
197 dynamic-power-coefficient = <590>;
198 next-level-cache = <&L2_600>;
199 power-domains = <&CPU_PD6>;
200 power-domain-names = "psci";
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
204 #cooling-cells = <2>;
205 L2_600: l2-cache {
206 compatible = "cache";
207 cache-level = <2>;
208 cache-unified;
209 next-level-cache = <&L3_0>;
210 };
211 };
212
213 CPU7: cpu@700 {
214 device_type = "cpu";
215 compatible = "arm,cortex-x1c";
216 reg = <0x0 0x700>;
217 clocks = <&cpufreq_hw 1>;
218 enable-method = "psci";
219 capacity-dmips-mhz = <1024>;
220 dynamic-power-coefficient = <590>;
221 next-level-cache = <&L2_700>;
222 power-domains = <&CPU_PD7>;
223 power-domain-names = "psci";
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
227 #cooling-cells = <2>;
228 L2_700: l2-cache {
229 compatible = "cache";
230 cache-level = <2>;
231 cache-unified;
232 next-level-cache = <&L3_0>;
233 };
234 };
235
236 cpu-map {
237 cluster0 {
238 core0 {
239 cpu = <&CPU0>;
240 };
241
242 core1 {
243 cpu = <&CPU1>;
244 };
245
246 core2 {
247 cpu = <&CPU2>;
248 };
249
250 core3 {
251 cpu = <&CPU3>;
252 };
253
254 core4 {
255 cpu = <&CPU4>;
256 };
257
258 core5 {
259 cpu = <&CPU5>;
260 };
261
262 core6 {
263 cpu = <&CPU6>;
264 };
265
266 core7 {
267 cpu = <&CPU7>;
268 };
269 };
270 };
271
272 idle-states {
273 entry-method = "psci";
274
275 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
276 compatible = "arm,idle-state";
277 idle-state-name = "little-rail-power-collapse";
278 arm,psci-suspend-param = <0x40000004>;
279 entry-latency-us = <355>;
280 exit-latency-us = <909>;
281 min-residency-us = <3934>;
282 local-timer-stop;
283 };
284
285 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
286 compatible = "arm,idle-state";
287 idle-state-name = "big-rail-power-collapse";
288 arm,psci-suspend-param = <0x40000004>;
289 entry-latency-us = <241>;
290 exit-latency-us = <1461>;
291 min-residency-us = <4488>;
292 local-timer-stop;
293 };
294 };
295
296 domain-idle-states {
297 CLUSTER_SLEEP_0: cluster-sleep-0 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x4100c344>;
300 entry-latency-us = <3263>;
301 exit-latency-us = <6562>;
302 min-residency-us = <9987>;
303 };
304 };
305 };
306
307 firmware {
308 scm: scm {
309 compatible = "qcom,scm-sc8280xp", "qcom,scm";
310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
311 qcom,dload-mode = <&tcsr 0x13000>;
312 };
313 };
314
315 aggre1_noc: interconnect-aggre1-noc {
316 compatible = "qcom,sc8280xp-aggre1-noc";
317 #interconnect-cells = <2>;
318 qcom,bcm-voters = <&apps_bcm_voter>;
319 };
320
321 aggre2_noc: interconnect-aggre2-noc {
322 compatible = "qcom,sc8280xp-aggre2-noc";
323 #interconnect-cells = <2>;
324 qcom,bcm-voters = <&apps_bcm_voter>;
325 };
326
327 clk_virt: interconnect-clk-virt {
328 compatible = "qcom,sc8280xp-clk-virt";
329 #interconnect-cells = <2>;
330 qcom,bcm-voters = <&apps_bcm_voter>;
331 };
332
333 config_noc: interconnect-config-noc {
334 compatible = "qcom,sc8280xp-config-noc";
335 #interconnect-cells = <2>;
336 qcom,bcm-voters = <&apps_bcm_voter>;
337 };
338
339 dc_noc: interconnect-dc-noc {
340 compatible = "qcom,sc8280xp-dc-noc";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
343 };
344
345 gem_noc: interconnect-gem-noc {
346 compatible = "qcom,sc8280xp-gem-noc";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
349 };
350
351 lpass_noc: interconnect-lpass-ag-noc {
352 compatible = "qcom,sc8280xp-lpass-ag-noc";
353 #interconnect-cells = <2>;
354 qcom,bcm-voters = <&apps_bcm_voter>;
355 };
356
357 mc_virt: interconnect-mc-virt {
358 compatible = "qcom,sc8280xp-mc-virt";
359 #interconnect-cells = <2>;
360 qcom,bcm-voters = <&apps_bcm_voter>;
361 };
362
363 mmss_noc: interconnect-mmss-noc {
364 compatible = "qcom,sc8280xp-mmss-noc";
365 #interconnect-cells = <2>;
366 qcom,bcm-voters = <&apps_bcm_voter>;
367 };
368
369 nspa_noc: interconnect-nspa-noc {
370 compatible = "qcom,sc8280xp-nspa-noc";
371 #interconnect-cells = <2>;
372 qcom,bcm-voters = <&apps_bcm_voter>;
373 };
374
375 nspb_noc: interconnect-nspb-noc {
376 compatible = "qcom,sc8280xp-nspb-noc";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
379 };
380
381 system_noc: interconnect-system-noc {
382 compatible = "qcom,sc8280xp-system-noc";
383 #interconnect-cells = <2>;
384 qcom,bcm-voters = <&apps_bcm_voter>;
385 };
386
387 memory@80000000 {
388 device_type = "memory";
389 /* We expect the bootloader to fill in the size */
390 reg = <0x0 0x80000000 0x0 0x0>;
391 };
392
393 cpu0_opp_table: opp-table-cpu0 {
394 compatible = "operating-points-v2";
395 opp-shared;
396
397 opp-300000000 {
398 opp-hz = /bits/ 64 <300000000>;
399 opp-peak-kBps = <(300000 * 32)>;
400 };
401 opp-403200000 {
402 opp-hz = /bits/ 64 <403200000>;
403 opp-peak-kBps = <(384000 * 32)>;
404 };
405 opp-499200000 {
406 opp-hz = /bits/ 64 <499200000>;
407 opp-peak-kBps = <(480000 * 32)>;
408 };
409 opp-595200000 {
410 opp-hz = /bits/ 64 <595200000>;
411 opp-peak-kBps = <(576000 * 32)>;
412 };
413 opp-691200000 {
414 opp-hz = /bits/ 64 <691200000>;
415 opp-peak-kBps = <(672000 * 32)>;
416 };
417 opp-806400000 {
418 opp-hz = /bits/ 64 <806400000>;
419 opp-peak-kBps = <(768000 * 32)>;
420 };
421 opp-902400000 {
422 opp-hz = /bits/ 64 <902400000>;
423 opp-peak-kBps = <(864000 * 32)>;
424 };
425 opp-1017600000 {
426 opp-hz = /bits/ 64 <1017600000>;
427 opp-peak-kBps = <(960000 * 32)>;
428 };
429 opp-1113600000 {
430 opp-hz = /bits/ 64 <1113600000>;
431 opp-peak-kBps = <(1075200 * 32)>;
432 };
433 opp-1209600000 {
434 opp-hz = /bits/ 64 <1209600000>;
435 opp-peak-kBps = <(1171200 * 32)>;
436 };
437 opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <(1267200 * 32)>;
440 };
441 opp-1440000000 {
442 opp-hz = /bits/ 64 <1440000000>;
443 opp-peak-kBps = <(1363200 * 32)>;
444 };
445 opp-1555200000 {
446 opp-hz = /bits/ 64 <1555200000>;
447 opp-peak-kBps = <(1536000 * 32)>;
448 };
449 opp-1670400000 {
450 opp-hz = /bits/ 64 <1670400000>;
451 opp-peak-kBps = <(1612800 * 32)>;
452 };
453 opp-1785600000 {
454 opp-hz = /bits/ 64 <1785600000>;
455 opp-peak-kBps = <(1689600 * 32)>;
456 };
457 opp-1881600000 {
458 opp-hz = /bits/ 64 <1881600000>;
459 opp-peak-kBps = <(1689600 * 32)>;
460 };
461 opp-1996800000 {
462 opp-hz = /bits/ 64 <1996800000>;
463 opp-peak-kBps = <(1689600 * 32)>;
464 };
465 opp-2112000000 {
466 opp-hz = /bits/ 64 <2112000000>;
467 opp-peak-kBps = <(1689600 * 32)>;
468 };
469 opp-2227200000 {
470 opp-hz = /bits/ 64 <2227200000>;
471 opp-peak-kBps = <(1689600 * 32)>;
472 };
473 opp-2342400000 {
474 opp-hz = /bits/ 64 <2342400000>;
475 opp-peak-kBps = <(1689600 * 32)>;
476 };
477 opp-2438400000 {
478 opp-hz = /bits/ 64 <2438400000>;
479 opp-peak-kBps = <(1689600 * 32)>;
480 };
481 };
482
483 cpu4_opp_table: opp-table-cpu4 {
484 compatible = "operating-points-v2";
485 opp-shared;
486
487 opp-825600000 {
488 opp-hz = /bits/ 64 <825600000>;
489 opp-peak-kBps = <(768000 * 32)>;
490 };
491 opp-940800000 {
492 opp-hz = /bits/ 64 <940800000>;
493 opp-peak-kBps = <(864000 * 32)>;
494 };
495 opp-1056000000 {
496 opp-hz = /bits/ 64 <1056000000>;
497 opp-peak-kBps = <(960000 * 32)>;
498 };
499 opp-1171200000 {
500 opp-hz = /bits/ 64 <1171200000>;
501 opp-peak-kBps = <(1171200 * 32)>;
502 };
503 opp-1286400000 {
504 opp-hz = /bits/ 64 <1286400000>;
505 opp-peak-kBps = <(1267200 * 32)>;
506 };
507 opp-1401600000 {
508 opp-hz = /bits/ 64 <1401600000>;
509 opp-peak-kBps = <(1363200 * 32)>;
510 };
511 opp-1516800000 {
512 opp-hz = /bits/ 64 <1516800000>;
513 opp-peak-kBps = <(1459200 * 32)>;
514 };
515 opp-1632000000 {
516 opp-hz = /bits/ 64 <1632000000>;
517 opp-peak-kBps = <(1612800 * 32)>;
518 };
519 opp-1747200000 {
520 opp-hz = /bits/ 64 <1747200000>;
521 opp-peak-kBps = <(1689600 * 32)>;
522 };
523 opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <(1689600 * 32)>;
526 };
527 opp-1977600000 {
528 opp-hz = /bits/ 64 <1977600000>;
529 opp-peak-kBps = <(1689600 * 32)>;
530 };
531 opp-2073600000 {
532 opp-hz = /bits/ 64 <2073600000>;
533 opp-peak-kBps = <(1689600 * 32)>;
534 };
535 opp-2169600000 {
536 opp-hz = /bits/ 64 <2169600000>;
537 opp-peak-kBps = <(1689600 * 32)>;
538 };
539 opp-2284800000 {
540 opp-hz = /bits/ 64 <2284800000>;
541 opp-peak-kBps = <(1689600 * 32)>;
542 };
543 opp-2400000000 {
544 opp-hz = /bits/ 64 <2400000000>;
545 opp-peak-kBps = <(1689600 * 32)>;
546 };
547 opp-2496000000 {
548 opp-hz = /bits/ 64 <2496000000>;
549 opp-peak-kBps = <(1689600 * 32)>;
550 };
551 opp-2592000000 {
552 opp-hz = /bits/ 64 <2592000000>;
553 opp-peak-kBps = <(1689600 * 32)>;
554 };
555 opp-2688000000 {
556 opp-hz = /bits/ 64 <2688000000>;
557 opp-peak-kBps = <(1689600 * 32)>;
558 };
559 opp-2803200000 {
560 opp-hz = /bits/ 64 <2803200000>;
561 opp-peak-kBps = <(1689600 * 32)>;
562 };
563 opp-2899200000 {
564 opp-hz = /bits/ 64 <2899200000>;
565 opp-peak-kBps = <(1689600 * 32)>;
566 };
567 opp-2995200000 {
568 opp-hz = /bits/ 64 <2995200000>;
569 opp-peak-kBps = <(1689600 * 32)>;
570 };
571 };
572
573 qup_opp_table_100mhz: opp-table-qup100mhz {
574 compatible = "operating-points-v2";
575
576 opp-75000000 {
577 opp-hz = /bits/ 64 <75000000>;
578 required-opps = <&rpmhpd_opp_low_svs>;
579 };
580
581 opp-100000000 {
582 opp-hz = /bits/ 64 <100000000>;
583 required-opps = <&rpmhpd_opp_svs>;
584 };
585 };
586
587 pmu {
588 compatible = "arm,armv8-pmuv3";
589 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
590 };
591
592 psci {
593 compatible = "arm,psci-1.0";
594 method = "smc";
595
596 CPU_PD0: power-domain-cpu0 {
597 #power-domain-cells = <0>;
598 power-domains = <&CLUSTER_PD>;
599 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
600 };
601
602 CPU_PD1: power-domain-cpu1 {
603 #power-domain-cells = <0>;
604 power-domains = <&CLUSTER_PD>;
605 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
606 };
607
608 CPU_PD2: power-domain-cpu2 {
609 #power-domain-cells = <0>;
610 power-domains = <&CLUSTER_PD>;
611 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
612 };
613
614 CPU_PD3: power-domain-cpu3 {
615 #power-domain-cells = <0>;
616 power-domains = <&CLUSTER_PD>;
617 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
618 };
619
620 CPU_PD4: power-domain-cpu4 {
621 #power-domain-cells = <0>;
622 power-domains = <&CLUSTER_PD>;
623 domain-idle-states = <&BIG_CPU_SLEEP_0>;
624 };
625
626 CPU_PD5: power-domain-cpu5 {
627 #power-domain-cells = <0>;
628 power-domains = <&CLUSTER_PD>;
629 domain-idle-states = <&BIG_CPU_SLEEP_0>;
630 };
631
632 CPU_PD6: power-domain-cpu6 {
633 #power-domain-cells = <0>;
634 power-domains = <&CLUSTER_PD>;
635 domain-idle-states = <&BIG_CPU_SLEEP_0>;
636 };
637
638 CPU_PD7: power-domain-cpu7 {
639 #power-domain-cells = <0>;
640 power-domains = <&CLUSTER_PD>;
641 domain-idle-states = <&BIG_CPU_SLEEP_0>;
642 };
643
644 CLUSTER_PD: power-domain-cpu-cluster0 {
645 #power-domain-cells = <0>;
646 domain-idle-states = <&CLUSTER_SLEEP_0>;
647 };
648 };
649
650 reserved-memory {
651 #address-cells = <2>;
652 #size-cells = <2>;
653 ranges;
654
655 reserved-region@80000000 {
656 reg = <0 0x80000000 0 0x860000>;
657 no-map;
658 };
659
660 cmd_db: cmd-db-region@80860000 {
661 compatible = "qcom,cmd-db";
662 reg = <0 0x80860000 0 0x20000>;
663 no-map;
664 };
665
666 reserved-region@80880000 {
667 reg = <0 0x80880000 0 0x80000>;
668 no-map;
669 };
670
671 smem_mem: smem-region@80900000 {
672 compatible = "qcom,smem";
673 reg = <0 0x80900000 0 0x200000>;
674 no-map;
675 hwlocks = <&tcsr_mutex 3>;
676 };
677
678 reserved-region@80b00000 {
679 reg = <0 0x80b00000 0 0x100000>;
680 no-map;
681 };
682
683 reserved-region@83b00000 {
684 reg = <0 0x83b00000 0 0x1700000>;
685 no-map;
686 };
687
688 reserved-region@85b00000 {
689 reg = <0 0x85b00000 0 0xc00000>;
690 no-map;
691 };
692
693 pil_adsp_mem: adsp-region@86c00000 {
694 reg = <0 0x86c00000 0 0x2000000>;
695 no-map;
696 };
697
698 pil_nsp0_mem: cdsp0-region@8a100000 {
699 reg = <0 0x8a100000 0 0x1e00000>;
700 no-map;
701 };
702
703 pil_nsp1_mem: cdsp1-region@8c600000 {
704 reg = <0 0x8c600000 0 0x1e00000>;
705 no-map;
706 };
707
708 reserved-region@aeb00000 {
709 reg = <0 0xaeb00000 0 0x16600000>;
710 no-map;
711 };
712 };
713
714 smp2p-adsp {
715 compatible = "qcom,smp2p";
716 qcom,smem = <443>, <429>;
717 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
718 IPCC_MPROC_SIGNAL_SMP2P
719 IRQ_TYPE_EDGE_RISING>;
720 mboxes = <&ipcc IPCC_CLIENT_LPASS
721 IPCC_MPROC_SIGNAL_SMP2P>;
722
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <2>;
725
726 smp2p_adsp_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
729 };
730
731 smp2p_adsp_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
735 };
736 };
737
738 smp2p-nsp0 {
739 compatible = "qcom,smp2p";
740 qcom,smem = <94>, <432>;
741 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
742 IPCC_MPROC_SIGNAL_SMP2P
743 IRQ_TYPE_EDGE_RISING>;
744 mboxes = <&ipcc IPCC_CLIENT_CDSP
745 IPCC_MPROC_SIGNAL_SMP2P>;
746
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <5>;
749
750 smp2p_nsp0_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
753 };
754
755 smp2p_nsp0_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
759 };
760 };
761
762 smp2p-nsp1 {
763 compatible = "qcom,smp2p";
764 qcom,smem = <617>, <616>;
765 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
766 IPCC_MPROC_SIGNAL_SMP2P
767 IRQ_TYPE_EDGE_RISING>;
768 mboxes = <&ipcc IPCC_CLIENT_NSP1
769 IPCC_MPROC_SIGNAL_SMP2P>;
770
771 qcom,local-pid = <0>;
772 qcom,remote-pid = <12>;
773
774 smp2p_nsp1_out: master-kernel {
775 qcom,entry-name = "master-kernel";
776 #qcom,smem-state-cells = <1>;
777 };
778
779 smp2p_nsp1_in: slave-kernel {
780 qcom,entry-name = "slave-kernel";
781 interrupt-controller;
782 #interrupt-cells = <2>;
783 };
784 };
785
786 soc: soc@0 {
787 compatible = "simple-bus";
788 #address-cells = <2>;
789 #size-cells = <2>;
790 ranges = <0 0 0 0 0x10 0>;
791 dma-ranges = <0 0 0 0 0x10 0>;
792
793 ethernet0: ethernet@20000 {
794 compatible = "qcom,sc8280xp-ethqos";
795 reg = <0x0 0x00020000 0x0 0x10000>,
796 <0x0 0x00036000 0x0 0x100>;
797 reg-names = "stmmaceth", "rgmii";
798
799 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801 <&gcc GCC_EMAC0_PTP_CLK>,
802 <&gcc GCC_EMAC0_RGMII_CLK>;
803 clock-names = "stmmaceth",
804 "pclk",
805 "ptp_ref",
806 "rgmii";
807
808 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "macirq", "eth_lpi";
811
812 iommus = <&apps_smmu 0x4c0 0xf>;
813 power-domains = <&gcc EMAC_0_GDSC>;
814
815 snps,tso;
816 snps,pbl = <32>;
817 rx-fifo-depth = <4096>;
818 tx-fifo-depth = <4096>;
819
820 status = "disabled";
821 };
822
823 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc-sc8280xp";
825 reg = <0x0 0x00100000 0x0 0x1f0000>;
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #power-domain-cells = <1>;
829 clocks = <&rpmhcc RPMH_CXO_CLK>,
830 <&sleep_clk>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
836 <0>,
837 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
838 <0>,
839 <0>,
840 <0>,
841 <0>,
842 <0>,
843 <0>,
844 <0>,
845 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
846 <0>,
847 <0>,
848 <0>,
849 <0>,
850 <0>,
851 <0>,
852 <0>,
853 <0>,
854 <0>,
855 <&pcie2a_phy>,
856 <&pcie2b_phy>,
857 <&pcie3a_phy>,
858 <&pcie3b_phy>,
859 <&pcie4_phy>,
860 <0>,
861 <0>;
862 power-domains = <&rpmhpd SC8280XP_CX>;
863 };
864
865 ipcc: mailbox@408000 {
866 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
867 reg = <0 0x00408000 0 0x1000>;
868 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller;
870 #interrupt-cells = <3>;
871 #mbox-cells = <2>;
872 };
873
874 qfprom: efuse@784000 {
875 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
876 reg = <0 0x00784000 0 0x3000>;
877 #address-cells = <1>;
878 #size-cells = <1>;
879
880 gpu_speed_bin: gpu-speed-bin@18b {
881 reg = <0x18b 0x1>;
882 bits = <5 3>;
883 };
884 };
885
886 qup2: geniqup@8c0000 {
887 compatible = "qcom,geni-se-qup";
888 reg = <0 0x008c0000 0 0x2000>;
889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
891 clock-names = "m-ahb", "s-ahb";
892 iommus = <&apps_smmu 0xa3 0>;
893
894 #address-cells = <2>;
895 #size-cells = <2>;
896 ranges;
897
898 status = "disabled";
899
900 i2c16: i2c@880000 {
901 compatible = "qcom,geni-i2c";
902 reg = <0 0x00880000 0 0x4000>;
903 #address-cells = <1>;
904 #size-cells = <0>;
905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
906 clock-names = "se";
907 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains = <&rpmhpd SC8280XP_CX>;
909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
912 interconnect-names = "qup-core", "qup-config", "qup-memory";
913 status = "disabled";
914 };
915
916 spi16: spi@880000 {
917 compatible = "qcom,geni-spi";
918 reg = <0 0x00880000 0 0x4000>;
919 #address-cells = <1>;
920 #size-cells = <0>;
921 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
922 clock-names = "se";
923 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
924 power-domains = <&rpmhpd SC8280XP_CX>;
925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
928 interconnect-names = "qup-core", "qup-config", "qup-memory";
929 status = "disabled";
930 };
931
932 i2c17: i2c@884000 {
933 compatible = "qcom,geni-i2c";
934 reg = <0 0x00884000 0 0x4000>;
935 #address-cells = <1>;
936 #size-cells = <0>;
937 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
938 clock-names = "se";
939 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
940 power-domains = <&rpmhpd SC8280XP_CX>;
941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
944 interconnect-names = "qup-core", "qup-config", "qup-memory";
945 status = "disabled";
946 };
947
948 spi17: spi@884000 {
949 compatible = "qcom,geni-spi";
950 reg = <0 0x00884000 0 0x4000>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
954 clock-names = "se";
955 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
956 power-domains = <&rpmhpd SC8280XP_CX>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disabled";
962 };
963
964 uart17: serial@884000 {
965 compatible = "qcom,geni-uart";
966 reg = <0 0x00884000 0 0x4000>;
967 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
968 clock-names = "se";
969 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
970 operating-points-v2 = <&qup_opp_table_100mhz>;
971 power-domains = <&rpmhpd SC8280XP_CX>;
972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
974 interconnect-names = "qup-core", "qup-config";
975 status = "disabled";
976 };
977
978 i2c18: i2c@888000 {
979 compatible = "qcom,geni-i2c";
980 reg = <0 0x00888000 0 0x4000>;
981 #address-cells = <1>;
982 #size-cells = <0>;
983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
984 clock-names = "se";
985 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
986 power-domains = <&rpmhpd SC8280XP_CX>;
987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
990 interconnect-names = "qup-core", "qup-config", "qup-memory";
991 status = "disabled";
992 };
993
994 spi18: spi@888000 {
995 compatible = "qcom,geni-spi";
996 reg = <0 0x00888000 0 0x4000>;
997 #address-cells = <1>;
998 #size-cells = <0>;
999 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1000 clock-names = "se";
1001 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1002 power-domains = <&rpmhpd SC8280XP_CX>;
1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1006 interconnect-names = "qup-core", "qup-config", "qup-memory";
1007 status = "disabled";
1008 };
1009
1010 i2c19: i2c@88c000 {
1011 compatible = "qcom,geni-i2c";
1012 reg = <0 0x0088c000 0 0x4000>;
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1016 clock-names = "se";
1017 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1018 power-domains = <&rpmhpd SC8280XP_CX>;
1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1020 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1021 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 interconnect-names = "qup-core", "qup-config", "qup-memory";
1023 status = "disabled";
1024 };
1025
1026 spi19: spi@88c000 {
1027 compatible = "qcom,geni-spi";
1028 reg = <0 0x0088c000 0 0x4000>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1032 clock-names = "se";
1033 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1034 power-domains = <&rpmhpd SC8280XP_CX>;
1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1038 interconnect-names = "qup-core", "qup-config", "qup-memory";
1039 status = "disabled";
1040 };
1041
1042 i2c20: i2c@890000 {
1043 compatible = "qcom,geni-i2c";
1044 reg = <0 0x00890000 0 0x4000>;
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1048 clock-names = "se";
1049 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1050 power-domains = <&rpmhpd SC8280XP_CX>;
1051 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1053 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1054 interconnect-names = "qup-core", "qup-config", "qup-memory";
1055 status = "disabled";
1056 };
1057
1058 spi20: spi@890000 {
1059 compatible = "qcom,geni-spi";
1060 reg = <0 0x00890000 0 0x4000>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1064 clock-names = "se";
1065 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1066 power-domains = <&rpmhpd SC8280XP_CX>;
1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 interconnect-names = "qup-core", "qup-config", "qup-memory";
1071 status = "disabled";
1072 };
1073
1074 i2c21: i2c@894000 {
1075 compatible = "qcom,geni-i2c";
1076 reg = <0 0x00894000 0 0x4000>;
1077 clock-names = "se";
1078 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1079 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 power-domains = <&rpmhpd SC8280XP_CX>;
1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1087 status = "disabled";
1088 };
1089
1090 spi21: spi@894000 {
1091 compatible = "qcom,geni-spi";
1092 reg = <0 0x00894000 0 0x4000>;
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1095 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1096 clock-names = "se";
1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains = <&rpmhpd SC8280XP_CX>;
1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1100 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1101 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1102 interconnect-names = "qup-core", "qup-config", "qup-memory";
1103 status = "disabled";
1104 };
1105
1106 i2c22: i2c@898000 {
1107 compatible = "qcom,geni-i2c";
1108 reg = <0 0x00898000 0 0x4000>;
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 clock-names = "se";
1112 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1113 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1114 power-domains = <&rpmhpd SC8280XP_CX>;
1115 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1117 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1118 interconnect-names = "qup-core", "qup-config", "qup-memory";
1119 status = "disabled";
1120 };
1121
1122 spi22: spi@898000 {
1123 compatible = "qcom,geni-spi";
1124 reg = <0 0x00898000 0 0x4000>;
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1127 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1128 clock-names = "se";
1129 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1130 power-domains = <&rpmhpd SC8280XP_CX>;
1131 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1133 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1134 interconnect-names = "qup-core", "qup-config", "qup-memory";
1135 status = "disabled";
1136 };
1137
1138 i2c23: i2c@89c000 {
1139 compatible = "qcom,geni-i2c";
1140 reg = <0 0x0089c000 0 0x4000>;
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 clock-names = "se";
1144 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1145 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1146 power-domains = <&rpmhpd SC8280XP_CX>;
1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1148 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1150 interconnect-names = "qup-core", "qup-config", "qup-memory";
1151 status = "disabled";
1152 };
1153
1154 spi23: spi@89c000 {
1155 compatible = "qcom,geni-spi";
1156 reg = <0 0x0089c000 0 0x4000>;
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1160 clock-names = "se";
1161 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1162 power-domains = <&rpmhpd SC8280XP_CX>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1165 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1166 interconnect-names = "qup-core", "qup-config", "qup-memory";
1167 status = "disabled";
1168 };
1169 };
1170
1171 qup0: geniqup@9c0000 {
1172 compatible = "qcom,geni-se-qup";
1173 reg = <0 0x009c0000 0 0x6000>;
1174 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1176 clock-names = "m-ahb", "s-ahb";
1177 iommus = <&apps_smmu 0x563 0>;
1178
1179 #address-cells = <2>;
1180 #size-cells = <2>;
1181 ranges;
1182
1183 status = "disabled";
1184
1185 i2c0: i2c@980000 {
1186 compatible = "qcom,geni-i2c";
1187 reg = <0 0x00980000 0 0x4000>;
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190 clock-names = "se";
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1192 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1193 power-domains = <&rpmhpd SC8280XP_CX>;
1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1196 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1197 interconnect-names = "qup-core", "qup-config", "qup-memory";
1198 status = "disabled";
1199 };
1200
1201 spi0: spi@980000 {
1202 compatible = "qcom,geni-spi";
1203 reg = <0 0x00980000 0 0x4000>;
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1207 clock-names = "se";
1208 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains = <&rpmhpd SC8280XP_CX>;
1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1212 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1213 interconnect-names = "qup-core", "qup-config", "qup-memory";
1214 status = "disabled";
1215 };
1216
1217 i2c1: i2c@984000 {
1218 compatible = "qcom,geni-i2c";
1219 reg = <0 0x00984000 0 0x4000>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 clock-names = "se";
1223 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1224 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1225 power-domains = <&rpmhpd SC8280XP_CX>;
1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1228 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1229 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 status = "disabled";
1231 };
1232
1233 spi1: spi@984000 {
1234 compatible = "qcom,geni-spi";
1235 reg = <0 0x00984000 0 0x4000>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1239 clock-names = "se";
1240 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1241 power-domains = <&rpmhpd SC8280XP_CX>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1246 status = "disabled";
1247 };
1248
1249 i2c2: i2c@988000 {
1250 compatible = "qcom,geni-i2c";
1251 reg = <0 0x00988000 0 0x4000>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 clock-names = "se";
1255 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1256 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1257 power-domains = <&rpmhpd SC8280XP_CX>;
1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1260 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 interconnect-names = "qup-core", "qup-config", "qup-memory";
1262 status = "disabled";
1263 };
1264
1265 spi2: spi@988000 {
1266 compatible = "qcom,geni-spi";
1267 reg = <0 0x00988000 0 0x4000>;
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1270 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1271 clock-names = "se";
1272 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains = <&rpmhpd SC8280XP_CX>;
1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1276 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1277 interconnect-names = "qup-core", "qup-config", "qup-memory";
1278 status = "disabled";
1279 };
1280
1281 uart2: serial@988000 {
1282 compatible = "qcom,geni-uart";
1283 reg = <0 0x00988000 0 0x4000>;
1284 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1285 clock-names = "se";
1286 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287 operating-points-v2 = <&qup_opp_table_100mhz>;
1288 power-domains = <&rpmhpd SC8280XP_CX>;
1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1291 interconnect-names = "qup-core", "qup-config";
1292 status = "disabled";
1293 };
1294
1295 i2c3: i2c@98c000 {
1296 compatible = "qcom,geni-i2c";
1297 reg = <0 0x0098c000 0 0x4000>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1300 clock-names = "se";
1301 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1302 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303 power-domains = <&rpmhpd SC8280XP_CX>;
1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1307 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308 status = "disabled";
1309 };
1310
1311 spi3: spi@98c000 {
1312 compatible = "qcom,geni-spi";
1313 reg = <0 0x0098c000 0 0x4000>;
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1316 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1317 clock-names = "se";
1318 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1319 power-domains = <&rpmhpd SC8280XP_CX>;
1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1322 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 status = "disabled";
1325 };
1326
1327 i2c4: i2c@990000 {
1328 compatible = "qcom,geni-i2c";
1329 reg = <0 0x00990000 0 0x4000>;
1330 clock-names = "se";
1331 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1332 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1335 power-domains = <&rpmhpd SC8280XP_CX>;
1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1339 interconnect-names = "qup-core", "qup-config", "qup-memory";
1340 status = "disabled";
1341 };
1342
1343 spi4: spi@990000 {
1344 compatible = "qcom,geni-spi";
1345 reg = <0 0x00990000 0 0x4000>;
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1348 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1349 clock-names = "se";
1350 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1351 power-domains = <&rpmhpd SC8280XP_CX>;
1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356 status = "disabled";
1357 };
1358
1359 i2c5: i2c@994000 {
1360 compatible = "qcom,geni-i2c";
1361 reg = <0 0x00994000 0 0x4000>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 clock-names = "se";
1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1366 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1367 power-domains = <&rpmhpd SC8280XP_CX>;
1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1370 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 status = "disabled";
1373 };
1374
1375 spi5: spi@994000 {
1376 compatible = "qcom,geni-spi";
1377 reg = <0 0x00994000 0 0x4000>;
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1381 clock-names = "se";
1382 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1383 power-domains = <&rpmhpd SC8280XP_CX>;
1384 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1386 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1387 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 status = "disabled";
1389 };
1390
1391 i2c6: i2c@998000 {
1392 compatible = "qcom,geni-i2c";
1393 reg = <0 0x00998000 0 0x4000>;
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 clock-names = "se";
1397 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399 power-domains = <&rpmhpd SC8280XP_CX>;
1400 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1402 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404 status = "disabled";
1405 };
1406
1407 spi6: spi@998000 {
1408 compatible = "qcom,geni-spi";
1409 reg = <0 0x00998000 0 0x4000>;
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1412 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1413 clock-names = "se";
1414 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1415 power-domains = <&rpmhpd SC8280XP_CX>;
1416 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1418 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1419 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 status = "disabled";
1421 };
1422
1423 i2c7: i2c@99c000 {
1424 compatible = "qcom,geni-i2c";
1425 reg = <0 0x0099c000 0 0x4000>;
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 clock-names = "se";
1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1430 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1431 power-domains = <&rpmhpd SC8280XP_CX>;
1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1434 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1435 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436 status = "disabled";
1437 };
1438
1439 spi7: spi@99c000 {
1440 compatible = "qcom,geni-spi";
1441 reg = <0 0x0099c000 0 0x4000>;
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1444 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1445 clock-names = "se";
1446 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447 power-domains = <&rpmhpd SC8280XP_CX>;
1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1449 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1450 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1451 interconnect-names = "qup-core", "qup-config", "qup-memory";
1452 status = "disabled";
1453 };
1454 };
1455
1456 qup1: geniqup@ac0000 {
1457 compatible = "qcom,geni-se-qup";
1458 reg = <0 0x00ac0000 0 0x6000>;
1459 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1461 clock-names = "m-ahb", "s-ahb";
1462 iommus = <&apps_smmu 0x83 0>;
1463
1464 #address-cells = <2>;
1465 #size-cells = <2>;
1466 ranges;
1467
1468 status = "disabled";
1469
1470 i2c8: i2c@a80000 {
1471 compatible = "qcom,geni-i2c";
1472 reg = <0 0x00a80000 0 0x4000>;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1475 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1476 clock-names = "se";
1477 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1478 power-domains = <&rpmhpd SC8280XP_CX>;
1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1482 interconnect-names = "qup-core", "qup-config", "qup-memory";
1483 status = "disabled";
1484 };
1485
1486 spi8: spi@a80000 {
1487 compatible = "qcom,geni-spi";
1488 reg = <0 0x00a80000 0 0x4000>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1492 clock-names = "se";
1493 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1494 power-domains = <&rpmhpd SC8280XP_CX>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499 status = "disabled";
1500 };
1501
1502 i2c9: i2c@a84000 {
1503 compatible = "qcom,geni-i2c";
1504 reg = <0 0x00a84000 0 0x4000>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1507 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1508 clock-names = "se";
1509 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1510 power-domains = <&rpmhpd SC8280XP_CX>;
1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515 status = "disabled";
1516 };
1517
1518 spi9: spi@a84000 {
1519 compatible = "qcom,geni-spi";
1520 reg = <0 0x00a84000 0 0x4000>;
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1523 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1524 clock-names = "se";
1525 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526 power-domains = <&rpmhpd SC8280XP_CX>;
1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1530 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 status = "disabled";
1532 };
1533
1534 i2c10: i2c@a88000 {
1535 compatible = "qcom,geni-i2c";
1536 reg = <0 0x00a88000 0 0x4000>;
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1539 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1540 clock-names = "se";
1541 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1542 power-domains = <&rpmhpd SC8280XP_CX>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 status = "disabled";
1548 };
1549
1550 spi10: spi@a88000 {
1551 compatible = "qcom,geni-spi";
1552 reg = <0 0x00a88000 0 0x4000>;
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1555 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1556 clock-names = "se";
1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1558 power-domains = <&rpmhpd SC8280XP_CX>;
1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1562 interconnect-names = "qup-core", "qup-config", "qup-memory";
1563 status = "disabled";
1564 };
1565
1566 i2c11: i2c@a8c000 {
1567 compatible = "qcom,geni-i2c";
1568 reg = <0 0x00a8c000 0 0x4000>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1572 clock-names = "se";
1573 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574 power-domains = <&rpmhpd SC8280XP_CX>;
1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1576 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1577 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1578 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 status = "disabled";
1580 };
1581
1582 spi11: spi@a8c000 {
1583 compatible = "qcom,geni-spi";
1584 reg = <0 0x00a8c000 0 0x4000>;
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1587 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1588 clock-names = "se";
1589 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1590 power-domains = <&rpmhpd SC8280XP_CX>;
1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1593 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595 status = "disabled";
1596 };
1597
1598 i2c12: i2c@a90000 {
1599 compatible = "qcom,geni-i2c";
1600 reg = <0 0x00a90000 0 0x4000>;
1601 #address-cells = <1>;
1602 #size-cells = <0>;
1603 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1604 clock-names = "se";
1605 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1606 power-domains = <&rpmhpd SC8280XP_CX>;
1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1610 interconnect-names = "qup-core", "qup-config", "qup-memory";
1611 status = "disabled";
1612 };
1613
1614 spi12: spi@a90000 {
1615 compatible = "qcom,geni-spi";
1616 reg = <0 0x00a90000 0 0x4000>;
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1619 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1620 clock-names = "se";
1621 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1622 power-domains = <&rpmhpd SC8280XP_CX>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1625 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 status = "disabled";
1628 };
1629
1630 i2c13: i2c@a94000 {
1631 compatible = "qcom,geni-i2c";
1632 reg = <0 0x00a94000 0 0x4000>;
1633 #address-cells = <1>;
1634 #size-cells = <0>;
1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1636 clock-names = "se";
1637 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638 power-domains = <&rpmhpd SC8280XP_CX>;
1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1641 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 interconnect-names = "qup-core", "qup-config", "qup-memory";
1643 status = "disabled";
1644 };
1645
1646 spi13: spi@a94000 {
1647 compatible = "qcom,geni-spi";
1648 reg = <0 0x00a94000 0 0x4000>;
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1652 clock-names = "se";
1653 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654 power-domains = <&rpmhpd SC8280XP_CX>;
1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1656 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1657 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1658 interconnect-names = "qup-core", "qup-config", "qup-memory";
1659 status = "disabled";
1660 };
1661
1662 i2c14: i2c@a98000 {
1663 compatible = "qcom,geni-i2c";
1664 reg = <0 0x00a98000 0 0x4000>;
1665 #address-cells = <1>;
1666 #size-cells = <0>;
1667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1668 clock-names = "se";
1669 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1670 power-domains = <&rpmhpd SC8280XP_CX>;
1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1673 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1674 interconnect-names = "qup-core", "qup-config", "qup-memory";
1675 status = "disabled";
1676 };
1677
1678 spi14: spi@a98000 {
1679 compatible = "qcom,geni-spi";
1680 reg = <0 0x00a98000 0 0x4000>;
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1684 clock-names = "se";
1685 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1686 power-domains = <&rpmhpd SC8280XP_CX>;
1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1688 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1689 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1690 interconnect-names = "qup-core", "qup-config", "qup-memory";
1691 status = "disabled";
1692 };
1693
1694 i2c15: i2c@a9c000 {
1695 compatible = "qcom,geni-i2c";
1696 reg = <0 0x00a9c000 0 0x4000>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1699 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1700 clock-names = "se";
1701 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1702 power-domains = <&rpmhpd SC8280XP_CX>;
1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1705 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 status = "disabled";
1708 };
1709
1710 spi15: spi@a9c000 {
1711 compatible = "qcom,geni-spi";
1712 reg = <0 0x00a9c000 0 0x4000>;
1713 #address-cells = <1>;
1714 #size-cells = <0>;
1715 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1716 clock-names = "se";
1717 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1718 power-domains = <&rpmhpd SC8280XP_CX>;
1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1720 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1721 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1722 interconnect-names = "qup-core", "qup-config", "qup-memory";
1723 status = "disabled";
1724 };
1725 };
1726
1727 rng: rng@10d3000 {
1728 compatible = "qcom,prng-ee";
1729 reg = <0 0x010d3000 0 0x1000>;
1730 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1731 clock-names = "core";
1732 };
1733
1734 pcie4: pcie@1c00000 {
1735 device_type = "pci";
1736 compatible = "qcom,pcie-sc8280xp";
1737 reg = <0x0 0x01c00000 0x0 0x3000>,
1738 <0x0 0x30000000 0x0 0xf1d>,
1739 <0x0 0x30000f20 0x0 0xa8>,
1740 <0x0 0x30001000 0x0 0x1000>,
1741 <0x0 0x30100000 0x0 0x100000>,
1742 <0x0 0x01c03000 0x0 0x1000>;
1743 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1744 #address-cells = <3>;
1745 #size-cells = <2>;
1746 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1747 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1748 bus-range = <0x00 0xff>;
1749
1750 dma-coherent;
1751
1752 linux,pci-domain = <6>;
1753 num-lanes = <1>;
1754
1755 msi-map = <0x0 &its 0xe0000 0x10000>;
1756
1757 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1761 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1762
1763 #interrupt-cells = <1>;
1764 interrupt-map-mask = <0 0 0 0x7>;
1765 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1766 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1767 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1768 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1769
1770 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1779 clock-names = "aux",
1780 "cfg",
1781 "bus_master",
1782 "bus_slave",
1783 "slave_q2a",
1784 "ddrss_sf_tbu",
1785 "noc_aggr_4",
1786 "noc_aggr_south_sf",
1787 "cnoc_qx";
1788
1789 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1790 assigned-clock-rates = <19200000>;
1791
1792 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1793 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1794 interconnect-names = "pcie-mem", "cpu-pcie";
1795
1796 resets = <&gcc GCC_PCIE_4_BCR>;
1797 reset-names = "pci";
1798
1799 power-domains = <&gcc PCIE_4_GDSC>;
1800 required-opps = <&rpmhpd_opp_nom>;
1801
1802 phys = <&pcie4_phy>;
1803 phy-names = "pciephy";
1804
1805 status = "disabled";
1806
1807 pcie4_port0: pcie@0 {
1808 device_type = "pci";
1809 reg = <0x0 0x0 0x0 0x0 0x0>;
1810 bus-range = <0x01 0xff>;
1811
1812 #address-cells = <3>;
1813 #size-cells = <2>;
1814 ranges;
1815 };
1816 };
1817
1818 pcie4_phy: phy@1c06000 {
1819 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1820 reg = <0x0 0x01c06000 0x0 0x2000>;
1821
1822 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1828 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1829 "pipe", "pipediv2";
1830
1831 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1832 assigned-clock-rates = <100000000>;
1833
1834 power-domains = <&gcc PCIE_4_GDSC>;
1835
1836 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1837 reset-names = "phy";
1838
1839 #clock-cells = <0>;
1840 clock-output-names = "pcie_4_pipe_clk";
1841
1842 #phy-cells = <0>;
1843
1844 status = "disabled";
1845 };
1846
1847 pcie3b: pcie@1c08000 {
1848 device_type = "pci";
1849 compatible = "qcom,pcie-sc8280xp";
1850 reg = <0x0 0x01c08000 0x0 0x3000>,
1851 <0x0 0x32000000 0x0 0xf1d>,
1852 <0x0 0x32000f20 0x0 0xa8>,
1853 <0x0 0x32001000 0x0 0x1000>,
1854 <0x0 0x32100000 0x0 0x100000>,
1855 <0x0 0x01c0b000 0x0 0x1000>;
1856 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1857 #address-cells = <3>;
1858 #size-cells = <2>;
1859 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1860 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1861 bus-range = <0x00 0xff>;
1862
1863 dma-coherent;
1864
1865 linux,pci-domain = <5>;
1866 num-lanes = <2>;
1867
1868 msi-map = <0x0 &its 0xd0000 0x10000>;
1869
1870 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1874 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1875
1876 #interrupt-cells = <1>;
1877 interrupt-map-mask = <0 0 0 0x7>;
1878 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1879 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1880 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1881 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1882
1883 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1891 clock-names = "aux",
1892 "cfg",
1893 "bus_master",
1894 "bus_slave",
1895 "slave_q2a",
1896 "ddrss_sf_tbu",
1897 "noc_aggr_4",
1898 "noc_aggr_south_sf";
1899
1900 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1901 assigned-clock-rates = <19200000>;
1902
1903 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1905 interconnect-names = "pcie-mem", "cpu-pcie";
1906
1907 resets = <&gcc GCC_PCIE_3B_BCR>;
1908 reset-names = "pci";
1909
1910 power-domains = <&gcc PCIE_3B_GDSC>;
1911 required-opps = <&rpmhpd_opp_nom>;
1912
1913 phys = <&pcie3b_phy>;
1914 phy-names = "pciephy";
1915
1916 status = "disabled";
1917
1918 pcie3b_port0: pcie@0 {
1919 device_type = "pci";
1920 reg = <0x0 0x0 0x0 0x0 0x0>;
1921 bus-range = <0x01 0xff>;
1922
1923 #address-cells = <3>;
1924 #size-cells = <2>;
1925 ranges;
1926 };
1927 };
1928
1929 pcie3b_phy: phy@1c0e000 {
1930 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1931 reg = <0x0 0x01c0e000 0x0 0x2000>;
1932
1933 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1939 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1940 "pipe", "pipediv2";
1941
1942 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1943 assigned-clock-rates = <100000000>;
1944
1945 power-domains = <&gcc PCIE_3B_GDSC>;
1946
1947 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1948 reset-names = "phy";
1949
1950 #clock-cells = <0>;
1951 clock-output-names = "pcie_3b_pipe_clk";
1952
1953 #phy-cells = <0>;
1954
1955 status = "disabled";
1956 };
1957
1958 pcie3a: pcie@1c10000 {
1959 device_type = "pci";
1960 compatible = "qcom,pcie-sc8280xp";
1961 reg = <0x0 0x01c10000 0x0 0x3000>,
1962 <0x0 0x34000000 0x0 0xf1d>,
1963 <0x0 0x34000f20 0x0 0xa8>,
1964 <0x0 0x34001000 0x0 0x1000>,
1965 <0x0 0x34100000 0x0 0x100000>,
1966 <0x0 0x01c13000 0x0 0x1000>;
1967 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1968 #address-cells = <3>;
1969 #size-cells = <2>;
1970 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1971 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1972 bus-range = <0x00 0xff>;
1973
1974 dma-coherent;
1975
1976 linux,pci-domain = <4>;
1977 num-lanes = <4>;
1978
1979 msi-map = <0x0 &its 0xc0000 0x10000>;
1980
1981 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1985 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1986
1987 #interrupt-cells = <1>;
1988 interrupt-map-mask = <0 0 0 0x7>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1990 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1991 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1992 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1993
1994 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2002 clock-names = "aux",
2003 "cfg",
2004 "bus_master",
2005 "bus_slave",
2006 "slave_q2a",
2007 "ddrss_sf_tbu",
2008 "noc_aggr_4",
2009 "noc_aggr_south_sf";
2010
2011 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2012 assigned-clock-rates = <19200000>;
2013
2014 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
2015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
2016 interconnect-names = "pcie-mem", "cpu-pcie";
2017
2018 resets = <&gcc GCC_PCIE_3A_BCR>;
2019 reset-names = "pci";
2020
2021 power-domains = <&gcc PCIE_3A_GDSC>;
2022 required-opps = <&rpmhpd_opp_nom>;
2023
2024 phys = <&pcie3a_phy>;
2025 phy-names = "pciephy";
2026
2027 status = "disabled";
2028
2029 pcie3a_port0: pcie@0 {
2030 device_type = "pci";
2031 reg = <0x0 0x0 0x0 0x0 0x0>;
2032 bus-range = <0x01 0xff>;
2033
2034 #address-cells = <3>;
2035 #size-cells = <2>;
2036 ranges;
2037 };
2038 };
2039
2040 pcie3a_phy: phy@1c14000 {
2041 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2042 reg = <0x0 0x01c14000 0x0 0x2000>,
2043 <0x0 0x01c16000 0x0 0x2000>;
2044
2045 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2051 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2052 "pipe", "pipediv2";
2053
2054 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2055 assigned-clock-rates = <100000000>;
2056
2057 power-domains = <&gcc PCIE_3A_GDSC>;
2058
2059 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2060 reset-names = "phy";
2061
2062 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2063
2064 #clock-cells = <0>;
2065 clock-output-names = "pcie_3a_pipe_clk";
2066
2067 #phy-cells = <0>;
2068
2069 status = "disabled";
2070 };
2071
2072 pcie2b: pcie@1c18000 {
2073 device_type = "pci";
2074 compatible = "qcom,pcie-sc8280xp";
2075 reg = <0x0 0x01c18000 0x0 0x3000>,
2076 <0x0 0x38000000 0x0 0xf1d>,
2077 <0x0 0x38000f20 0x0 0xa8>,
2078 <0x0 0x38001000 0x0 0x1000>,
2079 <0x0 0x38100000 0x0 0x100000>,
2080 <0x0 0x01c1b000 0x0 0x1000>;
2081 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2082 #address-cells = <3>;
2083 #size-cells = <2>;
2084 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2085 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2086 bus-range = <0x00 0xff>;
2087
2088 dma-coherent;
2089
2090 linux,pci-domain = <3>;
2091 num-lanes = <2>;
2092
2093 msi-map = <0x0 &its 0xb0000 0x10000>;
2094
2095 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2099 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2100
2101 #interrupt-cells = <1>;
2102 interrupt-map-mask = <0 0 0 0x7>;
2103 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2104 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2105 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2106 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2107
2108 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2116 clock-names = "aux",
2117 "cfg",
2118 "bus_master",
2119 "bus_slave",
2120 "slave_q2a",
2121 "ddrss_sf_tbu",
2122 "noc_aggr_4",
2123 "noc_aggr_south_sf";
2124
2125 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2126 assigned-clock-rates = <19200000>;
2127
2128 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2130 interconnect-names = "pcie-mem", "cpu-pcie";
2131
2132 resets = <&gcc GCC_PCIE_2B_BCR>;
2133 reset-names = "pci";
2134
2135 power-domains = <&gcc PCIE_2B_GDSC>;
2136 required-opps = <&rpmhpd_opp_nom>;
2137
2138 phys = <&pcie2b_phy>;
2139 phy-names = "pciephy";
2140
2141 status = "disabled";
2142
2143 pcie2b_port0: pcie@0 {
2144 device_type = "pci";
2145 reg = <0x0 0x0 0x0 0x0 0x0>;
2146 bus-range = <0x01 0xff>;
2147
2148 #address-cells = <3>;
2149 #size-cells = <2>;
2150 ranges;
2151 };
2152 };
2153
2154 pcie2b_phy: phy@1c1e000 {
2155 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2156 reg = <0x0 0x01c1e000 0x0 0x2000>;
2157
2158 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2164 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2165 "pipe", "pipediv2";
2166
2167 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2168 assigned-clock-rates = <100000000>;
2169
2170 power-domains = <&gcc PCIE_2B_GDSC>;
2171
2172 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2173 reset-names = "phy";
2174
2175 #clock-cells = <0>;
2176 clock-output-names = "pcie_2b_pipe_clk";
2177
2178 #phy-cells = <0>;
2179
2180 status = "disabled";
2181 };
2182
2183 pcie2a: pcie@1c20000 {
2184 device_type = "pci";
2185 compatible = "qcom,pcie-sc8280xp";
2186 reg = <0x0 0x01c20000 0x0 0x3000>,
2187 <0x0 0x3c000000 0x0 0xf1d>,
2188 <0x0 0x3c000f20 0x0 0xa8>,
2189 <0x0 0x3c001000 0x0 0x1000>,
2190 <0x0 0x3c100000 0x0 0x100000>,
2191 <0x0 0x01c23000 0x0 0x1000>;
2192 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2193 #address-cells = <3>;
2194 #size-cells = <2>;
2195 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2196 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2197 bus-range = <0x00 0xff>;
2198
2199 dma-coherent;
2200
2201 linux,pci-domain = <2>;
2202 num-lanes = <4>;
2203
2204 msi-map = <0x0 &its 0xa0000 0x10000>;
2205
2206 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2211
2212 #interrupt-cells = <1>;
2213 interrupt-map-mask = <0 0 0 0x7>;
2214 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2215 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2216 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2217 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2218
2219 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2227 clock-names = "aux",
2228 "cfg",
2229 "bus_master",
2230 "bus_slave",
2231 "slave_q2a",
2232 "ddrss_sf_tbu",
2233 "noc_aggr_4",
2234 "noc_aggr_south_sf";
2235
2236 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2237 assigned-clock-rates = <19200000>;
2238
2239 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2240 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2241 interconnect-names = "pcie-mem", "cpu-pcie";
2242
2243 resets = <&gcc GCC_PCIE_2A_BCR>;
2244 reset-names = "pci";
2245
2246 power-domains = <&gcc PCIE_2A_GDSC>;
2247 required-opps = <&rpmhpd_opp_nom>;
2248
2249 phys = <&pcie2a_phy>;
2250 phy-names = "pciephy";
2251
2252 status = "disabled";
2253
2254 pcie2a_port0: pcie@0 {
2255 device_type = "pci";
2256 reg = <0x0 0x0 0x0 0x0 0x0>;
2257 bus-range = <0x01 0xff>;
2258
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2261 ranges;
2262 };
2263 };
2264
2265 pcie2a_phy: phy@1c24000 {
2266 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2267 reg = <0x0 0x01c24000 0x0 0x2000>,
2268 <0x0 0x01c26000 0x0 0x2000>;
2269
2270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2276 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2277 "pipe", "pipediv2";
2278
2279 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2280 assigned-clock-rates = <100000000>;
2281
2282 power-domains = <&gcc PCIE_2A_GDSC>;
2283
2284 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2285 reset-names = "phy";
2286
2287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2288
2289 #clock-cells = <0>;
2290 clock-output-names = "pcie_2a_pipe_clk";
2291
2292 #phy-cells = <0>;
2293
2294 status = "disabled";
2295 };
2296
2297 ufs_mem_hc: ufs@1d84000 {
2298 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2299 "jedec,ufs-2.0";
2300 reg = <0 0x01d84000 0 0x3000>;
2301 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2302 phys = <&ufs_mem_phy>;
2303 phy-names = "ufsphy";
2304 lanes-per-direction = <2>;
2305 #reset-cells = <1>;
2306 resets = <&gcc GCC_UFS_PHY_BCR>;
2307 reset-names = "rst";
2308
2309 power-domains = <&gcc UFS_PHY_GDSC>;
2310 required-opps = <&rpmhpd_opp_nom>;
2311
2312 iommus = <&apps_smmu 0xe0 0x0>;
2313 dma-coherent;
2314
2315 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2323 clock-names = "core_clk",
2324 "bus_aggr_clk",
2325 "iface_clk",
2326 "core_clk_unipro",
2327 "ref_clk",
2328 "tx_lane0_sync_clk",
2329 "rx_lane0_sync_clk",
2330 "rx_lane1_sync_clk";
2331 freq-table-hz = <75000000 300000000>,
2332 <0 0>,
2333 <0 0>,
2334 <75000000 300000000>,
2335 <0 0>,
2336 <0 0>,
2337 <0 0>,
2338 <0 0>;
2339 status = "disabled";
2340 };
2341
2342 ufs_mem_phy: phy@1d87000 {
2343 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2344 reg = <0 0x01d87000 0 0x1000>;
2345
2346 clocks = <&rpmhcc RPMH_CXO_CLK>,
2347 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2348 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2349 clock-names = "ref",
2350 "ref_aux",
2351 "qref";
2352
2353 power-domains = <&gcc UFS_PHY_GDSC>;
2354
2355 resets = <&ufs_mem_hc 0>;
2356 reset-names = "ufsphy";
2357
2358 #phy-cells = <0>;
2359
2360 status = "disabled";
2361 };
2362
2363 ufs_card_hc: ufs@1da4000 {
2364 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2365 "jedec,ufs-2.0";
2366 reg = <0 0x01da4000 0 0x3000>;
2367 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2368 phys = <&ufs_card_phy>;
2369 phy-names = "ufsphy";
2370 lanes-per-direction = <2>;
2371 #reset-cells = <1>;
2372 resets = <&gcc GCC_UFS_CARD_BCR>;
2373 reset-names = "rst";
2374
2375 power-domains = <&gcc UFS_CARD_GDSC>;
2376
2377 iommus = <&apps_smmu 0x4a0 0x0>;
2378 dma-coherent;
2379
2380 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2388 clock-names = "core_clk",
2389 "bus_aggr_clk",
2390 "iface_clk",
2391 "core_clk_unipro",
2392 "ref_clk",
2393 "tx_lane0_sync_clk",
2394 "rx_lane0_sync_clk",
2395 "rx_lane1_sync_clk";
2396 freq-table-hz = <75000000 300000000>,
2397 <0 0>,
2398 <0 0>,
2399 <75000000 300000000>,
2400 <0 0>,
2401 <0 0>,
2402 <0 0>,
2403 <0 0>;
2404 status = "disabled";
2405 };
2406
2407 ufs_card_phy: phy@1da7000 {
2408 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2409 reg = <0 0x01da7000 0 0x1000>;
2410
2411 clocks = <&rpmhcc RPMH_CXO_CLK>,
2412 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2413 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2414 clock-names = "ref",
2415 "ref_aux",
2416 "qref";
2417
2418 power-domains = <&gcc UFS_CARD_GDSC>;
2419
2420 resets = <&ufs_card_hc 0>;
2421 reset-names = "ufsphy";
2422
2423 #phy-cells = <0>;
2424
2425 status = "disabled";
2426 };
2427
2428 tcsr_mutex: hwlock@1f40000 {
2429 compatible = "qcom,tcsr-mutex";
2430 reg = <0x0 0x01f40000 0x0 0x20000>;
2431 #hwlock-cells = <1>;
2432 };
2433
2434 tcsr: syscon@1fc0000 {
2435 compatible = "qcom,sc8280xp-tcsr", "syscon";
2436 reg = <0x0 0x01fc0000 0x0 0x30000>;
2437 };
2438
2439 gpu: gpu@3d00000 {
2440 compatible = "qcom,adreno-690.0", "qcom,adreno";
2441
2442 reg = <0 0x03d00000 0 0x40000>,
2443 <0 0x03d9e000 0 0x1000>,
2444 <0 0x03d61000 0 0x800>;
2445 reg-names = "kgsl_3d0_reg_memory",
2446 "cx_mem",
2447 "cx_dbgc";
2448 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2449 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2450 operating-points-v2 = <&gpu_opp_table>;
2451
2452 qcom,gmu = <&gmu>;
2453 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2454 interconnect-names = "gfx-mem";
2455 #cooling-cells = <2>;
2456
2457 status = "disabled";
2458
2459 gpu_opp_table: opp-table {
2460 compatible = "operating-points-v2";
2461
2462 opp-270000000 {
2463 opp-hz = /bits/ 64 <270000000>;
2464 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2465 opp-peak-kBps = <451000>;
2466 };
2467
2468 opp-410000000 {
2469 opp-hz = /bits/ 64 <410000000>;
2470 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2471 opp-peak-kBps = <1555000>;
2472 };
2473
2474 opp-500000000 {
2475 opp-hz = /bits/ 64 <500000000>;
2476 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2477 opp-peak-kBps = <1555000>;
2478 };
2479
2480 opp-547000000 {
2481 opp-hz = /bits/ 64 <547000000>;
2482 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2483 opp-peak-kBps = <1555000>;
2484 };
2485
2486 opp-606000000 {
2487 opp-hz = /bits/ 64 <606000000>;
2488 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2489 opp-peak-kBps = <2736000>;
2490 };
2491
2492 opp-640000000 {
2493 opp-hz = /bits/ 64 <640000000>;
2494 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2495 opp-peak-kBps = <2736000>;
2496 };
2497
2498 opp-655000000 {
2499 opp-hz = /bits/ 64 <655000000>;
2500 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2501 opp-peak-kBps = <2736000>;
2502 };
2503
2504 opp-690000000 {
2505 opp-hz = /bits/ 64 <690000000>;
2506 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2507 opp-peak-kBps = <2736000>;
2508 };
2509 };
2510 };
2511
2512 gmu: gmu@3d6a000 {
2513 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2514 reg = <0 0x03d6a000 0 0x34000>,
2515 <0 0x03de0000 0 0x10000>,
2516 <0 0x0b290000 0 0x10000>;
2517 reg-names = "gmu", "rscc", "gmu_pdc";
2518 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2519 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2520 interrupt-names = "hfi", "gmu";
2521 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2522 <&gpucc GPU_CC_CXO_CLK>,
2523 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2525 <&gpucc GPU_CC_AHB_CLK>,
2526 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2527 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2528 clock-names = "gmu",
2529 "cxo",
2530 "axi",
2531 "memnoc",
2532 "ahb",
2533 "hub",
2534 "smmu_vote";
2535 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2536 <&gpucc GPU_CC_GX_GDSC>;
2537 power-domain-names = "cx",
2538 "gx";
2539 iommus = <&gpu_smmu 5 0xc00>;
2540 operating-points-v2 = <&gmu_opp_table>;
2541
2542 gmu_opp_table: opp-table {
2543 compatible = "operating-points-v2";
2544
2545 opp-200000000 {
2546 opp-hz = /bits/ 64 <200000000>;
2547 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2548 };
2549
2550 opp-500000000 {
2551 opp-hz = /bits/ 64 <500000000>;
2552 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2553 };
2554 };
2555 };
2556
2557 gpucc: clock-controller@3d90000 {
2558 compatible = "qcom,sc8280xp-gpucc";
2559 reg = <0 0x03d90000 0 0x9000>;
2560 clocks = <&rpmhcc RPMH_CXO_CLK>,
2561 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2562 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2563 clock-names = "bi_tcxo",
2564 "gcc_gpu_gpll0_clk_src",
2565 "gcc_gpu_gpll0_div_clk_src";
2566
2567 power-domains = <&rpmhpd SC8280XP_GFX>;
2568 #clock-cells = <1>;
2569 #reset-cells = <1>;
2570 #power-domain-cells = <1>;
2571 };
2572
2573 gpu_smmu: iommu@3da0000 {
2574 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2575 "qcom,smmu-500", "arm,mmu-500";
2576 reg = <0 0x03da0000 0 0x20000>;
2577 #iommu-cells = <2>;
2578 #global-interrupts = <2>;
2579 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2580 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2581 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2584 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2585 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2588 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2590 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2591 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2592 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2593
2594 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2595 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2596 <&gpucc GPU_CC_AHB_CLK>,
2597 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2598 <&gpucc GPU_CC_CX_GMU_CLK>,
2599 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2600 <&gpucc GPU_CC_HUB_AON_CLK>;
2601 clock-names = "gcc_gpu_memnoc_gfx_clk",
2602 "gcc_gpu_snoc_dvm_gfx_clk",
2603 "gpu_cc_ahb_clk",
2604 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2605 "gpu_cc_cx_gmu_clk",
2606 "gpu_cc_hub_cx_int_clk",
2607 "gpu_cc_hub_aon_clk";
2608
2609 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2610 dma-coherent;
2611 };
2612
2613 usb_0_hsphy: phy@88e5000 {
2614 compatible = "qcom,sc8280xp-usb-hs-phy",
2615 "qcom,usb-snps-hs-5nm-phy";
2616 reg = <0 0x088e5000 0 0x400>;
2617 clocks = <&rpmhcc RPMH_CXO_CLK>;
2618 clock-names = "ref";
2619 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2620
2621 #phy-cells = <0>;
2622
2623 status = "disabled";
2624 };
2625
2626 usb_2_hsphy0: phy@88e7000 {
2627 compatible = "qcom,sc8280xp-usb-hs-phy",
2628 "qcom,usb-snps-hs-5nm-phy";
2629 reg = <0 0x088e7000 0 0x400>;
2630 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2631 clock-names = "ref";
2632 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2633
2634 #phy-cells = <0>;
2635
2636 status = "disabled";
2637 };
2638
2639 usb_2_hsphy1: phy@88e8000 {
2640 compatible = "qcom,sc8280xp-usb-hs-phy",
2641 "qcom,usb-snps-hs-5nm-phy";
2642 reg = <0 0x088e8000 0 0x400>;
2643 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2644 clock-names = "ref";
2645 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2646
2647 #phy-cells = <0>;
2648
2649 status = "disabled";
2650 };
2651
2652 usb_2_hsphy2: phy@88e9000 {
2653 compatible = "qcom,sc8280xp-usb-hs-phy",
2654 "qcom,usb-snps-hs-5nm-phy";
2655 reg = <0 0x088e9000 0 0x400>;
2656 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2657 clock-names = "ref";
2658 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2659
2660 #phy-cells = <0>;
2661
2662 status = "disabled";
2663 };
2664
2665 usb_2_hsphy3: phy@88ea000 {
2666 compatible = "qcom,sc8280xp-usb-hs-phy",
2667 "qcom,usb-snps-hs-5nm-phy";
2668 reg = <0 0x088ea000 0 0x400>;
2669 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2670 clock-names = "ref";
2671 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2672
2673 #phy-cells = <0>;
2674
2675 status = "disabled";
2676 };
2677
2678 usb_2_qmpphy0: phy@88ef000 {
2679 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2680 reg = <0 0x088ef000 0 0x2000>;
2681
2682 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2686 clock-names = "aux", "ref", "com_aux", "pipe";
2687
2688 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2690 reset-names = "phy", "phy_phy";
2691
2692 power-domains = <&gcc USB30_MP_GDSC>;
2693
2694 #clock-cells = <0>;
2695 clock-output-names = "usb2_phy0_pipe_clk";
2696
2697 #phy-cells = <0>;
2698
2699 status = "disabled";
2700 };
2701
2702 usb_2_qmpphy1: phy@88f1000 {
2703 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2704 reg = <0 0x088f1000 0 0x2000>;
2705
2706 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2710 clock-names = "aux", "ref", "com_aux", "pipe";
2711
2712 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2714 reset-names = "phy", "phy_phy";
2715
2716 power-domains = <&gcc USB30_MP_GDSC>;
2717
2718 #clock-cells = <0>;
2719 clock-output-names = "usb2_phy1_pipe_clk";
2720
2721 #phy-cells = <0>;
2722
2723 status = "disabled";
2724 };
2725
2726 remoteproc_adsp: remoteproc@3000000 {
2727 compatible = "qcom,sc8280xp-adsp-pas";
2728 reg = <0 0x03000000 0 0x100>;
2729
2730 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2731 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2732 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2733 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2734 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2735 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2736 interrupt-names = "wdog", "fatal", "ready",
2737 "handover", "stop-ack", "shutdown-ack";
2738
2739 clocks = <&rpmhcc RPMH_CXO_CLK>;
2740 clock-names = "xo";
2741
2742 power-domains = <&rpmhpd SC8280XP_LCX>,
2743 <&rpmhpd SC8280XP_LMX>;
2744 power-domain-names = "lcx", "lmx";
2745
2746 memory-region = <&pil_adsp_mem>;
2747
2748 qcom,qmp = <&aoss_qmp>;
2749
2750 qcom,smem-states = <&smp2p_adsp_out 0>;
2751 qcom,smem-state-names = "stop";
2752
2753 status = "disabled";
2754
2755 remoteproc_adsp_glink: glink-edge {
2756 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2757 IPCC_MPROC_SIGNAL_GLINK_QMP
2758 IRQ_TYPE_EDGE_RISING>;
2759 mboxes = <&ipcc IPCC_CLIENT_LPASS
2760 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2761
2762 label = "lpass";
2763 qcom,remote-pid = <2>;
2764
2765 gpr {
2766 compatible = "qcom,gpr";
2767 qcom,glink-channels = "adsp_apps";
2768 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2769 qcom,intents = <512 20>;
2770 #address-cells = <1>;
2771 #size-cells = <0>;
2772
2773 q6apm: service@1 {
2774 compatible = "qcom,q6apm";
2775 reg = <GPR_APM_MODULE_IID>;
2776 #sound-dai-cells = <0>;
2777 qcom,protection-domain = "avs/audio",
2778 "msm/adsp/audio_pd";
2779 q6apmdai: dais {
2780 compatible = "qcom,q6apm-dais";
2781 iommus = <&apps_smmu 0x0c01 0x0>;
2782 };
2783
2784 q6apmbedai: bedais {
2785 compatible = "qcom,q6apm-lpass-dais";
2786 #sound-dai-cells = <1>;
2787 };
2788 };
2789
2790 q6prm: service@2 {
2791 compatible = "qcom,q6prm";
2792 reg = <GPR_PRM_MODULE_IID>;
2793 qcom,protection-domain = "avs/audio",
2794 "msm/adsp/audio_pd";
2795 q6prmcc: clock-controller {
2796 compatible = "qcom,q6prm-lpass-clocks";
2797 #clock-cells = <2>;
2798 };
2799 };
2800 };
2801 };
2802 };
2803
2804 rxmacro: rxmacro@3200000 {
2805 compatible = "qcom,sc8280xp-lpass-rx-macro";
2806 reg = <0 0x03200000 0 0x1000>;
2807 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2808 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2809 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2810 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2811 <&vamacro>;
2812 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2813 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2814 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2815 assigned-clock-rates = <19200000>, <19200000>;
2816
2817 clock-output-names = "mclk";
2818 #clock-cells = <0>;
2819 #sound-dai-cells = <1>;
2820
2821 pinctrl-names = "default";
2822 pinctrl-0 = <&rx_swr_default>;
2823
2824 status = "disabled";
2825 };
2826
2827 swr1: soundwire@3210000 {
2828 compatible = "qcom,soundwire-v1.6.0";
2829 reg = <0 0x03210000 0 0x2000>;
2830 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2831 clocks = <&rxmacro>;
2832 clock-names = "iface";
2833 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2834 reset-names = "swr_audio_cgcr";
2835 label = "RX";
2836
2837 qcom,din-ports = <0>;
2838 qcom,dout-ports = <5>;
2839
2840 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2841 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2842 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2843 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2844 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2845 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2846 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2847 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2848 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2849
2850 #sound-dai-cells = <1>;
2851 #address-cells = <2>;
2852 #size-cells = <0>;
2853
2854 status = "disabled";
2855 };
2856
2857 txmacro: txmacro@3220000 {
2858 compatible = "qcom,sc8280xp-lpass-tx-macro";
2859 reg = <0 0x03220000 0 0x1000>;
2860 pinctrl-names = "default";
2861 pinctrl-0 = <&tx_swr_default>;
2862 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2863 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2864 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2865 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2866 <&vamacro>;
2867
2868 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2869 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2870 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2871 assigned-clock-rates = <19200000>, <19200000>;
2872 clock-output-names = "mclk";
2873
2874 #clock-cells = <0>;
2875 #sound-dai-cells = <1>;
2876
2877 status = "disabled";
2878 };
2879
2880 wsamacro: codec@3240000 {
2881 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2882 reg = <0 0x03240000 0 0x1000>;
2883 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2886 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2887 <&vamacro>;
2888 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2889 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2891 assigned-clock-rates = <19200000>, <19200000>;
2892
2893 #clock-cells = <0>;
2894 clock-output-names = "mclk";
2895 #sound-dai-cells = <1>;
2896
2897 pinctrl-names = "default";
2898 pinctrl-0 = <&wsa_swr_default>;
2899
2900 status = "disabled";
2901 };
2902
2903 swr0: soundwire@3250000 {
2904 reg = <0 0x03250000 0 0x2000>;
2905 compatible = "qcom,soundwire-v1.6.0";
2906 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2907 clocks = <&wsamacro>;
2908 clock-names = "iface";
2909 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2910 reset-names = "swr_audio_cgcr";
2911 label = "WSA";
2912
2913 qcom,din-ports = <2>;
2914 qcom,dout-ports = <6>;
2915
2916 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2917 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2918 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2919 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2921 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2922 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2923 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2924 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2925
2926 #sound-dai-cells = <1>;
2927 #address-cells = <2>;
2928 #size-cells = <0>;
2929
2930 status = "disabled";
2931 };
2932
2933 lpass_audiocc: clock-controller@32a9000 {
2934 compatible = "qcom,sc8280xp-lpassaudiocc";
2935 reg = <0 0x032a9000 0 0x1000>;
2936 #clock-cells = <1>;
2937 #reset-cells = <1>;
2938 };
2939
2940 swr2: soundwire@3330000 {
2941 compatible = "qcom,soundwire-v1.6.0";
2942 reg = <0 0x03330000 0 0x2000>;
2943 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2944 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2945 interrupt-names = "core", "wakeup";
2946
2947 clocks = <&txmacro>;
2948 clock-names = "iface";
2949 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2950 reset-names = "swr_audio_cgcr";
2951 label = "TX";
2952 #sound-dai-cells = <1>;
2953 #address-cells = <2>;
2954 #size-cells = <0>;
2955
2956 qcom,din-ports = <4>;
2957 qcom,dout-ports = <0>;
2958 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2959 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2960 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2961 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2962 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2963 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2964 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2965 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2966 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2967
2968 status = "disabled";
2969 };
2970
2971 vamacro: codec@3370000 {
2972 compatible = "qcom,sc8280xp-lpass-va-macro";
2973 reg = <0 0x03370000 0 0x1000>;
2974 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2975 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2976 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2977 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2978 clock-names = "mclk", "macro", "dcodec", "npl";
2979 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2980 assigned-clock-rates = <19200000>;
2981
2982 #clock-cells = <0>;
2983 clock-output-names = "fsgen";
2984 #sound-dai-cells = <1>;
2985
2986 status = "disabled";
2987 };
2988
2989 lpass_tlmm: pinctrl@33c0000 {
2990 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2991 reg = <0 0x33c0000 0x0 0x20000>,
2992 <0 0x3550000 0x0 0x10000>;
2993 gpio-controller;
2994 #gpio-cells = <2>;
2995 gpio-ranges = <&lpass_tlmm 0 0 19>;
2996
2997 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2998 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2999 clock-names = "core", "audio";
3000
3001 status = "disabled";
3002
3003 tx_swr_default: tx-swr-default-state {
3004 clk-pins {
3005 pins = "gpio0";
3006 function = "swr_tx_clk";
3007 drive-strength = <2>;
3008 slew-rate = <1>;
3009 bias-disable;
3010 };
3011
3012 data-pins {
3013 pins = "gpio1", "gpio2";
3014 function = "swr_tx_data";
3015 drive-strength = <2>;
3016 slew-rate = <1>;
3017 bias-bus-hold;
3018 };
3019 };
3020
3021 rx_swr_default: rx-swr-default-state {
3022 clk-pins {
3023 pins = "gpio3";
3024 function = "swr_rx_clk";
3025 drive-strength = <2>;
3026 slew-rate = <1>;
3027 bias-disable;
3028 };
3029
3030 data-pins {
3031 pins = "gpio4", "gpio5";
3032 function = "swr_rx_data";
3033 drive-strength = <2>;
3034 slew-rate = <1>;
3035 bias-bus-hold;
3036 };
3037 };
3038
3039 dmic01_default: dmic01-default-state {
3040 clk-pins {
3041 pins = "gpio6";
3042 function = "dmic1_clk";
3043 drive-strength = <8>;
3044 output-high;
3045 };
3046
3047 data-pins {
3048 pins = "gpio7";
3049 function = "dmic1_data";
3050 drive-strength = <8>;
3051 input-enable;
3052 };
3053 };
3054
3055 dmic01_sleep: dmic01-sleep-state {
3056 clk-pins {
3057 pins = "gpio6";
3058 function = "dmic1_clk";
3059 drive-strength = <2>;
3060 bias-disable;
3061 output-low;
3062 };
3063
3064 data-pins {
3065 pins = "gpio7";
3066 function = "dmic1_data";
3067 drive-strength = <2>;
3068 bias-pull-down;
3069 input-enable;
3070 };
3071 };
3072
3073 dmic23_default: dmic23-default-state {
3074 clk-pins {
3075 pins = "gpio8";
3076 function = "dmic2_clk";
3077 drive-strength = <8>;
3078 output-high;
3079 };
3080
3081 data-pins {
3082 pins = "gpio9";
3083 function = "dmic2_data";
3084 drive-strength = <8>;
3085 input-enable;
3086 };
3087 };
3088
3089 dmic23_sleep: dmic23-sleep-state {
3090 clk-pins {
3091 pins = "gpio8";
3092 function = "dmic2_clk";
3093 drive-strength = <2>;
3094 bias-disable;
3095 output-low;
3096 };
3097
3098 data-pins {
3099 pins = "gpio9";
3100 function = "dmic2_data";
3101 drive-strength = <2>;
3102 bias-pull-down;
3103 input-enable;
3104 };
3105 };
3106
3107 wsa_swr_default: wsa-swr-default-state {
3108 clk-pins {
3109 pins = "gpio10";
3110 function = "wsa_swr_clk";
3111 drive-strength = <2>;
3112 slew-rate = <1>;
3113 bias-disable;
3114 };
3115
3116 data-pins {
3117 pins = "gpio11";
3118 function = "wsa_swr_data";
3119 drive-strength = <2>;
3120 slew-rate = <1>;
3121 bias-bus-hold;
3122 };
3123 };
3124
3125 wsa2_swr_default: wsa2-swr-default-state {
3126 clk-pins {
3127 pins = "gpio15";
3128 function = "wsa2_swr_clk";
3129 drive-strength = <2>;
3130 slew-rate = <1>;
3131 bias-disable;
3132 };
3133
3134 data-pins {
3135 pins = "gpio16";
3136 function = "wsa2_swr_data";
3137 drive-strength = <2>;
3138 slew-rate = <1>;
3139 bias-bus-hold;
3140 };
3141 };
3142 };
3143
3144 lpasscc: clock-controller@33e0000 {
3145 compatible = "qcom,sc8280xp-lpasscc";
3146 reg = <0 0x033e0000 0 0x12000>;
3147 #clock-cells = <1>;
3148 #reset-cells = <1>;
3149 };
3150
3151 sdc2: mmc@8804000 {
3152 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3153 reg = <0 0x08804000 0 0x1000>;
3154
3155 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3156 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3157 interrupt-names = "hc_irq", "pwr_irq";
3158
3159 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3160 <&gcc GCC_SDCC2_APPS_CLK>,
3161 <&rpmhcc RPMH_CXO_CLK>;
3162 clock-names = "iface", "core", "xo";
3163 resets = <&gcc GCC_SDCC2_BCR>;
3164 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3166 interconnect-names = "sdhc-ddr","cpu-sdhc";
3167 iommus = <&apps_smmu 0x4e0 0x0>;
3168 power-domains = <&rpmhpd SC8280XP_CX>;
3169 operating-points-v2 = <&sdc2_opp_table>;
3170 bus-width = <4>;
3171 dma-coherent;
3172
3173 status = "disabled";
3174
3175 sdc2_opp_table: opp-table {
3176 compatible = "operating-points-v2";
3177
3178 opp-100000000 {
3179 opp-hz = /bits/ 64 <100000000>;
3180 required-opps = <&rpmhpd_opp_low_svs>;
3181 opp-peak-kBps = <1800000 400000>;
3182 opp-avg-kBps = <100000 0>;
3183 };
3184
3185 opp-202000000 {
3186 opp-hz = /bits/ 64 <202000000>;
3187 required-opps = <&rpmhpd_opp_svs_l1>;
3188 opp-peak-kBps = <5400000 1600000>;
3189 opp-avg-kBps = <200000 0>;
3190 };
3191 };
3192 };
3193
3194 usb_0_qmpphy: phy@88eb000 {
3195 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3196 reg = <0 0x088eb000 0 0x4000>;
3197
3198 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3202 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3203
3204 power-domains = <&gcc USB30_PRIM_GDSC>;
3205
3206 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3208 reset-names = "phy", "common";
3209
3210 #clock-cells = <1>;
3211 #phy-cells = <1>;
3212
3213 status = "disabled";
3214
3215 ports {
3216 #address-cells = <1>;
3217 #size-cells = <0>;
3218
3219 port@0 {
3220 reg = <0>;
3221
3222 usb_0_qmpphy_out: endpoint {};
3223 };
3224
3225 port@1 {
3226 reg = <1>;
3227
3228 usb_0_qmpphy_usb_ss_in: endpoint {
3229 remote-endpoint = <&usb_0_dwc3_ss>;
3230 };
3231 };
3232
3233 port@2 {
3234 reg = <2>;
3235
3236 usb_0_qmpphy_dp_in: endpoint {};
3237 };
3238 };
3239 };
3240
3241 usb_1_hsphy: phy@8902000 {
3242 compatible = "qcom,sc8280xp-usb-hs-phy",
3243 "qcom,usb-snps-hs-5nm-phy";
3244 reg = <0 0x08902000 0 0x400>;
3245 #phy-cells = <0>;
3246
3247 clocks = <&rpmhcc RPMH_CXO_CLK>;
3248 clock-names = "ref";
3249
3250 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3251
3252 status = "disabled";
3253 };
3254
3255 usb_1_qmpphy: phy@8903000 {
3256 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3257 reg = <0 0x08903000 0 0x4000>;
3258
3259 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3263 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3264
3265 power-domains = <&gcc USB30_SEC_GDSC>;
3266
3267 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3269 reset-names = "phy", "common";
3270
3271 #clock-cells = <1>;
3272 #phy-cells = <1>;
3273
3274 status = "disabled";
3275
3276 ports {
3277 #address-cells = <1>;
3278 #size-cells = <0>;
3279
3280 port@0 {
3281 reg = <0>;
3282
3283 usb_1_qmpphy_out: endpoint {};
3284 };
3285
3286 port@1 {
3287 reg = <1>;
3288
3289 usb_1_qmpphy_usb_ss_in: endpoint {
3290 remote-endpoint = <&usb_1_dwc3_ss>;
3291 };
3292 };
3293
3294 port@2 {
3295 reg = <2>;
3296
3297 usb_1_qmpphy_dp_in: endpoint {};
3298 };
3299 };
3300 };
3301
3302 mdss1_dp0_phy: phy@8909a00 {
3303 compatible = "qcom,sc8280xp-dp-phy";
3304 reg = <0 0x08909a00 0 0x19c>,
3305 <0 0x08909200 0 0xec>,
3306 <0 0x08909600 0 0xec>,
3307 <0 0x08909000 0 0x1c8>;
3308
3309 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3310 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3311 clock-names = "aux", "cfg_ahb";
3312 power-domains = <&rpmhpd SC8280XP_MX>;
3313
3314 #clock-cells = <1>;
3315 #phy-cells = <0>;
3316
3317 status = "disabled";
3318 };
3319
3320 mdss1_dp1_phy: phy@890ca00 {
3321 compatible = "qcom,sc8280xp-dp-phy";
3322 reg = <0 0x0890ca00 0 0x19c>,
3323 <0 0x0890c200 0 0xec>,
3324 <0 0x0890c600 0 0xec>,
3325 <0 0x0890c000 0 0x1c8>;
3326
3327 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3328 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3329 clock-names = "aux", "cfg_ahb";
3330 power-domains = <&rpmhpd SC8280XP_MX>;
3331
3332 #clock-cells = <1>;
3333 #phy-cells = <0>;
3334
3335 status = "disabled";
3336 };
3337
3338 pmu@9091000 {
3339 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3340 reg = <0 0x09091000 0 0x1000>;
3341
3342 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3343
3344 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3345
3346 operating-points-v2 = <&llcc_bwmon_opp_table>;
3347
3348 llcc_bwmon_opp_table: opp-table {
3349 compatible = "operating-points-v2";
3350
3351 opp-0 {
3352 opp-peak-kBps = <762000>;
3353 };
3354 opp-1 {
3355 opp-peak-kBps = <1720000>;
3356 };
3357 opp-2 {
3358 opp-peak-kBps = <2086000>;
3359 };
3360 opp-3 {
3361 opp-peak-kBps = <2597000>;
3362 };
3363 opp-4 {
3364 opp-peak-kBps = <2929000>;
3365 };
3366 opp-5 {
3367 opp-peak-kBps = <3879000>;
3368 };
3369 opp-6 {
3370 opp-peak-kBps = <5161000>;
3371 };
3372 opp-7 {
3373 opp-peak-kBps = <5931000>;
3374 };
3375 opp-8 {
3376 opp-peak-kBps = <6515000>;
3377 };
3378 opp-9 {
3379 opp-peak-kBps = <7980000>;
3380 };
3381 opp-10 {
3382 opp-peak-kBps = <8136000>;
3383 };
3384 opp-11 {
3385 opp-peak-kBps = <10437000>;
3386 };
3387 opp-12 {
3388 opp-peak-kBps = <12191000>;
3389 };
3390 };
3391 };
3392
3393 pmu@90b6400 {
3394 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3395 reg = <0 0x090b6400 0 0x600>;
3396
3397 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3398
3399 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3400 operating-points-v2 = <&cpu_bwmon_opp_table>;
3401
3402 cpu_bwmon_opp_table: opp-table {
3403 compatible = "operating-points-v2";
3404
3405 opp-0 {
3406 opp-peak-kBps = <2288000>;
3407 };
3408 opp-1 {
3409 opp-peak-kBps = <4577000>;
3410 };
3411 opp-2 {
3412 opp-peak-kBps = <7110000>;
3413 };
3414 opp-3 {
3415 opp-peak-kBps = <9155000>;
3416 };
3417 opp-4 {
3418 opp-peak-kBps = <12298000>;
3419 };
3420 opp-5 {
3421 opp-peak-kBps = <14236000>;
3422 };
3423 opp-6 {
3424 opp-peak-kBps = <15258001>;
3425 };
3426 };
3427 };
3428
3429 system-cache-controller@9200000 {
3430 compatible = "qcom,sc8280xp-llcc";
3431 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3432 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3433 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3434 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3435 <0 0x09600000 0 0x58000>;
3436 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3437 "llcc3_base", "llcc4_base", "llcc5_base",
3438 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
3439 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3440 };
3441
3442 usb_2: usb@a4f8800 {
3443 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3";
3444 reg = <0 0x0a4f8800 0 0x400>;
3445 #address-cells = <2>;
3446 #size-cells = <2>;
3447 ranges;
3448
3449 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3450 <&gcc GCC_USB30_MP_MASTER_CLK>,
3451 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3452 <&gcc GCC_USB30_MP_SLEEP_CLK>,
3453 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3454 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3455 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3456 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3457 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3458 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3459 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3460
3461 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3462 <&gcc GCC_USB30_MP_MASTER_CLK>;
3463 assigned-clock-rates = <19200000>, <200000000>;
3464
3465 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3466 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3467 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
3468 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3469 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3470 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3471 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>,
3472 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
3473 <&pdc 127 IRQ_TYPE_EDGE_BOTH>,
3474 <&pdc 126 IRQ_TYPE_EDGE_BOTH>,
3475 <&pdc 129 IRQ_TYPE_EDGE_BOTH>,
3476 <&pdc 128 IRQ_TYPE_EDGE_BOTH>,
3477 <&pdc 131 IRQ_TYPE_EDGE_BOTH>,
3478 <&pdc 130 IRQ_TYPE_EDGE_BOTH>,
3479 <&pdc 133 IRQ_TYPE_EDGE_BOTH>,
3480 <&pdc 132 IRQ_TYPE_EDGE_BOTH>,
3481 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3482 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3483
3484 interrupt-names = "pwr_event_1", "pwr_event_2",
3485 "pwr_event_3", "pwr_event_4",
3486 "hs_phy_1", "hs_phy_2",
3487 "hs_phy_3", "hs_phy_4",
3488 "dp_hs_phy_1", "dm_hs_phy_1",
3489 "dp_hs_phy_2", "dm_hs_phy_2",
3490 "dp_hs_phy_3", "dm_hs_phy_3",
3491 "dp_hs_phy_4", "dm_hs_phy_4",
3492 "ss_phy_1", "ss_phy_2";
3493
3494 power-domains = <&gcc USB30_MP_GDSC>;
3495 required-opps = <&rpmhpd_opp_nom>;
3496
3497 resets = <&gcc GCC_USB30_MP_BCR>;
3498
3499 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>,
3500 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>;
3501 interconnect-names = "usb-ddr", "apps-usb";
3502
3503 wakeup-source;
3504
3505 status = "disabled";
3506
3507 usb_2_dwc3: usb@a400000 {
3508 compatible = "snps,dwc3";
3509 reg = <0 0x0a400000 0 0xcd00>;
3510 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3511 iommus = <&apps_smmu 0x800 0x0>;
3512 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
3513 <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
3514 <&usb_2_hsphy2>,
3515 <&usb_2_hsphy3>;
3516 phy-names = "usb2-0", "usb3-0",
3517 "usb2-1", "usb3-1",
3518 "usb2-2",
3519 "usb2-3";
3520 dr_mode = "host";
3521 };
3522 };
3523
3524 usb_0: usb@a6f8800 {
3525 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3526 reg = <0 0x0a6f8800 0 0x400>;
3527 #address-cells = <2>;
3528 #size-cells = <2>;
3529 ranges;
3530
3531 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3540 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3541 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3542
3543 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3545 assigned-clock-rates = <19200000>, <200000000>;
3546
3547 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3548 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
3549 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3550 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3551 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3552 interrupt-names = "pwr_event",
3553 "hs_phy_irq",
3554 "dp_hs_phy_irq",
3555 "dm_hs_phy_irq",
3556 "ss_phy_irq";
3557
3558 power-domains = <&gcc USB30_PRIM_GDSC>;
3559 required-opps = <&rpmhpd_opp_nom>;
3560
3561 resets = <&gcc GCC_USB30_PRIM_BCR>;
3562
3563 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3564 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3565 interconnect-names = "usb-ddr", "apps-usb";
3566
3567 wakeup-source;
3568
3569 status = "disabled";
3570
3571 usb_0_dwc3: usb@a600000 {
3572 compatible = "snps,dwc3";
3573 reg = <0 0x0a600000 0 0xcd00>;
3574 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3575 iommus = <&apps_smmu 0x820 0x0>;
3576 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3577 phy-names = "usb2-phy", "usb3-phy";
3578
3579 ports {
3580 #address-cells = <1>;
3581 #size-cells = <0>;
3582
3583 port@0 {
3584 reg = <0>;
3585
3586 usb_0_dwc3_hs: endpoint {
3587 };
3588 };
3589
3590 port@1 {
3591 reg = <1>;
3592
3593 usb_0_dwc3_ss: endpoint {
3594 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
3595 };
3596 };
3597 };
3598 };
3599 };
3600
3601 usb_1: usb@a8f8800 {
3602 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3603 reg = <0 0x0a8f8800 0 0x400>;
3604 #address-cells = <2>;
3605 #size-cells = <2>;
3606 ranges;
3607
3608 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3617 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3618 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3619
3620 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3622 assigned-clock-rates = <19200000>, <200000000>;
3623
3624 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3625 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
3626 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3627 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3628 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3629 interrupt-names = "pwr_event",
3630 "hs_phy_irq",
3631 "dp_hs_phy_irq",
3632 "dm_hs_phy_irq",
3633 "ss_phy_irq";
3634
3635 power-domains = <&gcc USB30_SEC_GDSC>;
3636 required-opps = <&rpmhpd_opp_nom>;
3637
3638 resets = <&gcc GCC_USB30_SEC_BCR>;
3639
3640 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3641 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3642 interconnect-names = "usb-ddr", "apps-usb";
3643
3644 wakeup-source;
3645
3646 status = "disabled";
3647
3648 usb_1_dwc3: usb@a800000 {
3649 compatible = "snps,dwc3";
3650 reg = <0 0x0a800000 0 0xcd00>;
3651 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3652 iommus = <&apps_smmu 0x860 0x0>;
3653 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3654 phy-names = "usb2-phy", "usb3-phy";
3655
3656 ports {
3657 #address-cells = <1>;
3658 #size-cells = <0>;
3659
3660 port@0 {
3661 reg = <0>;
3662
3663 usb_1_dwc3_hs: endpoint {
3664 };
3665 };
3666
3667 port@1 {
3668 reg = <1>;
3669
3670 usb_1_dwc3_ss: endpoint {
3671 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3672 };
3673 };
3674 };
3675 };
3676 };
3677
3678 cci0: cci@ac4a000 {
3679 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3680 reg = <0 0x0ac4a000 0 0x1000>;
3681
3682 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3683
3684 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3685 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3686 <&camcc CAMCC_CPAS_AHB_CLK>,
3687 <&camcc CAMCC_CCI_0_CLK>;
3688 clock-names = "camnoc_axi",
3689 "slow_ahb_src",
3690 "cpas_ahb",
3691 "cci";
3692
3693 power-domains = <&camcc TITAN_TOP_GDSC>;
3694
3695 pinctrl-0 = <&cci0_default>;
3696 pinctrl-1 = <&cci0_sleep>;
3697 pinctrl-names = "default", "sleep";
3698
3699 #address-cells = <1>;
3700 #size-cells = <0>;
3701
3702 status = "disabled";
3703
3704 cci0_i2c0: i2c-bus@0 {
3705 reg = <0>;
3706 clock-frequency = <1000000>;
3707 #address-cells = <1>;
3708 #size-cells = <0>;
3709 };
3710
3711 cci0_i2c1: i2c-bus@1 {
3712 reg = <1>;
3713 clock-frequency = <1000000>;
3714 #address-cells = <1>;
3715 #size-cells = <0>;
3716 };
3717 };
3718
3719 cci1: cci@ac4b000 {
3720 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3721 reg = <0 0x0ac4b000 0 0x1000>;
3722
3723 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3724
3725 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3726 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3727 <&camcc CAMCC_CPAS_AHB_CLK>,
3728 <&camcc CAMCC_CCI_1_CLK>;
3729 clock-names = "camnoc_axi",
3730 "slow_ahb_src",
3731 "cpas_ahb",
3732 "cci";
3733
3734 power-domains = <&camcc TITAN_TOP_GDSC>;
3735
3736 pinctrl-0 = <&cci1_default>;
3737 pinctrl-1 = <&cci1_sleep>;
3738 pinctrl-names = "default", "sleep";
3739
3740 #address-cells = <1>;
3741 #size-cells = <0>;
3742
3743 status = "disabled";
3744
3745 cci1_i2c0: i2c-bus@0 {
3746 reg = <0>;
3747 clock-frequency = <1000000>;
3748 #address-cells = <1>;
3749 #size-cells = <0>;
3750 };
3751
3752 cci1_i2c1: i2c-bus@1 {
3753 reg = <1>;
3754 clock-frequency = <1000000>;
3755 #address-cells = <1>;
3756 #size-cells = <0>;
3757 };
3758 };
3759
3760 cci2: cci@ac4c000 {
3761 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3762 reg = <0 0x0ac4c000 0 0x1000>;
3763
3764 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
3765
3766 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3767 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3768 <&camcc CAMCC_CPAS_AHB_CLK>,
3769 <&camcc CAMCC_CCI_2_CLK>;
3770 clock-names = "camnoc_axi",
3771 "slow_ahb_src",
3772 "cpas_ahb",
3773 "cci";
3774 power-domains = <&camcc TITAN_TOP_GDSC>;
3775
3776 pinctrl-0 = <&cci2_default>;
3777 pinctrl-1 = <&cci2_sleep>;
3778 pinctrl-names = "default", "sleep";
3779
3780 #address-cells = <1>;
3781 #size-cells = <0>;
3782
3783 status = "disabled";
3784
3785 cci2_i2c0: i2c-bus@0 {
3786 reg = <0>;
3787 clock-frequency = <1000000>;
3788 #address-cells = <1>;
3789 #size-cells = <0>;
3790 };
3791
3792 cci2_i2c1: i2c-bus@1 {
3793 reg = <1>;
3794 clock-frequency = <1000000>;
3795 #address-cells = <1>;
3796 #size-cells = <0>;
3797 };
3798 };
3799
3800 cci3: cci@ac4d000 {
3801 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3802 reg = <0 0x0ac4d000 0 0x1000>;
3803
3804 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
3805
3806 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3807 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3808 <&camcc CAMCC_CPAS_AHB_CLK>,
3809 <&camcc CAMCC_CCI_3_CLK>;
3810 clock-names = "camnoc_axi",
3811 "slow_ahb_src",
3812 "cpas_ahb",
3813 "cci";
3814
3815 power-domains = <&camcc TITAN_TOP_GDSC>;
3816
3817 pinctrl-0 = <&cci3_default>;
3818 pinctrl-1 = <&cci3_sleep>;
3819 pinctrl-names = "default", "sleep";
3820
3821 #address-cells = <1>;
3822 #size-cells = <0>;
3823
3824 status = "disabled";
3825
3826 cci3_i2c0: i2c-bus@0 {
3827 reg = <0>;
3828 clock-frequency = <1000000>;
3829 #address-cells = <1>;
3830 #size-cells = <0>;
3831 };
3832
3833 cci3_i2c1: i2c-bus@1 {
3834 reg = <1>;
3835 clock-frequency = <1000000>;
3836 #address-cells = <1>;
3837 #size-cells = <0>;
3838 };
3839 };
3840
3841 camss: camss@ac5a000 {
3842 compatible = "qcom,sc8280xp-camss";
3843
3844 reg = <0 0x0ac5a000 0 0x2000>,
3845 <0 0x0ac5c000 0 0x2000>,
3846 <0 0x0ac65000 0 0x2000>,
3847 <0 0x0ac67000 0 0x2000>,
3848 <0 0x0acaf000 0 0x4000>,
3849 <0 0x0acb3000 0 0x1000>,
3850 <0 0x0acb6000 0 0x4000>,
3851 <0 0x0acba000 0 0x1000>,
3852 <0 0x0acbd000 0 0x4000>,
3853 <0 0x0acc1000 0 0x1000>,
3854 <0 0x0acc4000 0 0x4000>,
3855 <0 0x0acc8000 0 0x1000>,
3856 <0 0x0accb000 0 0x4000>,
3857 <0 0x0accf000 0 0x1000>,
3858 <0 0x0acd2000 0 0x4000>,
3859 <0 0x0acd6000 0 0x1000>,
3860 <0 0x0acd9000 0 0x4000>,
3861 <0 0x0acdd000 0 0x1000>,
3862 <0 0x0ace0000 0 0x4000>,
3863 <0 0x0ace4000 0 0x1000>;
3864 reg-names = "csiphy2",
3865 "csiphy3",
3866 "csiphy0",
3867 "csiphy1",
3868 "vfe0",
3869 "csid0",
3870 "vfe1",
3871 "csid1",
3872 "vfe2",
3873 "csid2",
3874 "vfe_lite0",
3875 "csid0_lite",
3876 "vfe_lite1",
3877 "csid1_lite",
3878 "vfe_lite2",
3879 "csid2_lite",
3880 "vfe_lite3",
3881 "csid3_lite",
3882 "vfe3",
3883 "csid3";
3884
3885 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
3887 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3888 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3889 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3890 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3892 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3893 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3894 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3895 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3896 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3897 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3898 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3899 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
3900 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
3901 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
3902 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
3903 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
3904 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
3905 interrupt-names = "csid1_lite",
3906 "vfe_lite1",
3907 "csiphy3",
3908 "csid0",
3909 "vfe0",
3910 "csid1",
3911 "vfe1",
3912 "csid0_lite",
3913 "vfe_lite0",
3914 "csiphy0",
3915 "csiphy1",
3916 "csiphy2",
3917 "csid2",
3918 "vfe2",
3919 "csid3_lite",
3920 "csid2_lite",
3921 "vfe_lite3",
3922 "vfe_lite2",
3923 "csid3",
3924 "vfe3";
3925
3926 power-domains = <&camcc IFE_0_GDSC>,
3927 <&camcc IFE_1_GDSC>,
3928 <&camcc IFE_2_GDSC>,
3929 <&camcc IFE_3_GDSC>,
3930 <&camcc TITAN_TOP_GDSC>;
3931 power-domain-names = "ife0",
3932 "ife1",
3933 "ife2",
3934 "ife3",
3935 "top";
3936
3937 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3938 <&camcc CAMCC_CPAS_AHB_CLK>,
3939 <&camcc CAMCC_CSIPHY0_CLK>,
3940 <&camcc CAMCC_CSI0PHYTIMER_CLK>,
3941 <&camcc CAMCC_CSIPHY1_CLK>,
3942 <&camcc CAMCC_CSI1PHYTIMER_CLK>,
3943 <&camcc CAMCC_CSIPHY2_CLK>,
3944 <&camcc CAMCC_CSI2PHYTIMER_CLK>,
3945 <&camcc CAMCC_CSIPHY3_CLK>,
3946 <&camcc CAMCC_CSI3PHYTIMER_CLK>,
3947 <&camcc CAMCC_IFE_0_AXI_CLK>,
3948 <&camcc CAMCC_IFE_0_CLK>,
3949 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
3950 <&camcc CAMCC_IFE_0_CSID_CLK>,
3951 <&camcc CAMCC_IFE_1_AXI_CLK>,
3952 <&camcc CAMCC_IFE_1_CLK>,
3953 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
3954 <&camcc CAMCC_IFE_1_CSID_CLK>,
3955 <&camcc CAMCC_IFE_2_AXI_CLK>,
3956 <&camcc CAMCC_IFE_2_CLK>,
3957 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
3958 <&camcc CAMCC_IFE_2_CSID_CLK>,
3959 <&camcc CAMCC_IFE_3_AXI_CLK>,
3960 <&camcc CAMCC_IFE_3_CLK>,
3961 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
3962 <&camcc CAMCC_IFE_3_CSID_CLK>,
3963 <&camcc CAMCC_IFE_LITE_0_CLK>,
3964 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
3965 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
3966 <&camcc CAMCC_IFE_LITE_1_CLK>,
3967 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
3968 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
3969 <&camcc CAMCC_IFE_LITE_2_CLK>,
3970 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
3971 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
3972 <&camcc CAMCC_IFE_LITE_3_CLK>,
3973 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
3974 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
3975 <&gcc GCC_CAMERA_HF_AXI_CLK>,
3976 <&gcc GCC_CAMERA_SF_AXI_CLK>;
3977 clock-names = "camnoc_axi",
3978 "cpas_ahb",
3979 "csiphy0",
3980 "csiphy0_timer",
3981 "csiphy1",
3982 "csiphy1_timer",
3983 "csiphy2",
3984 "csiphy2_timer",
3985 "csiphy3",
3986 "csiphy3_timer",
3987 "vfe0_axi",
3988 "vfe0",
3989 "vfe0_cphy_rx",
3990 "vfe0_csid",
3991 "vfe1_axi",
3992 "vfe1",
3993 "vfe1_cphy_rx",
3994 "vfe1_csid",
3995 "vfe2_axi",
3996 "vfe2",
3997 "vfe2_cphy_rx",
3998 "vfe2_csid",
3999 "vfe3_axi",
4000 "vfe3",
4001 "vfe3_cphy_rx",
4002 "vfe3_csid",
4003 "vfe_lite0",
4004 "vfe_lite0_cphy_rx",
4005 "vfe_lite0_csid",
4006 "vfe_lite1",
4007 "vfe_lite1_cphy_rx",
4008 "vfe_lite1_csid",
4009 "vfe_lite2",
4010 "vfe_lite2_cphy_rx",
4011 "vfe_lite2_csid",
4012 "vfe_lite3",
4013 "vfe_lite3_cphy_rx",
4014 "vfe_lite3_csid",
4015 "gcc_axi_hf",
4016 "gcc_axi_sf";
4017
4018 iommus = <&apps_smmu 0x2000 0x4e0>,
4019 <&apps_smmu 0x2020 0x4e0>,
4020 <&apps_smmu 0x2040 0x4e0>,
4021 <&apps_smmu 0x2060 0x4e0>,
4022 <&apps_smmu 0x2080 0x4e0>,
4023 <&apps_smmu 0x20e0 0x4e0>,
4024 <&apps_smmu 0x20c0 0x4e0>,
4025 <&apps_smmu 0x20a0 0x4e0>,
4026 <&apps_smmu 0x2400 0x4e0>,
4027 <&apps_smmu 0x2420 0x4e0>,
4028 <&apps_smmu 0x2440 0x4e0>,
4029 <&apps_smmu 0x2460 0x4e0>,
4030 <&apps_smmu 0x2480 0x4e0>,
4031 <&apps_smmu 0x24e0 0x4e0>,
4032 <&apps_smmu 0x24c0 0x4e0>,
4033 <&apps_smmu 0x24a0 0x4e0>;
4034
4035 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
4036 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
4037 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
4038 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
4039 interconnect-names = "cam_ahb",
4040 "cam_hf_mnoc",
4041 "cam_sf_mnoc",
4042 "cam_sf_icp_mnoc";
4043
4044 status = "disabled";
4045
4046 ports {
4047 #address-cells = <1>;
4048 #size-cells = <0>;
4049
4050 port@0 {
4051 reg = <0>;
4052 #address-cells = <1>;
4053 #size-cells = <0>;
4054 };
4055
4056 port@1 {
4057 reg = <1>;
4058 #address-cells = <1>;
4059 #size-cells = <0>;
4060 };
4061
4062 port@2 {
4063 reg = <2>;
4064 #address-cells = <1>;
4065 #size-cells = <0>;
4066 };
4067
4068 port@3 {
4069 reg = <3>;
4070 #address-cells = <1>;
4071 #size-cells = <0>;
4072 };
4073 };
4074 };
4075
4076 camcc: clock-controller@ad00000 {
4077 compatible = "qcom,sc8280xp-camcc";
4078 reg = <0 0x0ad00000 0 0x20000>;
4079 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4080 <&rpmhcc RPMH_CXO_CLK>,
4081 <&rpmhcc RPMH_CXO_CLK_A>,
4082 <&sleep_clk>;
4083 power-domains = <&rpmhpd SC8280XP_MMCX>;
4084 required-opps = <&rpmhpd_opp_low_svs>;
4085 #clock-cells = <1>;
4086 #reset-cells = <1>;
4087 #power-domain-cells = <1>;
4088 };
4089
4090 mdss0: display-subsystem@ae00000 {
4091 compatible = "qcom,sc8280xp-mdss";
4092 reg = <0 0x0ae00000 0 0x1000>;
4093 reg-names = "mdss";
4094
4095 clocks = <&gcc GCC_DISP_AHB_CLK>,
4096 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4098 clock-names = "iface",
4099 "ahb",
4100 "core";
4101 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4102 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
4103 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
4104 interconnect-names = "mdp0-mem", "mdp1-mem";
4105 iommus = <&apps_smmu 0x1000 0x402>;
4106 power-domains = <&dispcc0 MDSS_GDSC>;
4107 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4108
4109 interrupt-controller;
4110 #interrupt-cells = <1>;
4111 #address-cells = <2>;
4112 #size-cells = <2>;
4113 ranges;
4114
4115 status = "disabled";
4116
4117 mdss0_mdp: display-controller@ae01000 {
4118 compatible = "qcom,sc8280xp-dpu";
4119 reg = <0 0x0ae01000 0 0x8f000>,
4120 <0 0x0aeb0000 0 0x2008>;
4121 reg-names = "mdp", "vbif";
4122
4123 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124 <&gcc GCC_DISP_SF_AXI_CLK>,
4125 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4129 clock-names = "bus",
4130 "nrt_bus",
4131 "iface",
4132 "lut",
4133 "core",
4134 "vsync";
4135 interrupt-parent = <&mdss0>;
4136 interrupts = <0>;
4137 power-domains = <&rpmhpd SC8280XP_MMCX>;
4138
4139 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4140 assigned-clock-rates = <19200000>;
4141 operating-points-v2 = <&mdss0_mdp_opp_table>;
4142
4143 ports {
4144 #address-cells = <1>;
4145 #size-cells = <0>;
4146
4147 port@0 {
4148 reg = <0>;
4149 mdss0_intf0_out: endpoint {
4150 remote-endpoint = <&mdss0_dp0_in>;
4151 };
4152 };
4153
4154 port@4 {
4155 reg = <4>;
4156 mdss0_intf4_out: endpoint {
4157 remote-endpoint = <&mdss0_dp1_in>;
4158 };
4159 };
4160
4161 port@5 {
4162 reg = <5>;
4163 mdss0_intf5_out: endpoint {
4164 remote-endpoint = <&mdss0_dp3_in>;
4165 };
4166 };
4167
4168 port@6 {
4169 reg = <6>;
4170 mdss0_intf6_out: endpoint {
4171 remote-endpoint = <&mdss0_dp2_in>;
4172 };
4173 };
4174 };
4175
4176 mdss0_mdp_opp_table: opp-table {
4177 compatible = "operating-points-v2";
4178
4179 opp-200000000 {
4180 opp-hz = /bits/ 64 <200000000>;
4181 required-opps = <&rpmhpd_opp_low_svs>;
4182 };
4183
4184 opp-300000000 {
4185 opp-hz = /bits/ 64 <300000000>;
4186 required-opps = <&rpmhpd_opp_svs>;
4187 };
4188
4189 opp-375000000 {
4190 opp-hz = /bits/ 64 <375000000>;
4191 required-opps = <&rpmhpd_opp_svs_l1>;
4192 };
4193
4194 opp-500000000 {
4195 opp-hz = /bits/ 64 <500000000>;
4196 required-opps = <&rpmhpd_opp_nom>;
4197 };
4198 opp-600000000 {
4199 opp-hz = /bits/ 64 <600000000>;
4200 required-opps = <&rpmhpd_opp_turbo_l1>;
4201 };
4202 };
4203 };
4204
4205 mdss0_dp0: displayport-controller@ae90000 {
4206 compatible = "qcom,sc8280xp-dp";
4207 reg = <0 0xae90000 0 0x200>,
4208 <0 0xae90200 0 0x200>,
4209 <0 0xae90400 0 0x600>,
4210 <0 0xae91000 0 0x400>,
4211 <0 0xae91400 0 0x400>;
4212 interrupt-parent = <&mdss0>;
4213 interrupts = <12>;
4214 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4219 clock-names = "core_iface", "core_aux",
4220 "ctrl_link",
4221 "ctrl_link_iface",
4222 "stream_pixel";
4223
4224 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4226 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4227 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4228
4229 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4230 phy-names = "dp";
4231
4232 #sound-dai-cells = <0>;
4233
4234 operating-points-v2 = <&mdss0_dp0_opp_table>;
4235 power-domains = <&rpmhpd SC8280XP_MMCX>;
4236
4237 status = "disabled";
4238
4239 ports {
4240 #address-cells = <1>;
4241 #size-cells = <0>;
4242
4243 port@0 {
4244 reg = <0>;
4245
4246 mdss0_dp0_in: endpoint {
4247 remote-endpoint = <&mdss0_intf0_out>;
4248 };
4249 };
4250
4251 port@1 {
4252 reg = <1>;
4253
4254 mdss0_dp0_out: endpoint {
4255 };
4256 };
4257 };
4258
4259 mdss0_dp0_opp_table: opp-table {
4260 compatible = "operating-points-v2";
4261
4262 opp-160000000 {
4263 opp-hz = /bits/ 64 <160000000>;
4264 required-opps = <&rpmhpd_opp_low_svs>;
4265 };
4266
4267 opp-270000000 {
4268 opp-hz = /bits/ 64 <270000000>;
4269 required-opps = <&rpmhpd_opp_svs>;
4270 };
4271
4272 opp-540000000 {
4273 opp-hz = /bits/ 64 <540000000>;
4274 required-opps = <&rpmhpd_opp_svs_l1>;
4275 };
4276
4277 opp-810000000 {
4278 opp-hz = /bits/ 64 <810000000>;
4279 required-opps = <&rpmhpd_opp_nom>;
4280 };
4281 };
4282 };
4283
4284 mdss0_dp1: displayport-controller@ae98000 {
4285 compatible = "qcom,sc8280xp-dp";
4286 reg = <0 0xae98000 0 0x200>,
4287 <0 0xae98200 0 0x200>,
4288 <0 0xae98400 0 0x600>,
4289 <0 0xae99000 0 0x400>,
4290 <0 0xae99400 0 0x400>;
4291 interrupt-parent = <&mdss0>;
4292 interrupts = <13>;
4293 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4298 clock-names = "core_iface", "core_aux",
4299 "ctrl_link",
4300 "ctrl_link_iface", "stream_pixel";
4301
4302 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4304 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4305 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4306
4307 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4308 phy-names = "dp";
4309
4310 #sound-dai-cells = <0>;
4311
4312 operating-points-v2 = <&mdss0_dp1_opp_table>;
4313 power-domains = <&rpmhpd SC8280XP_MMCX>;
4314
4315 status = "disabled";
4316
4317 ports {
4318 #address-cells = <1>;
4319 #size-cells = <0>;
4320
4321 port@0 {
4322 reg = <0>;
4323
4324 mdss0_dp1_in: endpoint {
4325 remote-endpoint = <&mdss0_intf4_out>;
4326 };
4327 };
4328
4329 port@1 {
4330 reg = <1>;
4331
4332 mdss0_dp1_out: endpoint {
4333 };
4334 };
4335 };
4336
4337 mdss0_dp1_opp_table: opp-table {
4338 compatible = "operating-points-v2";
4339
4340 opp-160000000 {
4341 opp-hz = /bits/ 64 <160000000>;
4342 required-opps = <&rpmhpd_opp_low_svs>;
4343 };
4344
4345 opp-270000000 {
4346 opp-hz = /bits/ 64 <270000000>;
4347 required-opps = <&rpmhpd_opp_svs>;
4348 };
4349
4350 opp-540000000 {
4351 opp-hz = /bits/ 64 <540000000>;
4352 required-opps = <&rpmhpd_opp_svs_l1>;
4353 };
4354
4355 opp-810000000 {
4356 opp-hz = /bits/ 64 <810000000>;
4357 required-opps = <&rpmhpd_opp_nom>;
4358 };
4359 };
4360 };
4361
4362 mdss0_dp2: displayport-controller@ae9a000 {
4363 compatible = "qcom,sc8280xp-dp";
4364 reg = <0 0xae9a000 0 0x200>,
4365 <0 0xae9a200 0 0x200>,
4366 <0 0xae9a400 0 0x600>,
4367 <0 0xae9b000 0 0x400>,
4368 <0 0xae9b400 0 0x400>;
4369
4370 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4375 clock-names = "core_iface", "core_aux",
4376 "ctrl_link",
4377 "ctrl_link_iface", "stream_pixel";
4378 interrupt-parent = <&mdss0>;
4379 interrupts = <14>;
4380 phys = <&mdss0_dp2_phy>;
4381 phy-names = "dp";
4382 power-domains = <&rpmhpd SC8280XP_MMCX>;
4383
4384 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4386 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4387 operating-points-v2 = <&mdss0_dp2_opp_table>;
4388
4389 #sound-dai-cells = <0>;
4390
4391 status = "disabled";
4392
4393 ports {
4394 #address-cells = <1>;
4395 #size-cells = <0>;
4396
4397 port@0 {
4398 reg = <0>;
4399 mdss0_dp2_in: endpoint {
4400 remote-endpoint = <&mdss0_intf6_out>;
4401 };
4402 };
4403
4404 port@1 {
4405 reg = <1>;
4406 };
4407 };
4408
4409 mdss0_dp2_opp_table: opp-table {
4410 compatible = "operating-points-v2";
4411
4412 opp-160000000 {
4413 opp-hz = /bits/ 64 <160000000>;
4414 required-opps = <&rpmhpd_opp_low_svs>;
4415 };
4416
4417 opp-270000000 {
4418 opp-hz = /bits/ 64 <270000000>;
4419 required-opps = <&rpmhpd_opp_svs>;
4420 };
4421
4422 opp-540000000 {
4423 opp-hz = /bits/ 64 <540000000>;
4424 required-opps = <&rpmhpd_opp_svs_l1>;
4425 };
4426
4427 opp-810000000 {
4428 opp-hz = /bits/ 64 <810000000>;
4429 required-opps = <&rpmhpd_opp_nom>;
4430 };
4431 };
4432 };
4433
4434 mdss0_dp3: displayport-controller@aea0000 {
4435 compatible = "qcom,sc8280xp-dp";
4436 reg = <0 0xaea0000 0 0x200>,
4437 <0 0xaea0200 0 0x200>,
4438 <0 0xaea0400 0 0x600>,
4439 <0 0xaea1000 0 0x400>,
4440 <0 0xaea1400 0 0x400>;
4441
4442 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4447 clock-names = "core_iface", "core_aux",
4448 "ctrl_link",
4449 "ctrl_link_iface", "stream_pixel";
4450 interrupt-parent = <&mdss0>;
4451 interrupts = <15>;
4452 phys = <&mdss0_dp3_phy>;
4453 phy-names = "dp";
4454 power-domains = <&rpmhpd SC8280XP_MMCX>;
4455
4456 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4458 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4459 operating-points-v2 = <&mdss0_dp3_opp_table>;
4460
4461 #sound-dai-cells = <0>;
4462
4463 status = "disabled";
4464
4465 ports {
4466 #address-cells = <1>;
4467 #size-cells = <0>;
4468
4469 port@0 {
4470 reg = <0>;
4471 mdss0_dp3_in: endpoint {
4472 remote-endpoint = <&mdss0_intf5_out>;
4473 };
4474 };
4475
4476 port@1 {
4477 reg = <1>;
4478 };
4479 };
4480
4481 mdss0_dp3_opp_table: opp-table {
4482 compatible = "operating-points-v2";
4483
4484 opp-160000000 {
4485 opp-hz = /bits/ 64 <160000000>;
4486 required-opps = <&rpmhpd_opp_low_svs>;
4487 };
4488
4489 opp-270000000 {
4490 opp-hz = /bits/ 64 <270000000>;
4491 required-opps = <&rpmhpd_opp_svs>;
4492 };
4493
4494 opp-540000000 {
4495 opp-hz = /bits/ 64 <540000000>;
4496 required-opps = <&rpmhpd_opp_svs_l1>;
4497 };
4498
4499 opp-810000000 {
4500 opp-hz = /bits/ 64 <810000000>;
4501 required-opps = <&rpmhpd_opp_nom>;
4502 };
4503 };
4504 };
4505 };
4506
4507 mdss0_dp2_phy: phy@aec2a00 {
4508 compatible = "qcom,sc8280xp-dp-phy";
4509 reg = <0 0x0aec2a00 0 0x19c>,
4510 <0 0x0aec2200 0 0xec>,
4511 <0 0x0aec2600 0 0xec>,
4512 <0 0x0aec2000 0 0x1c8>;
4513
4514 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4516 clock-names = "aux", "cfg_ahb";
4517 power-domains = <&rpmhpd SC8280XP_MX>;
4518
4519 #clock-cells = <1>;
4520 #phy-cells = <0>;
4521
4522 status = "disabled";
4523 };
4524
4525 mdss0_dp3_phy: phy@aec5a00 {
4526 compatible = "qcom,sc8280xp-dp-phy";
4527 reg = <0 0x0aec5a00 0 0x19c>,
4528 <0 0x0aec5200 0 0xec>,
4529 <0 0x0aec5600 0 0xec>,
4530 <0 0x0aec5000 0 0x1c8>;
4531
4532 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4534 clock-names = "aux", "cfg_ahb";
4535 power-domains = <&rpmhpd SC8280XP_MX>;
4536
4537 #clock-cells = <1>;
4538 #phy-cells = <0>;
4539
4540 status = "disabled";
4541 };
4542
4543 dispcc0: clock-controller@af00000 {
4544 compatible = "qcom,sc8280xp-dispcc0";
4545 reg = <0 0x0af00000 0 0x20000>;
4546
4547 clocks = <&gcc GCC_DISP_AHB_CLK>,
4548 <&rpmhcc RPMH_CXO_CLK>,
4549 <&sleep_clk>,
4550 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4551 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4552 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4553 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4554 <&mdss0_dp2_phy 0>,
4555 <&mdss0_dp2_phy 1>,
4556 <&mdss0_dp3_phy 0>,
4557 <&mdss0_dp3_phy 1>,
4558 <0>,
4559 <0>,
4560 <0>,
4561 <0>;
4562 power-domains = <&rpmhpd SC8280XP_MMCX>;
4563
4564 #clock-cells = <1>;
4565 #power-domain-cells = <1>;
4566 #reset-cells = <1>;
4567
4568 status = "disabled";
4569 };
4570
4571 pdc: interrupt-controller@b220000 {
4572 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4573 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4574 qcom,pdc-ranges = <0 480 40>,
4575 <40 140 14>,
4576 <54 263 1>,
4577 <55 306 4>,
4578 <59 312 3>,
4579 <62 374 2>,
4580 <64 434 2>,
4581 <66 438 3>,
4582 <69 86 1>,
4583 <70 520 54>,
4584 <124 609 28>,
4585 <159 638 1>,
4586 <160 720 8>,
4587 <168 801 1>,
4588 <169 728 30>,
4589 <199 416 2>,
4590 <201 449 1>,
4591 <202 89 1>,
4592 <203 451 1>,
4593 <204 462 1>,
4594 <205 264 1>,
4595 <206 579 1>,
4596 <207 653 1>,
4597 <208 656 1>,
4598 <209 659 1>,
4599 <210 122 1>,
4600 <211 699 1>,
4601 <212 705 1>,
4602 <213 450 1>,
4603 <214 643 1>,
4604 <216 646 5>,
4605 <221 390 5>,
4606 <226 700 3>,
4607 <229 240 3>,
4608 <232 269 1>,
4609 <233 377 1>,
4610 <234 372 1>,
4611 <235 138 1>,
4612 <236 857 1>,
4613 <237 860 1>,
4614 <238 137 1>,
4615 <239 668 1>,
4616 <240 366 1>,
4617 <241 949 1>,
4618 <242 815 5>,
4619 <247 769 1>,
4620 <248 768 1>,
4621 <249 663 1>,
4622 <250 799 2>,
4623 <252 798 1>,
4624 <253 765 1>,
4625 <254 763 1>,
4626 <255 454 1>,
4627 <258 139 1>,
4628 <259 786 2>,
4629 <261 370 2>,
4630 <263 158 2>;
4631 #interrupt-cells = <2>;
4632 interrupt-parent = <&intc>;
4633 interrupt-controller;
4634 };
4635
4636 tsens2: thermal-sensor@c251000 {
4637 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4638 reg = <0 0x0c251000 0 0x1ff>,
4639 <0 0x0c224000 0 0x8>;
4640 #qcom,sensors = <11>;
4641 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4642 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>;
4643 interrupt-names = "uplow", "critical";
4644 #thermal-sensor-cells = <1>;
4645 };
4646
4647 tsens3: thermal-sensor@c252000 {
4648 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4649 reg = <0 0x0c252000 0 0x1ff>,
4650 <0 0x0c225000 0 0x8>;
4651 #qcom,sensors = <5>;
4652 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4653 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>;
4654 interrupt-names = "uplow", "critical";
4655 #thermal-sensor-cells = <1>;
4656 };
4657
4658 tsens0: thermal-sensor@c263000 {
4659 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4660 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4661 <0 0x0c222000 0 0x8>; /* SROT */
4662 #qcom,sensors = <14>;
4663 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4664 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4665 interrupt-names = "uplow", "critical";
4666 #thermal-sensor-cells = <1>;
4667 };
4668
4669 restart@c264000 {
4670 compatible = "qcom,pshold";
4671 reg = <0 0x0c264000 0 0x4>;
4672 /* TZ seems to block access */
4673 status = "reserved";
4674 };
4675
4676 tsens1: thermal-sensor@c265000 {
4677 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4678 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4679 <0 0x0c223000 0 0x8>; /* SROT */
4680 #qcom,sensors = <16>;
4681 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4682 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4683 interrupt-names = "uplow", "critical";
4684 #thermal-sensor-cells = <1>;
4685 };
4686
4687 aoss_qmp: power-management@c300000 {
4688 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4689 reg = <0 0x0c300000 0 0x400>;
4690 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4691 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4692
4693 #clock-cells = <0>;
4694 };
4695
4696 sram@c3f0000 {
4697 compatible = "qcom,rpmh-stats";
4698 reg = <0 0x0c3f0000 0 0x400>;
4699 qcom,qmp = <&aoss_qmp>;
4700 };
4701
4702 spmi_bus: spmi@c440000 {
4703 compatible = "qcom,spmi-pmic-arb";
4704 reg = <0 0x0c440000 0 0x1100>,
4705 <0 0x0c600000 0 0x2000000>,
4706 <0 0x0e600000 0 0x100000>,
4707 <0 0x0e700000 0 0xa0000>,
4708 <0 0x0c40a000 0 0x26000>;
4709 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4710 interrupt-names = "periph_irq";
4711 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4712 qcom,ee = <0>;
4713 qcom,channel = <0>;
4714 #address-cells = <2>;
4715 #size-cells = <0>;
4716 interrupt-controller;
4717 #interrupt-cells = <4>;
4718 };
4719
4720 tlmm: pinctrl@f100000 {
4721 compatible = "qcom,sc8280xp-tlmm";
4722 reg = <0 0x0f100000 0 0x300000>;
4723 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4724 gpio-controller;
4725 #gpio-cells = <2>;
4726 interrupt-controller;
4727 #interrupt-cells = <2>;
4728 gpio-ranges = <&tlmm 0 0 230>;
4729 wakeup-parent = <&pdc>;
4730
4731 cci0_default: cci0-default-state {
4732 cci0_i2c0_default: cci0-i2c0-default-pins {
4733 /* cci_i2c_sda0, cci_i2c_scl0 */
4734 pins = "gpio113", "gpio114";
4735 function = "cci_i2c";
4736 drive-strength = <2>;
4737 bias-pull-up;
4738 };
4739
4740 cci0_i2c1_default: cci0-i2c1-default-pins {
4741 /* cci_i2c_sda1, cci_i2c_scl1 */
4742 pins = "gpio115", "gpio116";
4743 function = "cci_i2c";
4744 drive-strength = <2>;
4745 bias-pull-up;
4746 };
4747 };
4748
4749 cci0_sleep: cci0-sleep-state {
4750 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4751 /* cci_i2c_sda0, cci_i2c_scl0 */
4752 pins = "gpio113", "gpio114";
4753 function = "cci_i2c";
4754 drive-strength = <2>;
4755 bias-pull-down;
4756 };
4757
4758 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4759 /* cci_i2c_sda1, cci_i2c_scl1 */
4760 pins = "gpio115", "gpio116";
4761 function = "cci_i2c";
4762 drive-strength = <2>;
4763 bias-pull-down;
4764 };
4765 };
4766
4767 cci1_default: cci1-default-state {
4768 cci1_i2c0_default: cci1-i2c0-default-pins {
4769 /* cci_i2c_sda2, cci_i2c_scl2 */
4770 pins = "gpio10","gpio11";
4771 function = "cci_i2c";
4772 drive-strength = <2>;
4773 bias-pull-up;
4774 };
4775
4776 cci1_i2c1_default: cci1-i2c1-default-pins {
4777 /* cci_i2c_sda3, cci_i2c_scl3 */
4778 pins = "gpio123","gpio124";
4779 function = "cci_i2c";
4780 drive-strength = <2>;
4781 bias-pull-up;
4782 };
4783 };
4784
4785 cci1_sleep: cci1-sleep-state {
4786 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4787 /* cci_i2c_sda2, cci_i2c_scl2 */
4788 pins = "gpio10","gpio11";
4789 function = "cci_i2c";
4790 drive-strength = <2>;
4791 bias-pull-down;
4792 };
4793
4794 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4795 /* cci_i2c_sda3, cci_i2c_scl3 */
4796 pins = "gpio123","gpio124";
4797 function = "cci_i2c";
4798 drive-strength = <2>;
4799 bias-pull-down;
4800 };
4801 };
4802
4803 cci2_default: cci2-default-state {
4804 cci2_i2c0_default: cci2-i2c0-default-pins {
4805 /* cci_i2c_sda4, cci_i2c_scl4 */
4806 pins = "gpio117","gpio118";
4807 function = "cci_i2c";
4808 drive-strength = <2>;
4809 bias-pull-up;
4810 };
4811
4812 cci2_i2c1_default: cci2-i2c1-default-pins {
4813 /* cci_i2c_sda5, cci_i2c_scl5 */
4814 pins = "gpio12","gpio13";
4815 function = "cci_i2c";
4816 drive-strength = <2>;
4817 bias-pull-up;
4818 };
4819 };
4820
4821 cci2_sleep: cci2-sleep-state {
4822 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4823 /* cci_i2c_sda4, cci_i2c_scl4 */
4824 pins = "gpio117","gpio118";
4825 function = "cci_i2c";
4826 drive-strength = <2>;
4827 bias-pull-down;
4828 };
4829
4830 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4831 /* cci_i2c_sda5, cci_i2c_scl5 */
4832 pins = "gpio12","gpio13";
4833 function = "cci_i2c";
4834 drive-strength = <2>;
4835 bias-pull-down;
4836 };
4837 };
4838
4839 cci3_default: cci3-default-state {
4840 cci3_i2c0_default: cci3-i2c0-default-pins {
4841 /* cci_i2c_sda6, cci_i2c_scl6 */
4842 pins = "gpio145","gpio146";
4843 function = "cci_i2c";
4844 drive-strength = <2>;
4845 bias-pull-up;
4846 };
4847
4848 cci3_i2c1_default: cci3-i2c1-default-pins {
4849 /* cci_i2c_sda7, cci_i2c_scl7 */
4850 pins = "gpio164","gpio165";
4851 function = "cci_i2c";
4852 drive-strength = <2>;
4853 bias-pull-up;
4854 };
4855 };
4856
4857 cci3_sleep: cci3-sleep-state {
4858 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4859 /* cci_i2c_sda6, cci_i2c_scl6 */
4860 pins = "gpio145","gpio146";
4861 function = "cci_i2c";
4862 drive-strength = <2>;
4863 bias-pull-down;
4864 };
4865
4866 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4867 /* cci_i2c_sda7, cci_i2c_scl7 */
4868 pins = "gpio164","gpio165";
4869 function = "cci_i2c";
4870 drive-strength = <2>;
4871 bias-pull-down;
4872 };
4873 };
4874 };
4875
4876 apps_smmu: iommu@15000000 {
4877 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4878 reg = <0 0x15000000 0 0x100000>;
4879 #iommu-cells = <2>;
4880 #global-interrupts = <2>;
4881 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4882 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4883 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4884 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4885 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4886 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4887 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4889 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4890 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4891 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4892 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4893 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4894 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4895 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4896 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4897 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4898 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4899 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4900 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4901 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4902 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4903 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4904 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4905 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4906 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4907 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4908 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4911 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4912 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4913 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4914 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4915 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4916 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4917 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4918 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4919 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4920 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4921 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4922 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4924 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4925 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4926 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4927 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4928 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4929 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4930 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4931 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4932 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4933 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4935 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4936 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4937 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4938 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4939 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4940 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4941 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4942 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4943 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4946 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4948 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4949 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4950 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4951 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4952 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4954 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4955 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4956 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4957 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4959 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4960 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4961 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4962 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4963 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4965 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4966 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4967 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4968 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4969 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4970 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4971 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4974 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4975 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4976 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4977 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4978 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4979 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4980 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4981 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4982 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4985 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4986 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4987 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4988 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4989 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4990 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4991 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4992 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4993 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4994 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4995 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4996 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4997 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4998 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4999 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
5000 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
5001 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
5002 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
5003 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
5004 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
5005 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
5011 };
5012
5013 intc: interrupt-controller@17a00000 {
5014 compatible = "arm,gic-v3";
5015 interrupt-controller;
5016 #interrupt-cells = <3>;
5017 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
5018 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
5019 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-regions = <1>;
5021 redistributor-stride = <0 0x20000>;
5022
5023 #address-cells = <2>;
5024 #size-cells = <2>;
5025 ranges;
5026
5027 its: msi-controller@17a40000 {
5028 compatible = "arm,gic-v3-its";
5029 reg = <0 0x17a40000 0 0x20000>;
5030 msi-controller;
5031 #msi-cells = <1>;
5032 };
5033 };
5034
5035 watchdog@17c10000 {
5036 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
5037 reg = <0 0x17c10000 0 0x1000>;
5038 clocks = <&sleep_clk>;
5039 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5040 };
5041
5042 timer@17c20000 {
5043 compatible = "arm,armv7-timer-mem";
5044 reg = <0x0 0x17c20000 0x0 0x1000>;
5045 #address-cells = <1>;
5046 #size-cells = <1>;
5047 ranges = <0x0 0x0 0x0 0x20000000>;
5048
5049 frame@17c21000 {
5050 frame-number = <0>;
5051 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5052 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5053 reg = <0x17c21000 0x1000>,
5054 <0x17c22000 0x1000>;
5055 };
5056
5057 frame@17c23000 {
5058 frame-number = <1>;
5059 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5060 reg = <0x17c23000 0x1000>;
5061 status = "disabled";
5062 };
5063
5064 frame@17c25000 {
5065 frame-number = <2>;
5066 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5067 reg = <0x17c25000 0x1000>;
5068 status = "disabled";
5069 };
5070
5071 frame@17c27000 {
5072 frame-number = <3>;
5073 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5074 reg = <0x17c26000 0x1000>;
5075 status = "disabled";
5076 };
5077
5078 frame@17c29000 {
5079 frame-number = <4>;
5080 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5081 reg = <0x17c29000 0x1000>;
5082 status = "disabled";
5083 };
5084
5085 frame@17c2b000 {
5086 frame-number = <5>;
5087 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5088 reg = <0x17c2b000 0x1000>;
5089 status = "disabled";
5090 };
5091
5092 frame@17c2d000 {
5093 frame-number = <6>;
5094 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5095 reg = <0x17c2d000 0x1000>;
5096 status = "disabled";
5097 };
5098 };
5099
5100 apps_rsc: rsc@18200000 {
5101 compatible = "qcom,rpmh-rsc";
5102 reg = <0x0 0x18200000 0x0 0x10000>,
5103 <0x0 0x18210000 0x0 0x10000>,
5104 <0x0 0x18220000 0x0 0x10000>;
5105 reg-names = "drv-0", "drv-1", "drv-2";
5106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5109 qcom,tcs-offset = <0xd00>;
5110 qcom,drv-id = <2>;
5111 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5112 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5113 label = "apps_rsc";
5114 power-domains = <&CLUSTER_PD>;
5115
5116 apps_bcm_voter: bcm-voter {
5117 compatible = "qcom,bcm-voter";
5118 };
5119
5120 rpmhcc: clock-controller {
5121 compatible = "qcom,sc8280xp-rpmh-clk";
5122 #clock-cells = <1>;
5123 clock-names = "xo";
5124 clocks = <&xo_board_clk>;
5125 };
5126
5127 rpmhpd: power-controller {
5128 compatible = "qcom,sc8280xp-rpmhpd";
5129 #power-domain-cells = <1>;
5130 operating-points-v2 = <&rpmhpd_opp_table>;
5131
5132 rpmhpd_opp_table: opp-table {
5133 compatible = "operating-points-v2";
5134
5135 rpmhpd_opp_ret: opp1 {
5136 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5137 };
5138
5139 rpmhpd_opp_min_svs: opp2 {
5140 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5141 };
5142
5143 rpmhpd_opp_low_svs: opp3 {
5144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5145 };
5146
5147 rpmhpd_opp_svs: opp4 {
5148 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5149 };
5150
5151 rpmhpd_opp_svs_l1: opp5 {
5152 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5153 };
5154
5155 rpmhpd_opp_nom: opp6 {
5156 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5157 };
5158
5159 rpmhpd_opp_nom_l1: opp7 {
5160 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5161 };
5162
5163 rpmhpd_opp_nom_l2: opp8 {
5164 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5165 };
5166
5167 rpmhpd_opp_turbo: opp9 {
5168 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5169 };
5170
5171 rpmhpd_opp_turbo_l1: opp10 {
5172 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5173 };
5174 };
5175 };
5176 };
5177
5178 epss_l3: interconnect@18590000 {
5179 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
5180 reg = <0 0x18590000 0 0x1000>;
5181
5182 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5183 clock-names = "xo", "alternate";
5184
5185 #interconnect-cells = <1>;
5186 };
5187
5188 cpufreq_hw: cpufreq@18591000 {
5189 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
5190 reg = <0 0x18591000 0 0x1000>,
5191 <0 0x18592000 0 0x1000>;
5192 reg-names = "freq-domain0", "freq-domain1";
5193
5194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5195 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
5196 interrupt-names = "dcvsh-irq-0",
5197 "dcvsh-irq-1";
5198
5199 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5200 clock-names = "xo", "alternate";
5201
5202 #freq-domain-cells = <1>;
5203 #clock-cells = <1>;
5204 };
5205
5206 remoteproc_nsp0: remoteproc@1b300000 {
5207 compatible = "qcom,sc8280xp-nsp0-pas";
5208 reg = <0 0x1b300000 0 0x100>;
5209
5210 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
5211 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
5212 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5213 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
5214 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
5215 interrupt-names = "wdog", "fatal", "ready",
5216 "handover", "stop-ack";
5217
5218 clocks = <&rpmhcc RPMH_CXO_CLK>;
5219 clock-names = "xo";
5220
5221 power-domains = <&rpmhpd SC8280XP_NSP>;
5222 power-domain-names = "nsp";
5223
5224 memory-region = <&pil_nsp0_mem>;
5225
5226 qcom,smem-states = <&smp2p_nsp0_out 0>;
5227 qcom,smem-state-names = "stop";
5228
5229 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5230
5231 status = "disabled";
5232
5233 glink-edge {
5234 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5235 IPCC_MPROC_SIGNAL_GLINK_QMP
5236 IRQ_TYPE_EDGE_RISING>;
5237 mboxes = <&ipcc IPCC_CLIENT_CDSP
5238 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5239
5240 label = "nsp0";
5241 qcom,remote-pid = <5>;
5242
5243 fastrpc {
5244 compatible = "qcom,fastrpc";
5245 qcom,glink-channels = "fastrpcglink-apps-dsp";
5246 label = "cdsp";
5247 #address-cells = <1>;
5248 #size-cells = <0>;
5249
5250 compute-cb@1 {
5251 compatible = "qcom,fastrpc-compute-cb";
5252 reg = <1>;
5253 iommus = <&apps_smmu 0x3181 0x0420>;
5254 };
5255
5256 compute-cb@2 {
5257 compatible = "qcom,fastrpc-compute-cb";
5258 reg = <2>;
5259 iommus = <&apps_smmu 0x3182 0x0420>;
5260 };
5261
5262 compute-cb@3 {
5263 compatible = "qcom,fastrpc-compute-cb";
5264 reg = <3>;
5265 iommus = <&apps_smmu 0x3183 0x0420>;
5266 };
5267
5268 compute-cb@4 {
5269 compatible = "qcom,fastrpc-compute-cb";
5270 reg = <4>;
5271 iommus = <&apps_smmu 0x3184 0x0420>;
5272 };
5273
5274 compute-cb@5 {
5275 compatible = "qcom,fastrpc-compute-cb";
5276 reg = <5>;
5277 iommus = <&apps_smmu 0x3185 0x0420>;
5278 };
5279
5280 compute-cb@6 {
5281 compatible = "qcom,fastrpc-compute-cb";
5282 reg = <6>;
5283 iommus = <&apps_smmu 0x3186 0x0420>;
5284 };
5285
5286 compute-cb@7 {
5287 compatible = "qcom,fastrpc-compute-cb";
5288 reg = <7>;
5289 iommus = <&apps_smmu 0x3187 0x0420>;
5290 };
5291
5292 compute-cb@8 {
5293 compatible = "qcom,fastrpc-compute-cb";
5294 reg = <8>;
5295 iommus = <&apps_smmu 0x3188 0x0420>;
5296 };
5297
5298 compute-cb@9 {
5299 compatible = "qcom,fastrpc-compute-cb";
5300 reg = <9>;
5301 iommus = <&apps_smmu 0x318b 0x0420>;
5302 };
5303
5304 compute-cb@10 {
5305 compatible = "qcom,fastrpc-compute-cb";
5306 reg = <10>;
5307 iommus = <&apps_smmu 0x318b 0x0420>;
5308 };
5309
5310 compute-cb@11 {
5311 compatible = "qcom,fastrpc-compute-cb";
5312 reg = <11>;
5313 iommus = <&apps_smmu 0x318c 0x0420>;
5314 };
5315
5316 compute-cb@12 {
5317 compatible = "qcom,fastrpc-compute-cb";
5318 reg = <12>;
5319 iommus = <&apps_smmu 0x318d 0x0420>;
5320 };
5321
5322 compute-cb@13 {
5323 compatible = "qcom,fastrpc-compute-cb";
5324 reg = <13>;
5325 iommus = <&apps_smmu 0x318e 0x0420>;
5326 };
5327
5328 compute-cb@14 {
5329 compatible = "qcom,fastrpc-compute-cb";
5330 reg = <14>;
5331 iommus = <&apps_smmu 0x318f 0x0420>;
5332 };
5333 };
5334 };
5335 };
5336
5337 remoteproc_nsp1: remoteproc@21300000 {
5338 compatible = "qcom,sc8280xp-nsp1-pas";
5339 reg = <0 0x21300000 0 0x100>;
5340
5341 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
5342 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5343 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5344 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5345 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5346 interrupt-names = "wdog", "fatal", "ready",
5347 "handover", "stop-ack";
5348
5349 clocks = <&rpmhcc RPMH_CXO_CLK>;
5350 clock-names = "xo";
5351
5352 power-domains = <&rpmhpd SC8280XP_NSP>;
5353 power-domain-names = "nsp";
5354
5355 memory-region = <&pil_nsp1_mem>;
5356
5357 qcom,smem-states = <&smp2p_nsp1_out 0>;
5358 qcom,smem-state-names = "stop";
5359
5360 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5361
5362 status = "disabled";
5363
5364 glink-edge {
5365 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5366 IPCC_MPROC_SIGNAL_GLINK_QMP
5367 IRQ_TYPE_EDGE_RISING>;
5368 mboxes = <&ipcc IPCC_CLIENT_NSP1
5369 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5370
5371 label = "nsp1";
5372 qcom,remote-pid = <12>;
5373 };
5374 };
5375
5376 mdss1: display-subsystem@22000000 {
5377 compatible = "qcom,sc8280xp-mdss";
5378 reg = <0 0x22000000 0 0x1000>;
5379 reg-names = "mdss";
5380
5381 clocks = <&gcc GCC_DISP_AHB_CLK>,
5382 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5383 <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5384 clock-names = "iface",
5385 "ahb",
5386 "core";
5387 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5388 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5389 interconnect-names = "mdp0-mem", "mdp1-mem";
5390 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5391
5392 iommus = <&apps_smmu 0x1800 0x402>;
5393 power-domains = <&dispcc1 MDSS_GDSC>;
5394 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5395
5396 interrupt-controller;
5397 #interrupt-cells = <1>;
5398 #address-cells = <2>;
5399 #size-cells = <2>;
5400 ranges;
5401
5402 status = "disabled";
5403
5404 mdss1_mdp: display-controller@22001000 {
5405 compatible = "qcom,sc8280xp-dpu";
5406 reg = <0 0x22001000 0 0x8f000>,
5407 <0 0x220b0000 0 0x2008>;
5408 reg-names = "mdp", "vbif";
5409
5410 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411 <&gcc GCC_DISP_SF_AXI_CLK>,
5412 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5413 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5414 <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5415 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5416 clock-names = "bus",
5417 "nrt_bus",
5418 "iface",
5419 "lut",
5420 "core",
5421 "vsync";
5422 interrupt-parent = <&mdss1>;
5423 interrupts = <0>;
5424 power-domains = <&rpmhpd SC8280XP_MMCX>;
5425
5426 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5427 assigned-clock-rates = <19200000>;
5428 operating-points-v2 = <&mdss1_mdp_opp_table>;
5429
5430 ports {
5431 #address-cells = <1>;
5432 #size-cells = <0>;
5433
5434 port@0 {
5435 reg = <0>;
5436 mdss1_intf0_out: endpoint {
5437 remote-endpoint = <&mdss1_dp0_in>;
5438 };
5439 };
5440
5441 port@4 {
5442 reg = <4>;
5443 mdss1_intf4_out: endpoint {
5444 remote-endpoint = <&mdss1_dp1_in>;
5445 };
5446 };
5447
5448 port@5 {
5449 reg = <5>;
5450 mdss1_intf5_out: endpoint {
5451 remote-endpoint = <&mdss1_dp3_in>;
5452 };
5453 };
5454
5455 port@6 {
5456 reg = <6>;
5457 mdss1_intf6_out: endpoint {
5458 remote-endpoint = <&mdss1_dp2_in>;
5459 };
5460 };
5461 };
5462
5463 mdss1_mdp_opp_table: opp-table {
5464 compatible = "operating-points-v2";
5465
5466 opp-200000000 {
5467 opp-hz = /bits/ 64 <200000000>;
5468 required-opps = <&rpmhpd_opp_low_svs>;
5469 };
5470
5471 opp-300000000 {
5472 opp-hz = /bits/ 64 <300000000>;
5473 required-opps = <&rpmhpd_opp_svs>;
5474 };
5475
5476 opp-375000000 {
5477 opp-hz = /bits/ 64 <375000000>;
5478 required-opps = <&rpmhpd_opp_svs_l1>;
5479 };
5480
5481 opp-500000000 {
5482 opp-hz = /bits/ 64 <500000000>;
5483 required-opps = <&rpmhpd_opp_nom>;
5484 };
5485 opp-600000000 {
5486 opp-hz = /bits/ 64 <600000000>;
5487 required-opps = <&rpmhpd_opp_turbo_l1>;
5488 };
5489 };
5490 };
5491
5492 mdss1_dp0: displayport-controller@22090000 {
5493 compatible = "qcom,sc8280xp-dp";
5494 reg = <0 0x22090000 0 0x200>,
5495 <0 0x22090200 0 0x200>,
5496 <0 0x22090400 0 0x600>,
5497 <0 0x22091000 0 0x400>,
5498 <0 0x22091400 0 0x400>;
5499
5500 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5501 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5502 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5503 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5504 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5505 clock-names = "core_iface", "core_aux",
5506 "ctrl_link",
5507 "ctrl_link_iface", "stream_pixel";
5508 interrupt-parent = <&mdss1>;
5509 interrupts = <12>;
5510 phys = <&mdss1_dp0_phy>;
5511 phy-names = "dp";
5512 power-domains = <&rpmhpd SC8280XP_MMCX>;
5513
5514 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5515 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5516 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5517 operating-points-v2 = <&mdss1_dp0_opp_table>;
5518
5519 #sound-dai-cells = <0>;
5520
5521 status = "disabled";
5522
5523 ports {
5524 #address-cells = <1>;
5525 #size-cells = <0>;
5526
5527 port@0 {
5528 reg = <0>;
5529 mdss1_dp0_in: endpoint {
5530 remote-endpoint = <&mdss1_intf0_out>;
5531 };
5532 };
5533
5534 port@1 {
5535 reg = <1>;
5536 };
5537 };
5538
5539 mdss1_dp0_opp_table: opp-table {
5540 compatible = "operating-points-v2";
5541
5542 opp-160000000 {
5543 opp-hz = /bits/ 64 <160000000>;
5544 required-opps = <&rpmhpd_opp_low_svs>;
5545 };
5546
5547 opp-270000000 {
5548 opp-hz = /bits/ 64 <270000000>;
5549 required-opps = <&rpmhpd_opp_svs>;
5550 };
5551
5552 opp-540000000 {
5553 opp-hz = /bits/ 64 <540000000>;
5554 required-opps = <&rpmhpd_opp_svs_l1>;
5555 };
5556
5557 opp-810000000 {
5558 opp-hz = /bits/ 64 <810000000>;
5559 required-opps = <&rpmhpd_opp_nom>;
5560 };
5561 };
5562 };
5563
5564 mdss1_dp1: displayport-controller@22098000 {
5565 compatible = "qcom,sc8280xp-dp";
5566 reg = <0 0x22098000 0 0x200>,
5567 <0 0x22098200 0 0x200>,
5568 <0 0x22098400 0 0x600>,
5569 <0 0x22099000 0 0x400>,
5570 <0 0x22099400 0 0x400>;
5571
5572 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5573 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5574 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5575 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5576 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5577 clock-names = "core_iface", "core_aux",
5578 "ctrl_link",
5579 "ctrl_link_iface", "stream_pixel";
5580 interrupt-parent = <&mdss1>;
5581 interrupts = <13>;
5582 phys = <&mdss1_dp1_phy>;
5583 phy-names = "dp";
5584 power-domains = <&rpmhpd SC8280XP_MMCX>;
5585
5586 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5587 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5588 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5589 operating-points-v2 = <&mdss1_dp1_opp_table>;
5590
5591 #sound-dai-cells = <0>;
5592
5593 status = "disabled";
5594
5595 ports {
5596 #address-cells = <1>;
5597 #size-cells = <0>;
5598
5599 port@0 {
5600 reg = <0>;
5601 mdss1_dp1_in: endpoint {
5602 remote-endpoint = <&mdss1_intf4_out>;
5603 };
5604 };
5605
5606 port@1 {
5607 reg = <1>;
5608 };
5609 };
5610
5611 mdss1_dp1_opp_table: opp-table {
5612 compatible = "operating-points-v2";
5613
5614 opp-160000000 {
5615 opp-hz = /bits/ 64 <160000000>;
5616 required-opps = <&rpmhpd_opp_low_svs>;
5617 };
5618
5619 opp-270000000 {
5620 opp-hz = /bits/ 64 <270000000>;
5621 required-opps = <&rpmhpd_opp_svs>;
5622 };
5623
5624 opp-540000000 {
5625 opp-hz = /bits/ 64 <540000000>;
5626 required-opps = <&rpmhpd_opp_svs_l1>;
5627 };
5628
5629 opp-810000000 {
5630 opp-hz = /bits/ 64 <810000000>;
5631 required-opps = <&rpmhpd_opp_nom>;
5632 };
5633 };
5634 };
5635
5636 mdss1_dp2: displayport-controller@2209a000 {
5637 compatible = "qcom,sc8280xp-dp";
5638 reg = <0 0x2209a000 0 0x200>,
5639 <0 0x2209a200 0 0x200>,
5640 <0 0x2209a400 0 0x600>,
5641 <0 0x2209b000 0 0x400>,
5642 <0 0x2209b400 0 0x400>;
5643
5644 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5645 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5646 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5647 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5648 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5649 clock-names = "core_iface", "core_aux",
5650 "ctrl_link",
5651 "ctrl_link_iface", "stream_pixel";
5652 interrupt-parent = <&mdss1>;
5653 interrupts = <14>;
5654 phys = <&mdss1_dp2_phy>;
5655 phy-names = "dp";
5656 power-domains = <&rpmhpd SC8280XP_MMCX>;
5657
5658 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5659 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5660 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5661 operating-points-v2 = <&mdss1_dp2_opp_table>;
5662
5663 #sound-dai-cells = <0>;
5664
5665 status = "disabled";
5666
5667 ports {
5668 #address-cells = <1>;
5669 #size-cells = <0>;
5670
5671 port@0 {
5672 reg = <0>;
5673 mdss1_dp2_in: endpoint {
5674 remote-endpoint = <&mdss1_intf6_out>;
5675 };
5676 };
5677
5678 port@1 {
5679 reg = <1>;
5680 };
5681 };
5682
5683 mdss1_dp2_opp_table: opp-table {
5684 compatible = "operating-points-v2";
5685
5686 opp-160000000 {
5687 opp-hz = /bits/ 64 <160000000>;
5688 required-opps = <&rpmhpd_opp_low_svs>;
5689 };
5690
5691 opp-270000000 {
5692 opp-hz = /bits/ 64 <270000000>;
5693 required-opps = <&rpmhpd_opp_svs>;
5694 };
5695
5696 opp-540000000 {
5697 opp-hz = /bits/ 64 <540000000>;
5698 required-opps = <&rpmhpd_opp_svs_l1>;
5699 };
5700
5701 opp-810000000 {
5702 opp-hz = /bits/ 64 <810000000>;
5703 required-opps = <&rpmhpd_opp_nom>;
5704 };
5705 };
5706 };
5707
5708 mdss1_dp3: displayport-controller@220a0000 {
5709 compatible = "qcom,sc8280xp-dp";
5710 reg = <0 0x220a0000 0 0x200>,
5711 <0 0x220a0200 0 0x200>,
5712 <0 0x220a0400 0 0x600>,
5713 <0 0x220a1000 0 0x400>,
5714 <0 0x220a1400 0 0x400>;
5715
5716 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5717 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5718 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5719 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5720 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5721 clock-names = "core_iface", "core_aux",
5722 "ctrl_link",
5723 "ctrl_link_iface", "stream_pixel";
5724 interrupt-parent = <&mdss1>;
5725 interrupts = <15>;
5726 phys = <&mdss1_dp3_phy>;
5727 phy-names = "dp";
5728 power-domains = <&rpmhpd SC8280XP_MMCX>;
5729
5730 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5731 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5732 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5733 operating-points-v2 = <&mdss1_dp3_opp_table>;
5734
5735 #sound-dai-cells = <0>;
5736
5737 status = "disabled";
5738
5739 ports {
5740 #address-cells = <1>;
5741 #size-cells = <0>;
5742
5743 port@0 {
5744 reg = <0>;
5745 mdss1_dp3_in: endpoint {
5746 remote-endpoint = <&mdss1_intf5_out>;
5747 };
5748 };
5749
5750 port@1 {
5751 reg = <1>;
5752 };
5753 };
5754
5755 mdss1_dp3_opp_table: opp-table {
5756 compatible = "operating-points-v2";
5757
5758 opp-160000000 {
5759 opp-hz = /bits/ 64 <160000000>;
5760 required-opps = <&rpmhpd_opp_low_svs>;
5761 };
5762
5763 opp-270000000 {
5764 opp-hz = /bits/ 64 <270000000>;
5765 required-opps = <&rpmhpd_opp_svs>;
5766 };
5767
5768 opp-540000000 {
5769 opp-hz = /bits/ 64 <540000000>;
5770 required-opps = <&rpmhpd_opp_svs_l1>;
5771 };
5772
5773 opp-810000000 {
5774 opp-hz = /bits/ 64 <810000000>;
5775 required-opps = <&rpmhpd_opp_nom>;
5776 };
5777 };
5778 };
5779 };
5780
5781 mdss1_dp2_phy: phy@220c2a00 {
5782 compatible = "qcom,sc8280xp-dp-phy";
5783 reg = <0 0x220c2a00 0 0x19c>,
5784 <0 0x220c2200 0 0xec>,
5785 <0 0x220c2600 0 0xec>,
5786 <0 0x220c2000 0 0x1c8>;
5787
5788 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5789 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5790 clock-names = "aux", "cfg_ahb";
5791 power-domains = <&rpmhpd SC8280XP_MX>;
5792
5793 #clock-cells = <1>;
5794 #phy-cells = <0>;
5795
5796 status = "disabled";
5797 };
5798
5799 mdss1_dp3_phy: phy@220c5a00 {
5800 compatible = "qcom,sc8280xp-dp-phy";
5801 reg = <0 0x220c5a00 0 0x19c>,
5802 <0 0x220c5200 0 0xec>,
5803 <0 0x220c5600 0 0xec>,
5804 <0 0x220c5000 0 0x1c8>;
5805
5806 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5807 <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5808 clock-names = "aux", "cfg_ahb";
5809 power-domains = <&rpmhpd SC8280XP_MX>;
5810
5811 #clock-cells = <1>;
5812 #phy-cells = <0>;
5813
5814 status = "disabled";
5815 };
5816
5817 dispcc1: clock-controller@22100000 {
5818 compatible = "qcom,sc8280xp-dispcc1";
5819 reg = <0 0x22100000 0 0x20000>;
5820
5821 clocks = <&gcc GCC_DISP_AHB_CLK>,
5822 <&rpmhcc RPMH_CXO_CLK>,
5823 <0>,
5824 <&mdss1_dp0_phy 0>,
5825 <&mdss1_dp0_phy 1>,
5826 <&mdss1_dp1_phy 0>,
5827 <&mdss1_dp1_phy 1>,
5828 <&mdss1_dp2_phy 0>,
5829 <&mdss1_dp2_phy 1>,
5830 <&mdss1_dp3_phy 0>,
5831 <&mdss1_dp3_phy 1>,
5832 <0>,
5833 <0>,
5834 <0>,
5835 <0>;
5836 power-domains = <&rpmhpd SC8280XP_MMCX>;
5837
5838 #clock-cells = <1>;
5839 #power-domain-cells = <1>;
5840 #reset-cells = <1>;
5841
5842 status = "disabled";
5843 };
5844
5845 ethernet1: ethernet@23000000 {
5846 compatible = "qcom,sc8280xp-ethqos";
5847 reg = <0x0 0x23000000 0x0 0x10000>,
5848 <0x0 0x23016000 0x0 0x100>;
5849 reg-names = "stmmaceth", "rgmii";
5850
5851 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5852 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5853 <&gcc GCC_EMAC1_PTP_CLK>,
5854 <&gcc GCC_EMAC1_RGMII_CLK>;
5855 clock-names = "stmmaceth",
5856 "pclk",
5857 "ptp_ref",
5858 "rgmii";
5859
5860 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5862 interrupt-names = "macirq", "eth_lpi";
5863
5864 iommus = <&apps_smmu 0x40 0xf>;
5865 power-domains = <&gcc EMAC_1_GDSC>;
5866
5867 snps,tso;
5868 snps,pbl = <32>;
5869 rx-fifo-depth = <4096>;
5870 tx-fifo-depth = <4096>;
5871
5872 status = "disabled";
5873 };
5874 };
5875
5876 sound: sound {
5877 };
5878
5879 thermal-zones {
5880 cpu0-thermal {
5881 polling-delay-passive = <250>;
5882
5883 thermal-sensors = <&tsens0 1>;
5884
5885 trips {
5886 cpu-crit {
5887 temperature = <110000>;
5888 hysteresis = <1000>;
5889 type = "critical";
5890 };
5891 };
5892 };
5893
5894 cpu1-thermal {
5895 polling-delay-passive = <250>;
5896
5897 thermal-sensors = <&tsens0 2>;
5898
5899 trips {
5900 cpu-crit {
5901 temperature = <110000>;
5902 hysteresis = <1000>;
5903 type = "critical";
5904 };
5905 };
5906 };
5907
5908 cpu2-thermal {
5909 polling-delay-passive = <250>;
5910
5911 thermal-sensors = <&tsens0 3>;
5912
5913 trips {
5914 cpu-crit {
5915 temperature = <110000>;
5916 hysteresis = <1000>;
5917 type = "critical";
5918 };
5919 };
5920 };
5921
5922 cpu3-thermal {
5923 polling-delay-passive = <250>;
5924
5925 thermal-sensors = <&tsens0 4>;
5926
5927 trips {
5928 cpu-crit {
5929 temperature = <110000>;
5930 hysteresis = <1000>;
5931 type = "critical";
5932 };
5933 };
5934 };
5935
5936 cpu4-thermal {
5937 polling-delay-passive = <250>;
5938
5939 thermal-sensors = <&tsens0 5>;
5940
5941 trips {
5942 cpu-crit {
5943 temperature = <110000>;
5944 hysteresis = <1000>;
5945 type = "critical";
5946 };
5947 };
5948 };
5949
5950 cpu5-thermal {
5951 polling-delay-passive = <250>;
5952
5953 thermal-sensors = <&tsens0 6>;
5954
5955 trips {
5956 cpu-crit {
5957 temperature = <110000>;
5958 hysteresis = <1000>;
5959 type = "critical";
5960 };
5961 };
5962 };
5963
5964 cpu6-thermal {
5965 polling-delay-passive = <250>;
5966
5967 thermal-sensors = <&tsens0 7>;
5968
5969 trips {
5970 cpu-crit {
5971 temperature = <110000>;
5972 hysteresis = <1000>;
5973 type = "critical";
5974 };
5975 };
5976 };
5977
5978 cpu7-thermal {
5979 polling-delay-passive = <250>;
5980
5981 thermal-sensors = <&tsens0 8>;
5982
5983 trips {
5984 cpu-crit {
5985 temperature = <110000>;
5986 hysteresis = <1000>;
5987 type = "critical";
5988 };
5989 };
5990 };
5991
5992 cluster0-thermal {
5993 polling-delay-passive = <250>;
5994
5995 thermal-sensors = <&tsens0 9>;
5996
5997 trips {
5998 cpu-crit {
5999 temperature = <110000>;
6000 hysteresis = <1000>;
6001 type = "critical";
6002 };
6003 };
6004 };
6005
6006 gpu-thermal {
6007 polling-delay-passive = <250>;
6008
6009 thermal-sensors = <&tsens2 2>;
6010
6011 cooling-maps {
6012 map0 {
6013 trip = <&gpu_alert0>;
6014 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6015 };
6016 };
6017
6018 trips {
6019 gpu_alert0: trip-point0 {
6020 temperature = <85000>;
6021 hysteresis = <1000>;
6022 type = "passive";
6023 };
6024
6025 trip-point1 {
6026 temperature = <110000>;
6027 hysteresis = <1000>;
6028 type = "critical";
6029 };
6030 };
6031 };
6032
6033 mem-thermal {
6034 polling-delay-passive = <250>;
6035
6036 thermal-sensors = <&tsens1 15>;
6037
6038 trips {
6039 trip-point0 {
6040 temperature = <90000>;
6041 hysteresis = <2000>;
6042 type = "hot";
6043 };
6044 };
6045 };
6046 };
6047
6048 timer {
6049 compatible = "arm,armv8-timer";
6050 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6051 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6052 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6053 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6054 };
6055 };
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