1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */
6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/soc/qcom,apr.h>
18
19 / {
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 aliases {
26 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2;
28 };
29
30 chosen { };
31
32 clocks {
33 xo_board: xo-board {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <19200000>;
37 clock-output-names = "xo_board";
38 };
39
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32764>;
44 clock-output-names = "sleep_clk";
45 };
46 };
47
48 cpus {
49 #address-cells = <2>;
50 #size-cells = <0>;
51
52 CPU0: cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>;
56 enable-method = "psci";
57 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 &PERF_CPU_SLEEP_1
59 &PERF_CLUSTER_SLEEP_0
60 &PERF_CLUSTER_SLEEP_1
61 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 };
70 };
71
72 CPU1: cpu@101 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>;
76 enable-method = "psci";
77 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 &PERF_CPU_SLEEP_1
79 &PERF_CLUSTER_SLEEP_0
80 &PERF_CLUSTER_SLEEP_1
81 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>;
84 next-level-cache = <&L2_1>;
85 };
86
87 CPU2: cpu@102 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>;
91 enable-method = "psci";
92 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 &PERF_CPU_SLEEP_1
94 &PERF_CLUSTER_SLEEP_0
95 &PERF_CLUSTER_SLEEP_1
96 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>;
99 next-level-cache = <&L2_1>;
100 };
101
102 CPU3: cpu@103 {
103 device_type = "cpu";
104 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>;
106 enable-method = "psci";
107 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 &PERF_CPU_SLEEP_1
109 &PERF_CLUSTER_SLEEP_0
110 &PERF_CLUSTER_SLEEP_1
111 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>;
114 next-level-cache = <&L2_1>;
115 };
116
117 CPU4: cpu@0 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>;
121 enable-method = "psci";
122 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 &PWR_CPU_SLEEP_1
124 &PWR_CLUSTER_SLEEP_0
125 &PWR_CLUSTER_SLEEP_1
126 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>;
129 next-level-cache = <&L2_0>;
130 L2_0: l2-cache {
131 compatible = "cache";
132 cache-level = <2>;
133 cache-unified;
134 };
135 };
136
137 CPU5: cpu@1 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>;
141 enable-method = "psci";
142 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 &PWR_CPU_SLEEP_1
144 &PWR_CLUSTER_SLEEP_0
145 &PWR_CLUSTER_SLEEP_1
146 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>;
149 next-level-cache = <&L2_0>;
150 };
151
152 CPU6: cpu@2 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>;
156 enable-method = "psci";
157 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 &PWR_CPU_SLEEP_1
159 &PWR_CLUSTER_SLEEP_0
160 &PWR_CLUSTER_SLEEP_1
161 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>;
164 next-level-cache = <&L2_0>;
165 };
166
167 CPU7: cpu@3 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>;
171 enable-method = "psci";
172 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 &PWR_CPU_SLEEP_1
174 &PWR_CLUSTER_SLEEP_0
175 &PWR_CLUSTER_SLEEP_1
176 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>;
179 next-level-cache = <&L2_0>;
180 };
181
182 cpu-map {
183 cluster0 {
184 core0 {
185 cpu = <&CPU4>;
186 };
187
188 core1 {
189 cpu = <&CPU5>;
190 };
191
192 core2 {
193 cpu = <&CPU6>;
194 };
195
196 core3 {
197 cpu = <&CPU7>;
198 };
199 };
200
201 cluster1 {
202 core0 {
203 cpu = <&CPU0>;
204 };
205
206 core1 {
207 cpu = <&CPU1>;
208 };
209
210 core2 {
211 cpu = <&CPU2>;
212 };
213
214 core3 {
215 cpu = <&CPU3>;
216 };
217 };
218 };
219
220 idle-states {
221 entry-method = "psci";
222
223 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = "arm,idle-state";
225 idle-state-name = "pwr-retention";
226 arm,psci-suspend-param = <0x40000002>;
227 entry-latency-us = <338>;
228 exit-latency-us = <423>;
229 min-residency-us = <200>;
230 };
231
232 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = "arm,idle-state";
234 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspend-param = <0x40000003>;
236 entry-latency-us = <515>;
237 exit-latency-us = <1821>;
238 min-residency-us = <1000>;
239 local-timer-stop;
240 };
241
242 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = "arm,idle-state";
244 idle-state-name = "perf-retention";
245 arm,psci-suspend-param = <0x40000002>;
246 entry-latency-us = <154>;
247 exit-latency-us = <87>;
248 min-residency-us = <200>;
249 };
250
251 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = "arm,idle-state";
253 idle-state-name = "perf-power-collapse";
254 arm,psci-suspend-param = <0x40000003>;
255 entry-latency-us = <262>;
256 exit-latency-us = <301>;
257 min-residency-us = <1000>;
258 local-timer-stop;
259 };
260
261 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency-us = <284>;
266 exit-latency-us = <384>;
267 min-residency-us = <9987>;
268 local-timer-stop;
269 };
270
271 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = "arm,idle-state";
273 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency-us = <338>;
276 exit-latency-us = <423>;
277 min-residency-us = <9987>;
278 local-timer-stop;
279 };
280
281 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = "arm,idle-state";
283 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency-us = <515>;
286 exit-latency-us = <1821>;
287 min-residency-us = <9987>;
288 local-timer-stop;
289 };
290
291 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = "arm,idle-state";
293 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency-us = <272>;
296 exit-latency-us = <329>;
297 min-residency-us = <9987>;
298 local-timer-stop;
299 };
300
301 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = "arm,idle-state";
303 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency-us = <332>;
306 exit-latency-us = <368>;
307 min-residency-us = <9987>;
308 local-timer-stop;
309 };
310
311 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = "arm,idle-state";
313 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency-us = <545>;
316 exit-latency-us = <1609>;
317 min-residency-us = <9987>;
318 local-timer-stop;
319 };
320 };
321 };
322
323 firmware {
324 scm {
325 compatible = "qcom,scm-msm8998", "qcom,scm";
326 };
327 };
328
329 memory@80000000 {
330 device_type = "memory";
331 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0>;
333 };
334
335 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points-v2";
337
338 opp-131250000 {
339 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmpd_opp_svs>;
341 };
342
343 opp-210000000 {
344 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmpd_opp_svs_plus>;
346 };
347
348 opp-262500000 {
349 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmpd_opp_nom>;
351 };
352 };
353
354 pmu {
355 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 };
358
359 psci {
360 compatible = "arm,psci-1.0";
361 method = "smc";
362 };
363
364 rpm: remoteproc {
365 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
366
367 glink-edge {
368 compatible = "qcom,glink-rpm";
369
370 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
371 qcom,rpm-msg-ram = <&rpm_msg_ram>;
372 mboxes = <&apcs_glb 0>;
373
374 rpm_requests: rpm-requests {
375 compatible = "qcom,rpm-sdm660";
376 qcom,glink-channels = "rpm_requests";
377
378 rpmcc: clock-controller {
379 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
380 #clock-cells = <1>;
381 };
382
383 rpmpd: power-controller {
384 compatible = "qcom,sdm660-rpmpd";
385 #power-domain-cells = <1>;
386 operating-points-v2 = <&rpmpd_opp_table>;
387
388 rpmpd_opp_table: opp-table {
389 compatible = "operating-points-v2";
390
391 rpmpd_opp_ret: opp1 {
392 opp-level = <RPM_SMD_LEVEL_RETENTION>;
393 };
394
395 rpmpd_opp_ret_plus: opp2 {
396 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
397 };
398
399 rpmpd_opp_min_svs: opp3 {
400 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401 };
402
403 rpmpd_opp_low_svs: opp4 {
404 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405 };
406
407 rpmpd_opp_svs: opp5 {
408 opp-level = <RPM_SMD_LEVEL_SVS>;
409 };
410
411 rpmpd_opp_svs_plus: opp6 {
412 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413 };
414
415 rpmpd_opp_nom: opp7 {
416 opp-level = <RPM_SMD_LEVEL_NOM>;
417 };
418
419 rpmpd_opp_nom_plus: opp8 {
420 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421 };
422
423 rpmpd_opp_turbo: opp9 {
424 opp-level = <RPM_SMD_LEVEL_TURBO>;
425 };
426 };
427 };
428 };
429 };
430 };
431
432 reserved-memory {
433 #address-cells = <2>;
434 #size-cells = <2>;
435 ranges;
436
437 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map;
440 };
441
442 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map;
445 };
446
447 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 0x0 0x600000>;
449 no-map;
450 };
451
452 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmtfs-mem";
454 reg = <0x0 0x85e00000 0x0 0x200000>;
455 no-map;
456
457 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
459 };
460
461 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 0x200000>;
463 no-map;
464 };
465
466 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map;
469 };
470
471 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map;
474 };
475
476 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map;
479 };
480
481 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map;
484 };
485
486 buffer_mem: tzbuffer@94a00000 {
487 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map;
489 };
490
491 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map;
494 };
495
496 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map;
499 };
500
501 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map;
504 };
505
506 zap_shader_region: gpu@fed00000 {
507 compatible = "shared-dma-pool";
508 reg = <0x0 0xfed00000 0x0 0xa00000>;
509 no-map;
510 };
511 };
512
513 smem: smem {
514 compatible = "qcom,smem";
515 memory-region = <&smem_region>;
516 hwlocks = <&tcsr_mutex 3>;
517 };
518
519 smp2p-adsp {
520 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
523 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>;
526
527 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells = <1>;
530 };
531
532 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "slave-kernel";
534 interrupt-controller;
535 #interrupt-cells = <2>;
536 };
537 };
538
539 smp2p-mpss {
540 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>;
546
547 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells = <1>;
550 };
551
552 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "slave-kernel";
554 interrupt-controller;
555 #interrupt-cells = <2>;
556 };
557 };
558
559 soc@0 {
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus";
564
565 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>;
568 #reset-cells = <1>;
569 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94000>;
571
572 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>,
574 <&sleep_clk>;
575 };
576
577 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x7000>;
580 };
581
582 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
584 reg = <0x00780000 0x621c>;
585 #address-cells = <1>;
586 #size-cells = <1>;
587
588 qusb2_hstx_trim: hstx-trim@240 {
589 reg = <0x243 0x1>;
590 bits = <1 3>;
591 };
592
593 gpu_speed_bin: gpu-speed-bin@41a0 {
594 reg = <0x41a2 0x1>;
595 bits = <5 7>;
596 };
597 };
598
599 rng: rng@793000 {
600 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core";
604 };
605
606 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm660-bimc";
608 reg = <0x01008000 0x78000>;
609 #interconnect-cells = <1>;
610 };
611
612 restart@10ac000 {
613 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4>;
615 };
616
617 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm660-cnoc";
619 reg = <0x01500000 0x10000>;
620 #interconnect-cells = <1>;
621 };
622
623 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm660-snoc";
625 reg = <0x01626000 0x7090>;
626 #interconnect-cells = <1>;
627 };
628
629 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40000>;
632 #global-interrupts = <2>;
633 #iommu-cells = <1>;
634
635 interrupts =
636 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638
639 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668
669 status = "disabled";
670 };
671
672 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm660-a2noc";
674 reg = <0x01704000 0xc100>;
675 #interconnect-cells = <1>;
676 clock-names = "ipa",
677 "ufs_axi",
678 "aggre2_ufs_axi",
679 "aggre2_usb3_axi",
680 "cfg_noc_usb2_axi";
681 clocks = <&rpmcc RPM_SMD_IPA_CLK>,
682 <&gcc GCC_UFS_AXI_CLK>,
683 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
684 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
685 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
686 };
687
688 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm660-mnoc";
690 reg = <0x01745000 0xa010>;
691 #interconnect-cells = <1>;
692 clock-names = "iface";
693 clocks = <&mmcc AHB_CLK_SRC>;
694 };
695
696 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
698 reg = <0x010ae000 0x1000>, /* TM */
699 <0x010ad000 0x1000>; /* SROT */
700 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells = <1>;
705 };
706
707 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcsr-mutex";
709 reg = <0x01f40000 0x20000>;
710 #hwlock-cells = <1>;
711 };
712
713 tcsr_regs_1: syscon@1f60000 {
714 compatible = "qcom,sdm630-tcsr", "syscon";
715 reg = <0x01f60000 0x20000>;
716 };
717
718 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x400000>,
721 <0x03500000 0x400000>,
722 <0x03900000 0x400000>;
723 reg-names = "south", "center", "north";
724 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller;
726 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>;
728 interrupt-controller;
729 #interrupt-cells = <2>;
730
731 blsp1_uart1_default: blsp1-uart1-default-state {
732 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "blsp_uart1";
734 drive-strength = <2>;
735 bias-disable;
736 };
737
738 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
739 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gpio";
741 drive-strength = <2>;
742 bias-disable;
743 };
744
745 blsp1_uart2_default: blsp1-uart2-default-state {
746 pins = "gpio4", "gpio5";
747 function = "blsp_uart2";
748 drive-strength = <2>;
749 bias-disable;
750 };
751
752 blsp2_uart1_default: blsp2-uart1-active-state {
753 tx-rts-pins {
754 pins = "gpio16", "gpio19";
755 function = "blsp_uart5";
756 drive-strength = <2>;
757 bias-disable;
758 };
759
760 rx-pins {
761 /*
762 * Avoid garbage data while BT module
763 * is powered off or not driving signal
764 */
765 pins = "gpio17";
766 function = "blsp_uart5";
767 drive-strength = <2>;
768 bias-pull-up;
769 };
770
771 cts-pins {
772 /* Match the pull of the BT module */
773 pins = "gpio18";
774 function = "blsp_uart5";
775 drive-strength = <2>;
776 bias-pull-down;
777 };
778 };
779
780 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
781 tx-pins {
782 pins = "gpio16";
783 function = "gpio";
784 drive-strength = <2>;
785 bias-pull-up;
786 };
787
788 rx-cts-rts-pins {
789 pins = "gpio17", "gpio18", "gpio19";
790 function = "gpio";
791 drive-strength = <2>;
792 bias-disable;
793 };
794 };
795
796 i2c1_default: i2c1-default-state {
797 pins = "gpio2", "gpio3";
798 function = "blsp_i2c1";
799 drive-strength = <2>;
800 bias-disable;
801 };
802
803 i2c1_sleep: i2c1-sleep-state {
804 pins = "gpio2", "gpio3";
805 function = "blsp_i2c1";
806 drive-strength = <2>;
807 bias-pull-up;
808 };
809
810 i2c2_default: i2c2-default-state {
811 pins = "gpio6", "gpio7";
812 function = "blsp_i2c2";
813 drive-strength = <2>;
814 bias-disable;
815 };
816
817 i2c2_sleep: i2c2-sleep-state {
818 pins = "gpio6", "gpio7";
819 function = "blsp_i2c2";
820 drive-strength = <2>;
821 bias-pull-up;
822 };
823
824 i2c3_default: i2c3-default-state {
825 pins = "gpio10", "gpio11";
826 function = "blsp_i2c3";
827 drive-strength = <2>;
828 bias-disable;
829 };
830
831 i2c3_sleep: i2c3-sleep-state {
832 pins = "gpio10", "gpio11";
833 function = "blsp_i2c3";
834 drive-strength = <2>;
835 bias-pull-up;
836 };
837
838 i2c4_default: i2c4-default-state {
839 pins = "gpio14", "gpio15";
840 function = "blsp_i2c4";
841 drive-strength = <2>;
842 bias-disable;
843 };
844
845 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio14", "gpio15";
847 function = "blsp_i2c4";
848 drive-strength = <2>;
849 bias-pull-up;
850 };
851
852 i2c5_default: i2c5-default-state {
853 pins = "gpio18", "gpio19";
854 function = "blsp_i2c5";
855 drive-strength = <2>;
856 bias-disable;
857 };
858
859 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio18", "gpio19";
861 function = "blsp_i2c5";
862 drive-strength = <2>;
863 bias-pull-up;
864 };
865
866 i2c6_default: i2c6-default-state {
867 pins = "gpio22", "gpio23";
868 function = "blsp_i2c6";
869 drive-strength = <2>;
870 bias-disable;
871 };
872
873 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio22", "gpio23";
875 function = "blsp_i2c6";
876 drive-strength = <2>;
877 bias-pull-up;
878 };
879
880 i2c7_default: i2c7-default-state {
881 pins = "gpio26", "gpio27";
882 function = "blsp_i2c7";
883 drive-strength = <2>;
884 bias-disable;
885 };
886
887 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio26", "gpio27";
889 function = "blsp_i2c7";
890 drive-strength = <2>;
891 bias-pull-up;
892 };
893
894 i2c8_default: i2c8-default-state {
895 pins = "gpio30", "gpio31";
896 function = "blsp_i2c8_a";
897 drive-strength = <2>;
898 bias-disable;
899 };
900
901 i2c8_sleep: i2c8-sleep-state {
902 pins = "gpio30", "gpio31";
903 function = "blsp_i2c8_a";
904 drive-strength = <2>;
905 bias-pull-up;
906 };
907
908 cci0_default: cci0-default-state {
909 pins = "gpio36","gpio37";
910 function = "cci_i2c";
911 bias-pull-up;
912 drive-strength = <2>;
913 };
914
915 cci1_default: cci1-default-state {
916 pins = "gpio38","gpio39";
917 function = "cci_i2c";
918 bias-pull-up;
919 drive-strength = <2>;
920 };
921
922 sdc1_state_on: sdc1-on-state {
923 clk-pins {
924 pins = "sdc1_clk";
925 bias-disable;
926 drive-strength = <16>;
927 };
928
929 cmd-pins {
930 pins = "sdc1_cmd";
931 bias-pull-up;
932 drive-strength = <10>;
933 };
934
935 data-pins {
936 pins = "sdc1_data";
937 bias-pull-up;
938 drive-strength = <10>;
939 };
940
941 rclk-pins {
942 pins = "sdc1_rclk";
943 bias-pull-down;
944 };
945 };
946
947 sdc1_state_off: sdc1-off-state {
948 clk-pins {
949 pins = "sdc1_clk";
950 bias-disable;
951 drive-strength = <2>;
952 };
953
954 cmd-pins {
955 pins = "sdc1_cmd";
956 bias-pull-up;
957 drive-strength = <2>;
958 };
959
960 data-pins {
961 pins = "sdc1_data";
962 bias-pull-up;
963 drive-strength = <2>;
964 };
965
966 rclk-pins {
967 pins = "sdc1_rclk";
968 bias-pull-down;
969 };
970 };
971
972 sdc2_state_on: sdc2-on-state {
973 clk-pins {
974 pins = "sdc2_clk";
975 bias-disable;
976 drive-strength = <16>;
977 };
978
979 cmd-pins {
980 pins = "sdc2_cmd";
981 bias-pull-up;
982 drive-strength = <10>;
983 };
984
985 data-pins {
986 pins = "sdc2_data";
987 bias-pull-up;
988 drive-strength = <10>;
989 };
990 };
991
992 sdc2_state_off: sdc2-off-state {
993 clk-pins {
994 pins = "sdc2_clk";
995 bias-disable;
996 drive-strength = <2>;
997 };
998
999 cmd-pins {
1000 pins = "sdc2_cmd";
1001 bias-pull-up;
1002 drive-strength = <2>;
1003 };
1004
1005 data-pins {
1006 pins = "sdc2_data";
1007 bias-pull-up;
1008 drive-strength = <2>;
1009 };
1010 };
1011 };
1012
1013 remoteproc_mss: remoteproc@4080000 {
1014 compatible = "qcom,sdm660-mss-pil";
1015 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1016 reg-names = "qdsp6", "rmb";
1017
1018 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1019 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1020 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1021 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1022 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1023 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1024 interrupt-names = "wdog",
1025 "fatal",
1026 "ready",
1027 "handover",
1028 "stop-ack",
1029 "shutdown-ack";
1030
1031 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1032 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1033 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1034 <&gcc GPLL0_OUT_MSSCC>,
1035 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1036 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1037 <&rpmcc RPM_SMD_QDSS_CLK>,
1038 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1039 clock-names = "iface",
1040 "bus",
1041 "mem",
1042 "gpll0_mss",
1043 "snoc_axi",
1044 "mnoc_axi",
1045 "qdss",
1046 "xo";
1047
1048 qcom,smem-states = <&modem_smp2p_out 0>;
1049 qcom,smem-state-names = "stop";
1050
1051 resets = <&gcc GCC_MSS_RESTART>;
1052 reset-names = "mss_restart";
1053
1054 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1055
1056 power-domains = <&rpmpd SDM660_VDDCX>,
1057 <&rpmpd SDM660_VDDMX>;
1058 power-domain-names = "cx", "mx";
1059
1060 memory-region = <&mba_region>, <&mpss_region>;
1061
1062 status = "disabled";
1063
1064 glink-edge {
1065 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1066 label = "modem";
1067 qcom,remote-pid = <1>;
1068 mboxes = <&apcs_glb 15>;
1069 };
1070 };
1071
1072 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074
1075 reg = <0x05000000 0x40000>;
1076 reg-names = "kgsl_3d0_reg_memory";
1077
1078 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1079
1080 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gpucc GPUCC_RBBMTIMER_CLK>,
1082 <&gcc GCC_BIMC_GFX_CLK>,
1083 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1084 <&gpucc GPUCC_RBCPR_CLK>,
1085 <&gpucc GPUCC_GFX3D_CLK>;
1086
1087 clock-names = "iface",
1088 "rbbmtimer",
1089 "mem",
1090 "mem_iface",
1091 "rbcpr",
1092 "core";
1093
1094 power-domains = <&rpmpd SDM660_VDDMX>;
1095 iommus = <&kgsl_smmu 0>;
1096
1097 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "speed_bin";
1099
1100 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1101 interconnect-names = "gfx-mem";
1102
1103 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>;
1105
1106 status = "disabled";
1107
1108 gpu_sdm630_opp_table: opp-table {
1109 compatible = "operating-points-v2";
1110 opp-775000000 {
1111 opp-hz = /bits/ 64 <775000000>;
1112 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-peak-kBps = <5412000>;
1114 opp-supported-hw = <0xa2>;
1115 };
1116 opp-647000000 {
1117 opp-hz = /bits/ 64 <647000000>;
1118 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-peak-kBps = <4068000>;
1120 opp-supported-hw = <0xff>;
1121 };
1122 opp-588000000 {
1123 opp-hz = /bits/ 64 <588000000>;
1124 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-peak-kBps = <3072000>;
1126 opp-supported-hw = <0xff>;
1127 };
1128 opp-465000000 {
1129 opp-hz = /bits/ 64 <465000000>;
1130 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-peak-kBps = <2724000>;
1132 opp-supported-hw = <0xff>;
1133 };
1134 opp-370000000 {
1135 opp-hz = /bits/ 64 <370000000>;
1136 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-peak-kBps = <2188000>;
1138 opp-supported-hw = <0xff>;
1139 };
1140 opp-240000000 {
1141 opp-hz = /bits/ 64 <240000000>;
1142 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-peak-kBps = <1648000>;
1144 opp-supported-hw = <0xff>;
1145 };
1146 opp-160000000 {
1147 opp-hz = /bits/ 64 <160000000>;
1148 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-peak-kBps = <1200000>;
1150 opp-supported-hw = <0xff>;
1151 };
1152 };
1153 };
1154
1155 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,adreno-smmu", "qcom,smmu-v2";
1158 reg = <0x05040000 0x10000>;
1159
1160 /*
1161 * GX GDSC parent is CX. We need to bring up CX for SMMU
1162 * but we need both up for Adreno. On the other hand, we
1163 * need to manage the GX rpmpd domain in the adreno driver.
1164 * Enable CX/GX GDSCs here so that we can manage just the GX
1165 * RPM Power Domain in the Adreno driver.
1166 */
1167 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1169 <&gcc GCC_BIMC_GFX_CLK>,
1170 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1171 clock-names = "iface",
1172 "mem",
1173 "mem_iface";
1174 #global-interrupts = <2>;
1175 #iommu-cells = <1>;
1176
1177 interrupts =
1178 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180
1181 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189
1190 status = "disabled";
1191 };
1192
1193 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>;
1196 #reset-cells = <1>;
1197 #power-domain-cells = <1>;
1198 reg = <0x05065000 0x9038>;
1199
1200 clocks = <&xo_board>,
1201 <&gcc GCC_GPU_GPLL0_CLK>,
1202 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1203 clock-names = "xo",
1204 "gcc_gpu_gpll0_clk",
1205 "gcc_gpu_gpll0_div_clk";
1206 status = "disabled";
1207 };
1208
1209 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>;
1213
1214 #global-interrupts = <2>;
1215 interrupts =
1216 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218
1219 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236
1237 status = "disabled";
1238 };
1239
1240 sram@290000 {
1241 compatible = "qcom,rpm-stats";
1242 reg = <0x00290000 0x10000>;
1243 };
1244
1245 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1000000>,
1249 <0x09400000 0x1000000>,
1250 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3000>;
1252 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>;
1256 qcom,channel = <0>;
1257 #address-cells = <2>;
1258 #size-cells = <0>;
1259 interrupt-controller;
1260 #interrupt-cells = <4>;
1261 };
1262
1263 usb3: usb@a8f8800 {
1264 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 reg = <0x0a8f8800 0x400>;
1266 status = "disabled";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1269 ranges;
1270
1271 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1272 <&gcc GCC_USB30_MASTER_CLK>,
1273 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1274 <&gcc GCC_USB30_SLEEP_CLK>,
1275 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1276 clock-names = "cfg_noc",
1277 "core",
1278 "iface",
1279 "sleep",
1280 "mock_utmi";
1281
1282 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1283 <&gcc GCC_USB30_MASTER_CLK>;
1284 assigned-clock-rates = <19200000>, <120000000>;
1285
1286 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1290 interrupt-names = "pwr_event",
1291 "qusb2_phy",
1292 "hs_phy_irq",
1293 "ss_phy_irq";
1294
1295 power-domains = <&gcc USB_30_GDSC>;
1296
1297 resets = <&gcc GCC_USB_30_BCR>;
1298
1299 usb3_dwc3: usb@a800000 {
1300 compatible = "snps,dwc3";
1301 reg = <0x0a800000 0xc8d0>;
1302 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1303 snps,dis_u2_susphy_quirk;
1304 snps,dis_enblslpm_quirk;
1305 snps,parkmode-disable-ss-quirk;
1306
1307 phys = <&qusb2phy0>, <&usb3_qmpphy>;
1308 phy-names = "usb2-phy", "usb3-phy";
1309 snps,hird-threshold = /bits/ 8 <0>;
1310 };
1311 };
1312
1313 usb3_qmpphy: phy@c010000 {
1314 compatible = "qcom,sdm660-qmp-usb3-phy";
1315 reg = <0x0c010000 0x1000>;
1316
1317 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1318 <&gcc GCC_USB3_CLKREF_CLK>,
1319 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1320 <&gcc GCC_USB3_PHY_PIPE_CLK>;
1321 clock-names = "aux",
1322 "ref",
1323 "cfg_ahb",
1324 "pipe";
1325 clock-output-names = "usb3_phy_pipe_clk_src";
1326 #clock-cells = <0>;
1327 #phy-cells = <0>;
1328
1329 resets = <&gcc GCC_USB3_PHY_BCR>,
1330 <&gcc GCC_USB3PHY_PHY_BCR>;
1331 reset-names = "phy",
1332 "phy_phy";
1333
1334 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1335
1336 status = "disabled";
1337 };
1338
1339 qusb2phy0: phy@c012000 {
1340 compatible = "qcom,sdm660-qusb2-phy";
1341 reg = <0x0c012000 0x180>;
1342 #phy-cells = <0>;
1343
1344 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1345 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1346 clock-names = "cfg_ahb", "ref";
1347
1348 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1349 nvmem-cells = <&qusb2_hstx_trim>;
1350 status = "disabled";
1351 };
1352
1353 qusb2phy1: phy@c014000 {
1354 compatible = "qcom,sdm660-qusb2-phy";
1355 reg = <0x0c014000 0x180>;
1356 #phy-cells = <0>;
1357
1358 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1359 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1360 clock-names = "cfg_ahb", "ref";
1361
1362 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1363 nvmem-cells = <&qusb2_hstx_trim>;
1364 status = "disabled";
1365 };
1366
1367 sdhc_2: mmc@c084000 {
1368 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1369 reg = <0x0c084000 0x1000>;
1370 reg-names = "hc";
1371
1372 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "hc_irq", "pwr_irq";
1375
1376 bus-width = <4>;
1377
1378 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1379 <&gcc GCC_SDCC2_APPS_CLK>,
1380 <&xo_board>;
1381 clock-names = "iface", "core", "xo";
1382
1383
1384 interconnects = <&a2noc 3 &a2noc 10>,
1385 <&gnoc 0 &cnoc 28>;
1386 interconnect-names = "sdhc-ddr","cpu-sdhc";
1387 operating-points-v2 = <&sdhc2_opp_table>;
1388
1389 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpmpd SDM660_VDDCX>;
1393
1394 status = "disabled";
1395
1396 sdhc2_opp_table: opp-table {
1397 compatible = "operating-points-v2";
1398
1399 opp-50000000 {
1400 opp-hz = /bits/ 64 <50000000>;
1401 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-peak-kBps = <200000 140000>;
1403 opp-avg-kBps = <130718 133320>;
1404 };
1405 opp-100000000 {
1406 opp-hz = /bits/ 64 <100000000>;
1407 required-opps = <&rpmpd_opp_svs>;
1408 opp-peak-kBps = <250000 160000>;
1409 opp-avg-kBps = <196078 150000>;
1410 };
1411 opp-200000000 {
1412 opp-hz = /bits/ 64 <200000000>;
1413 required-opps = <&rpmpd_opp_nom>;
1414 opp-peak-kBps = <4096000 4096000>;
1415 opp-avg-kBps = <1338562 1338562>;
1416 };
1417 };
1418 };
1419
1420 sdhc_1: mmc@c0c4000 {
1421 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1000>,
1424 <0x0c0c8000 0x8000>;
1425 reg-names = "hc", "cqhci", "ice";
1426
1427 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc_irq", "pwr_irq";
1430
1431 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1432 <&gcc GCC_SDCC1_APPS_CLK>,
1433 <&xo_board>,
1434 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1435 clock-names = "iface", "core", "xo", "ice";
1436
1437 interconnects = <&a2noc 2 &a2noc 10>,
1438 <&gnoc 0 &cnoc 27>;
1439 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1440 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpmpd SDM660_VDDCX>;
1445
1446 bus-width = <8>;
1447 non-removable;
1448
1449 status = "disabled";
1450
1451 sdhc1_opp_table: opp-table {
1452 compatible = "operating-points-v2";
1453
1454 opp-50000000 {
1455 opp-hz = /bits/ 64 <50000000>;
1456 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-peak-kBps = <200000 140000>;
1458 opp-avg-kBps = <130718 133320>;
1459 };
1460 opp-100000000 {
1461 opp-hz = /bits/ 64 <100000000>;
1462 required-opps = <&rpmpd_opp_svs>;
1463 opp-peak-kBps = <250000 160000>;
1464 opp-avg-kBps = <196078 150000>;
1465 };
1466 opp-384000000 {
1467 opp-hz = /bits/ 64 <384000000>;
1468 required-opps = <&rpmpd_opp_nom>;
1469 opp-peak-kBps = <4096000 4096000>;
1470 opp-avg-kBps = <1338562 1338562>;
1471 };
1472 };
1473 };
1474
1475 usb2: usb@c2f8800 {
1476 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1477 reg = <0x0c2f8800 0x400>;
1478 status = "disabled";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1481 ranges;
1482
1483 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1484 <&gcc GCC_USB20_MASTER_CLK>,
1485 <&gcc GCC_USB20_SLEEP_CLK>,
1486 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1487 clock-names = "cfg_noc", "core",
1488 "sleep", "mock_utmi";
1489
1490 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1491 <&gcc GCC_USB20_MASTER_CLK>;
1492 assigned-clock-rates = <19200000>, <60000000>;
1493
1494 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1497 interrupt-names = "pwr_event",
1498 "qusb2_phy",
1499 "hs_phy_irq";
1500
1501 qcom,select-utmi-as-pipe-clk;
1502
1503 resets = <&gcc GCC_USB_20_BCR>;
1504
1505 usb2_dwc3: usb@c200000 {
1506 compatible = "snps,dwc3";
1507 reg = <0x0c200000 0xc8d0>;
1508 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1509 snps,dis_u2_susphy_quirk;
1510 snps,dis_enblslpm_quirk;
1511
1512 /* This is the HS-only host */
1513 maximum-speed = "high-speed";
1514 phys = <&qusb2phy1>;
1515 phy-names = "usb2-phy";
1516 snps,hird-threshold = /bits/ 8 <0>;
1517 };
1518 };
1519
1520 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mmcc-sdm630";
1522 reg = <0x0c8c0000 0x40000>;
1523 #clock-cells = <1>;
1524 #reset-cells = <1>;
1525 #power-domain-cells = <1>;
1526 clock-names = "xo",
1527 "sleep_clk",
1528 "gpll0",
1529 "gpll0_div",
1530 "dsi0pll",
1531 "dsi0pllbyte",
1532 "dsi1pll",
1533 "dsi1pllbyte",
1534 "dp_link_2x_clk_divsel_five",
1535 "dp_vco_divided_clk_src_mux";
1536 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1537 <&sleep_clk>,
1538 <&gcc GCC_MMSS_GPLL0_CLK>,
1539 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1540 <&mdss_dsi0_phy 1>,
1541 <&mdss_dsi0_phy 0>,
1542 <0>,
1543 <0>,
1544 <0>,
1545 <0>;
1546 };
1547
1548 mdss: display-subsystem@c900000 {
1549 compatible = "qcom,mdss";
1550 reg = <0x0c900000 0x1000>,
1551 <0x0c9b0000 0x1040>;
1552 reg-names = "mdss_phys", "vbif_phys";
1553
1554 power-domains = <&mmcc MDSS_GDSC>;
1555
1556 clocks = <&mmcc MDSS_AHB_CLK>,
1557 <&mmcc MDSS_AXI_CLK>,
1558 <&mmcc MDSS_VSYNC_CLK>,
1559 <&mmcc MDSS_MDP_CLK>;
1560 clock-names = "iface",
1561 "bus",
1562 "vsync",
1563 "core";
1564
1565 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1566
1567 interrupt-controller;
1568 #interrupt-cells = <1>;
1569
1570 #address-cells = <1>;
1571 #size-cells = <1>;
1572 ranges;
1573 status = "disabled";
1574
1575 mdp: display-controller@c901000 {
1576 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1577 reg = <0x0c901000 0x89000>;
1578 reg-names = "mdp_phys";
1579
1580 interrupt-parent = <&mdss>;
1581 interrupts = <0>;
1582
1583 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1584 <&mmcc MDSS_VSYNC_CLK>;
1585 assigned-clock-rates = <300000000>,
1586 <19200000>;
1587 clocks = <&mmcc MDSS_AHB_CLK>,
1588 <&mmcc MDSS_AXI_CLK>,
1589 <&mmcc MDSS_MDP_CLK>,
1590 <&mmcc MDSS_VSYNC_CLK>;
1591 clock-names = "iface",
1592 "bus",
1593 "core",
1594 "vsync";
1595
1596 interconnects = <&mnoc 2 &bimc 5>,
1597 <&mnoc 3 &bimc 5>,
1598 <&gnoc 0 &mnoc 17>;
1599 interconnect-names = "mdp0-mem",
1600 "mdp1-mem",
1601 "rotator-mem";
1602 iommus = <&mmss_smmu 0>;
1603 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains = <&rpmpd SDM660_VDDCX>;
1605
1606 ports {
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609
1610 port@0 {
1611 reg = <0>;
1612 mdp5_intf1_out: endpoint {
1613 remote-endpoint = <&mdss_dsi0_in>;
1614 };
1615 };
1616 };
1617
1618 mdp_opp_table: opp-table {
1619 compatible = "operating-points-v2";
1620
1621 opp-150000000 {
1622 opp-hz = /bits/ 64 <150000000>;
1623 opp-peak-kBps = <320000 320000 76800>;
1624 required-opps = <&rpmpd_opp_low_svs>;
1625 };
1626 opp-275000000 {
1627 opp-hz = /bits/ 64 <275000000>;
1628 opp-peak-kBps = <6400000 6400000 160000>;
1629 required-opps = <&rpmpd_opp_svs>;
1630 };
1631 opp-300000000 {
1632 opp-hz = /bits/ 64 <300000000>;
1633 opp-peak-kBps = <6400000 6400000 190000>;
1634 required-opps = <&rpmpd_opp_svs_plus>;
1635 };
1636 opp-330000000 {
1637 opp-hz = /bits/ 64 <330000000>;
1638 opp-peak-kBps = <6400000 6400000 240000>;
1639 required-opps = <&rpmpd_opp_nom>;
1640 };
1641 opp-412500000 {
1642 opp-hz = /bits/ 64 <412500000>;
1643 opp-peak-kBps = <6400000 6400000 320000>;
1644 required-opps = <&rpmpd_opp_turbo>;
1645 };
1646 };
1647 };
1648
1649 mdss_dsi0: dsi@c994000 {
1650 compatible = "qcom,sdm660-dsi-ctrl",
1651 "qcom,mdss-dsi-ctrl";
1652 reg = <0x0c994000 0x400>;
1653 reg-names = "dsi_ctrl";
1654
1655 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains = <&rpmpd SDM660_VDDCX>;
1657
1658 interrupt-parent = <&mdss>;
1659 interrupts = <4>;
1660
1661 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1662 <&mmcc PCLK0_CLK_SRC>;
1663 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1664 <&mdss_dsi0_phy 1>;
1665
1666 clocks = <&mmcc MDSS_MDP_CLK>,
1667 <&mmcc MDSS_BYTE0_CLK>,
1668 <&mmcc MDSS_BYTE0_INTF_CLK>,
1669 <&mmcc MNOC_AHB_CLK>,
1670 <&mmcc MDSS_AHB_CLK>,
1671 <&mmcc MDSS_AXI_CLK>,
1672 <&mmcc MISC_AHB_CLK>,
1673 <&mmcc MDSS_PCLK0_CLK>,
1674 <&mmcc MDSS_ESC0_CLK>;
1675 clock-names = "mdp_core",
1676 "byte",
1677 "byte_intf",
1678 "mnoc",
1679 "iface",
1680 "bus",
1681 "core_mmss",
1682 "pixel",
1683 "core";
1684
1685 phys = <&mdss_dsi0_phy>;
1686
1687 status = "disabled";
1688
1689 ports {
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692
1693 port@0 {
1694 reg = <0>;
1695 mdss_dsi0_in: endpoint {
1696 remote-endpoint = <&mdp5_intf1_out>;
1697 };
1698 };
1699
1700 port@1 {
1701 reg = <1>;
1702 mdss_dsi0_out: endpoint {
1703 };
1704 };
1705 };
1706 };
1707
1708 mdss_dsi0_phy: phy@c994400 {
1709 compatible = "qcom,dsi-phy-14nm-660";
1710 reg = <0x0c994400 0x100>,
1711 <0x0c994500 0x300>,
1712 <0x0c994800 0x188>;
1713 reg-names = "dsi_phy",
1714 "dsi_phy_lane",
1715 "dsi_pll";
1716
1717 #clock-cells = <1>;
1718 #phy-cells = <0>;
1719
1720 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = "iface", "ref";
1722 status = "disabled";
1723 };
1724 };
1725
1726 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_clk";
1732 #dma-cells = <1>;
1733 qcom,ee = <0>;
1734 qcom,controlled-remotely;
1735 num-channels = <18>;
1736 qcom,num-ees = <4>;
1737 };
1738
1739 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx";
1748 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled";
1752 };
1753
1754 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx";
1763 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled";
1766 };
1767
1768 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772
1773 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", "iface";
1776 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1778 dma-names = "tx", "rx";
1779
1780 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1785 status = "disabled";
1786 };
1787
1788 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792
1793 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", "iface";
1796 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1798 dma-names = "tx", "rx";
1799
1800 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>;
1804 #size-cells = <0>;
1805 status = "disabled";
1806 };
1807
1808 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812
1813 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", "iface";
1816 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1818 dma-names = "tx", "rx";
1819
1820 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 status = "disabled";
1826 };
1827
1828 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832
1833 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", "iface";
1836 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1838 dma-names = "tx", "rx";
1839
1840 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1845 status = "disabled";
1846 };
1847
1848 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_clk";
1854 #dma-cells = <1>;
1855 qcom,ee = <0>;
1856 qcom,controlled-remotely;
1857 num-channels = <18>;
1858 qcom,num-ees = <4>;
1859 };
1860
1861 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx";
1870 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_uart1_sleep>;
1873 status = "disabled";
1874 };
1875
1876 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880
1881 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", "iface";
1884 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1886 dma-names = "tx", "rx";
1887
1888 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1893 status = "disabled";
1894 };
1895
1896 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900
1901 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", "iface";
1904 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1906 dma-names = "tx", "rx";
1907
1908 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>;
1912 #size-cells = <0>;
1913 status = "disabled";
1914 };
1915
1916 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920
1921 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", "iface";
1924 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1926 dma-names = "tx", "rx";
1927
1928 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1933 status = "disabled";
1934 };
1935
1936 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940
1941 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", "iface";
1944 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1946 dma-names = "tx", "rx";
1947
1948 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1953 status = "disabled";
1954 };
1955
1956 sram@146bf000 {
1957 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1958 reg = <0x146bf000 0x1000>;
1959
1960 #address-cells = <1>;
1961 #size-cells = <1>;
1962
1963 ranges = <0 0x146bf000 0x1000>;
1964
1965 pil-reloc@94c {
1966 compatible = "qcom,pil-reloc-info";
1967 reg = <0x94c 0xc8>;
1968 };
1969 };
1970
1971 camss: camss@ca00020 {
1972 compatible = "qcom,sdm660-camss";
1973 reg = <0x0ca00020 0x10>,
1974 <0x0ca30000 0x100>,
1975 <0x0ca30400 0x100>,
1976 <0x0ca30800 0x100>,
1977 <0x0ca30c00 0x100>,
1978 <0x0c824000 0x1000>,
1979 <0x0ca00120 0x4>,
1980 <0x0c825000 0x1000>,
1981 <0x0ca00124 0x4>,
1982 <0x0c826000 0x1000>,
1983 <0x0ca00128 0x4>,
1984 <0x0ca31000 0x500>,
1985 <0x0ca10000 0x1000>,
1986 <0x0ca14000 0x1000>;
1987 reg-names = "csi_clk_mux",
1988 "csid0",
1989 "csid1",
1990 "csid2",
1991 "csid3",
1992 "csiphy0",
1993 "csiphy0_clk_mux",
1994 "csiphy1",
1995 "csiphy1_clk_mux",
1996 "csiphy2",
1997 "csiphy2_clk_mux",
1998 "ispif",
1999 "vfe0",
2000 "vfe1";
2001 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2005 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2006 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2007 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2008 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2009 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2010 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2011 interrupt-names = "csid0",
2012 "csid1",
2013 "csid2",
2014 "csid3",
2015 "csiphy0",
2016 "csiphy1",
2017 "csiphy2",
2018 "ispif",
2019 "vfe0",
2020 "vfe1";
2021 clocks = <&mmcc CAMSS_AHB_CLK>,
2022 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2023 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2025 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2026 <&mmcc CAMSS_CSI0_AHB_CLK>,
2027 <&mmcc CAMSS_CSI0_CLK>,
2028 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2029 <&mmcc CAMSS_CSI0PIX_CLK>,
2030 <&mmcc CAMSS_CSI0RDI_CLK>,
2031 <&mmcc CAMSS_CSI1_AHB_CLK>,
2032 <&mmcc CAMSS_CSI1_CLK>,
2033 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2034 <&mmcc CAMSS_CSI1PIX_CLK>,
2035 <&mmcc CAMSS_CSI1RDI_CLK>,
2036 <&mmcc CAMSS_CSI2_AHB_CLK>,
2037 <&mmcc CAMSS_CSI2_CLK>,
2038 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2039 <&mmcc CAMSS_CSI2PIX_CLK>,
2040 <&mmcc CAMSS_CSI2RDI_CLK>,
2041 <&mmcc CAMSS_CSI3_AHB_CLK>,
2042 <&mmcc CAMSS_CSI3_CLK>,
2043 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2044 <&mmcc CAMSS_CSI3PIX_CLK>,
2045 <&mmcc CAMSS_CSI3RDI_CLK>,
2046 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2047 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2048 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2049 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2050 <&mmcc CAMSS_CSI_VFE0_CLK>,
2051 <&mmcc CAMSS_CSI_VFE1_CLK>,
2052 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2053 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2054 <&mmcc CAMSS_TOP_AHB_CLK>,
2055 <&mmcc CAMSS_VFE0_AHB_CLK>,
2056 <&mmcc CAMSS_VFE0_CLK>,
2057 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2058 <&mmcc CAMSS_VFE1_AHB_CLK>,
2059 <&mmcc CAMSS_VFE1_CLK>,
2060 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2061 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2062 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2063 clock-names = "ahb",
2064 "cphy_csid0",
2065 "cphy_csid1",
2066 "cphy_csid2",
2067 "cphy_csid3",
2068 "csi0_ahb",
2069 "csi0",
2070 "csi0_phy",
2071 "csi0_pix",
2072 "csi0_rdi",
2073 "csi1_ahb",
2074 "csi1",
2075 "csi1_phy",
2076 "csi1_pix",
2077 "csi1_rdi",
2078 "csi2_ahb",
2079 "csi2",
2080 "csi2_phy",
2081 "csi2_pix",
2082 "csi2_rdi",
2083 "csi3_ahb",
2084 "csi3",
2085 "csi3_phy",
2086 "csi3_pix",
2087 "csi3_rdi",
2088 "csiphy0_timer",
2089 "csiphy1_timer",
2090 "csiphy2_timer",
2091 "csiphy_ahb2crif",
2092 "csi_vfe0",
2093 "csi_vfe1",
2094 "ispif_ahb",
2095 "throttle_axi",
2096 "top_ahb",
2097 "vfe0_ahb",
2098 "vfe0",
2099 "vfe0_stream",
2100 "vfe1_ahb",
2101 "vfe1",
2102 "vfe1_stream",
2103 "vfe_ahb",
2104 "vfe_axi";
2105 interconnects = <&mnoc 5 &bimc 5>;
2106 interconnect-names = "vfe-mem";
2107 iommus = <&mmss_smmu 0xc00>,
2108 <&mmss_smmu 0xc01>,
2109 <&mmss_smmu 0xc02>,
2110 <&mmss_smmu 0xc03>;
2111 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2112 <&mmcc CAMSS_VFE1_GDSC>;
2113 status = "disabled";
2114
2115 ports {
2116 #address-cells = <1>;
2117 #size-cells = <0>;
2118 };
2119 };
2120
2121 cci: cci@ca0c000 {
2122 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>;
2124 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1000>;
2126 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2127
2128 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2129 <&mmcc CAMSS_CCI_CLK>;
2130 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2132 <&mmcc CAMSS_CCI_AHB_CLK>,
2133 <&mmcc CAMSS_CCI_CLK>,
2134 <&mmcc CAMSS_AHB_CLK>;
2135 clock-names = "camss_top_ahb",
2136 "cci_ahb",
2137 "cci",
2138 "camss_ahb";
2139
2140 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2143 status = "disabled";
2144
2145 cci_i2c0: i2c-bus@0 {
2146 reg = <0>;
2147 clock-frequency = <400000>;
2148 #address-cells = <1>;
2149 #size-cells = <0>;
2150 };
2151
2152 cci_i2c1: i2c-bus@1 {
2153 reg = <1>;
2154 clock-frequency = <400000>;
2155 #address-cells = <1>;
2156 #size-cells = <0>;
2157 };
2158 };
2159
2160 venus: video-codec@cc00000 {
2161 compatible = "qcom,sdm660-venus";
2162 reg = <0x0cc00000 0xff000>;
2163 clocks = <&mmcc VIDEO_CORE_CLK>,
2164 <&mmcc VIDEO_AHB_CLK>,
2165 <&mmcc VIDEO_AXI_CLK>,
2166 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2167 clock-names = "core", "iface", "bus", "bus_throttle";
2168 interconnects = <&gnoc 0 &mnoc 13>,
2169 <&mnoc 4 &bimc 5>;
2170 interconnect-names = "cpu-cfg", "video-mem";
2171 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&mmss_smmu 0x400>,
2173 <&mmss_smmu 0x401>,
2174 <&mmss_smmu 0x40a>,
2175 <&mmss_smmu 0x407>,
2176 <&mmss_smmu 0x40e>,
2177 <&mmss_smmu 0x40f>,
2178 <&mmss_smmu 0x408>,
2179 <&mmss_smmu 0x409>,
2180 <&mmss_smmu 0x40b>,
2181 <&mmss_smmu 0x40c>,
2182 <&mmss_smmu 0x40d>,
2183 <&mmss_smmu 0x410>,
2184 <&mmss_smmu 0x421>,
2185 <&mmss_smmu 0x428>,
2186 <&mmss_smmu 0x429>,
2187 <&mmss_smmu 0x42b>,
2188 <&mmss_smmu 0x42c>,
2189 <&mmss_smmu 0x42d>,
2190 <&mmss_smmu 0x411>,
2191 <&mmss_smmu 0x431>;
2192 memory-region = <&venus_region>;
2193 power-domains = <&mmcc VENUS_GDSC>;
2194 status = "disabled";
2195
2196 video-decoder {
2197 compatible = "venus-decoder";
2198 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = "vcodec0_core";
2200 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 };
2202
2203 video-encoder {
2204 compatible = "venus-encoder";
2205 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = "vcodec0_core";
2207 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2208 };
2209 };
2210
2211 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x40000>;
2214
2215 clocks = <&mmcc MNOC_AHB_CLK>,
2216 <&mmcc BIMC_SMMU_AHB_CLK>,
2217 <&mmcc BIMC_SMMU_AXI_CLK>;
2218 clock-names = "iface-mm", "iface-smmu",
2219 "bus-smmu";
2220 #global-interrupts = <2>;
2221 #iommu-cells = <1>;
2222
2223 interrupts =
2224 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226
2227 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251
2252 status = "disabled";
2253 };
2254
2255 adsp_pil: remoteproc@15700000 {
2256 compatible = "qcom,sdm660-adsp-pas";
2257 reg = <0x15700000 0x4040>;
2258
2259 interrupts-extended =
2260 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2261 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2262 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2263 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2264 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2265 interrupt-names = "wdog", "fatal", "ready",
2266 "handover", "stop-ack";
2267
2268 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo";
2270
2271 memory-region = <&adsp_region>;
2272 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = "cx";
2274
2275 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names = "stop";
2277
2278 glink-edge {
2279 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2280
2281 label = "lpass";
2282 mboxes = <&apcs_glb 9>;
2283 qcom,remote-pid = <2>;
2284
2285 apr {
2286 compatible = "qcom,apr-v2";
2287 qcom,glink-channels = "apr_audio_svc";
2288 qcom,domain = <APR_DOMAIN_ADSP>;
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2291
2292 service@3 {
2293 reg = <APR_SVC_ADSP_CORE>;
2294 compatible = "qcom,q6core";
2295 };
2296
2297 q6afe: service@4 {
2298 compatible = "qcom,q6afe";
2299 reg = <APR_SVC_AFE>;
2300 q6afedai: dais {
2301 compatible = "qcom,q6afe-dais";
2302 #address-cells = <1>;
2303 #size-cells = <0>;
2304 #sound-dai-cells = <1>;
2305 };
2306 };
2307
2308 q6asm: service@7 {
2309 compatible = "qcom,q6asm";
2310 reg = <APR_SVC_ASM>;
2311 q6asmdai: dais {
2312 compatible = "qcom,q6asm-dais";
2313 #address-cells = <1>;
2314 #size-cells = <0>;
2315 #sound-dai-cells = <1>;
2316 iommus = <&lpass_smmu 1>;
2317 };
2318 };
2319
2320 q6adm: service@8 {
2321 compatible = "qcom,q6adm";
2322 reg = <APR_SVC_ADM>;
2323 q6routing: routing {
2324 compatible = "qcom,q6adm-routing";
2325 #sound-dai-cells = <0>;
2326 };
2327 };
2328 };
2329 };
2330 };
2331
2332 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sdm660-gnoc";
2334 reg = <0x17900000 0xe000>;
2335 #interconnect-cells = <1>;
2336 };
2337
2338 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sdm660-apcs-hmss-global",
2340 "qcom,msm8994-apcs-kpss-global";
2341 reg = <0x17911000 0x1000>;
2342
2343 #mbox-cells = <1>;
2344 };
2345
2346 timer@17920000 {
2347 #address-cells = <1>;
2348 #size-cells = <1>;
2349 ranges;
2350 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19200000>;
2353
2354 frame@17921000 {
2355 frame-number = <0>;
2356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2357 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2358 reg = <0x17921000 0x1000>,
2359 <0x17922000 0x1000>;
2360 };
2361
2362 frame@17923000 {
2363 frame-number = <1>;
2364 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2365 reg = <0x17923000 0x1000>;
2366 status = "disabled";
2367 };
2368
2369 frame@17924000 {
2370 frame-number = <2>;
2371 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2372 reg = <0x17924000 0x1000>;
2373 status = "disabled";
2374 };
2375
2376 frame@17925000 {
2377 frame-number = <3>;
2378 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2379 reg = <0x17925000 0x1000>;
2380 status = "disabled";
2381 };
2382
2383 frame@17926000 {
2384 frame-number = <4>;
2385 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2386 reg = <0x17926000 0x1000>;
2387 status = "disabled";
2388 };
2389
2390 frame@17927000 {
2391 frame-number = <5>;
2392 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2393 reg = <0x17927000 0x1000>;
2394 status = "disabled";
2395 };
2396
2397 frame@17928000 {
2398 frame-number = <6>;
2399 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2400 reg = <0x17928000 0x1000>;
2401 status = "disabled";
2402 };
2403 };
2404
2405 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3>;
2410 #address-cells = <1>;
2411 #size-cells = <1>;
2412 ranges;
2413 interrupt-controller;
2414 #redistributor-regions = <1>;
2415 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 };
2418 };
2419
2420 sound: sound {
2421 };
2422
2423 thermal-zones {
2424 aoss-thermal {
2425 polling-delay-passive = <250>;
2426
2427 thermal-sensors = <&tsens 0>;
2428
2429 trips {
2430 aoss_alert0: trip-point0 {
2431 temperature = <105000>;
2432 hysteresis = <1000>;
2433 type = "hot";
2434 };
2435 };
2436 };
2437
2438 cpuss0-thermal {
2439 polling-delay-passive = <250>;
2440
2441 thermal-sensors = <&tsens 1>;
2442
2443 trips {
2444 cpuss0_alert0: trip-point0 {
2445 temperature = <125000>;
2446 hysteresis = <1000>;
2447 type = "hot";
2448 };
2449 };
2450 };
2451
2452 cpuss1-thermal {
2453 polling-delay-passive = <250>;
2454
2455 thermal-sensors = <&tsens 2>;
2456
2457 trips {
2458 cpuss1_alert0: trip-point0 {
2459 temperature = <125000>;
2460 hysteresis = <1000>;
2461 type = "hot";
2462 };
2463 };
2464 };
2465
2466 cpu0-thermal {
2467 polling-delay-passive = <250>;
2468
2469 thermal-sensors = <&tsens 3>;
2470
2471 trips {
2472 cpu0_alert0: trip-point0 {
2473 temperature = <70000>;
2474 hysteresis = <1000>;
2475 type = "passive";
2476 };
2477
2478 cpu0_crit: cpu-crit {
2479 temperature = <110000>;
2480 hysteresis = <1000>;
2481 type = "critical";
2482 };
2483 };
2484 };
2485
2486 cpu1-thermal {
2487 polling-delay-passive = <250>;
2488
2489 thermal-sensors = <&tsens 4>;
2490
2491 trips {
2492 cpu1_alert0: trip-point0 {
2493 temperature = <70000>;
2494 hysteresis = <1000>;
2495 type = "passive";
2496 };
2497
2498 cpu1_crit: cpu-crit {
2499 temperature = <110000>;
2500 hysteresis = <1000>;
2501 type = "critical";
2502 };
2503 };
2504 };
2505
2506 cpu2-thermal {
2507 polling-delay-passive = <250>;
2508
2509 thermal-sensors = <&tsens 5>;
2510
2511 trips {
2512 cpu2_alert0: trip-point0 {
2513 temperature = <70000>;
2514 hysteresis = <1000>;
2515 type = "passive";
2516 };
2517
2518 cpu2_crit: cpu-crit {
2519 temperature = <110000>;
2520 hysteresis = <1000>;
2521 type = "critical";
2522 };
2523 };
2524 };
2525
2526 cpu3-thermal {
2527 polling-delay-passive = <250>;
2528
2529 thermal-sensors = <&tsens 6>;
2530
2531 trips {
2532 cpu3_alert0: trip-point0 {
2533 temperature = <70000>;
2534 hysteresis = <1000>;
2535 type = "passive";
2536 };
2537
2538 cpu3_crit: cpu-crit {
2539 temperature = <110000>;
2540 hysteresis = <1000>;
2541 type = "critical";
2542 };
2543 };
2544 };
2545
2546 /*
2547 * According to what downstream DTS says,
2548 * the entire power efficient cluster has
2549 * only a single thermal sensor.
2550 */
2551
2552 pwr-cluster-thermal {
2553 polling-delay-passive = <250>;
2554
2555 thermal-sensors = <&tsens 7>;
2556
2557 trips {
2558 pwr_cluster_alert0: trip-point0 {
2559 temperature = <70000>;
2560 hysteresis = <1000>;
2561 type = "passive";
2562 };
2563
2564 pwr_cluster_crit: cpu-crit {
2565 temperature = <110000>;
2566 hysteresis = <1000>;
2567 type = "critical";
2568 };
2569 };
2570 };
2571
2572 gpu-thermal {
2573 polling-delay-passive = <250>;
2574
2575 thermal-sensors = <&tsens 8>;
2576
2577 cooling-maps {
2578 map0 {
2579 trip = <&gpu_alert0>;
2580 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2581 };
2582 };
2583
2584 trips {
2585 gpu_alert0: trip-point0 {
2586 temperature = <85000>;
2587 hysteresis = <1000>;
2588 type = "passive";
2589 };
2590
2591 trip-point1 {
2592 temperature = <90000>;
2593 hysteresis = <1000>;
2594 type = "hot";
2595 };
2596
2597 trip-point2 {
2598 temperature = <110000>;
2599 hysteresis = <1000>;
2600 type = "critical";
2601 };
2602 };
2603 };
2604 };
2605
2606 timer {
2607 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2609 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2610 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2611 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2612 };
2613 };
2614
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