1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX75 SoC device tree source
4 *
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 */
8
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21 / {
22 #address-cells = <2>;
23 #size-cells = <2>;
24 interrupt-parent = <&intc>;
25
26 chosen: chosen { };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 #clock-cells = <0>;
33 };
34
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32000>;
38 #clock-cells = <0>;
39 };
40 };
41
42 cpus {
43 #address-cells = <2>;
44 #size-cells = <0>;
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci";
52 power-domains = <&CPU_PD0>;
53 power-domain-names = "psci";
54 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L2_0>;
58
59 L2_0: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
65 compatible = "cache";
66 cache-level = <3>;
67 cache-unified;
68 };
69 };
70 };
71
72 CPU1: cpu@100 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci";
78 power-domains = <&CPU_PD1>;
79 power-domain-names = "psci";
80 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L2_100>;
84
85 L2_100: l2-cache {
86 compatible = "cache";
87 cache-level = <2>;
88 cache-unified;
89 next-level-cache = <&L3_0>;
90 };
91 };
92
93 CPU2: cpu@200 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci";
99 power-domains = <&CPU_PD2>;
100 power-domain-names = "psci";
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L2_200>;
105
106 L2_200: l2-cache {
107 compatible = "cache";
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
111 };
112 };
113
114 CPU3: cpu@300 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci";
120 power-domains = <&CPU_PD3>;
121 power-domain-names = "psci";
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = <1024>;
124 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L2_300>;
126
127 L2_300: l2-cache {
128 compatible = "cache";
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
132 };
133 };
134
135 cpu-map {
136 cluster0 {
137 core0 {
138 cpu = <&CPU0>;
139 };
140
141 core1 {
142 cpu = <&CPU1>;
143 };
144
145 core2 {
146 cpu = <&CPU2>;
147 };
148
149 core3 {
150 cpu = <&CPU3>;
151 };
152 };
153 };
154
155 idle-states {
156 entry-method = "psci";
157
158 CPU_OFF: cpu-sleep-0 {
159 compatible = "arm,idle-state";
160 entry-latency-us = <235>;
161 exit-latency-us = <428>;
162 min-residency-us = <1774>;
163 arm,psci-suspend-param = <0x40000003>;
164 local-timer-stop;
165 };
166
167 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = "arm,idle-state";
169 entry-latency-us = <800>;
170 exit-latency-us = <750>;
171 min-residency-us = <4090>;
172 arm,psci-suspend-param = <0x40000004>;
173 local-timer-stop;
174 };
175
176 };
177
178 domain-idle-states {
179 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = "domain-idle-state";
181 arm,psci-suspend-param = <0x41000044>;
182 entry-latency-us = <1050>;
183 exit-latency-us = <2500>;
184 min-residency-us = <5309>;
185 };
186
187 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = "domain-idle-state";
189 arm,psci-suspend-param = <0x41001344>;
190 entry-latency-us = <2761>;
191 exit-latency-us = <3964>;
192 min-residency-us = <8467>;
193 };
194
195 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = "domain-idle-state";
197 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency-us = <2793>;
199 exit-latency-us = <4023>;
200 min-residency-us = <9826>;
201 };
202 };
203 };
204
205 firmware {
206 scm: scm {
207 compatible = "qcom,scm-sdx75", "qcom,scm";
208 };
209 };
210
211 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-virt";
213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_voter>;
215 clocks = <&rpmhcc RPMH_QPIC_CLK>;
216 };
217
218 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-virt";
220 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_voter>;
222 };
223
224 memory@80000000 {
225 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0>;
227 };
228
229 pmu {
230 compatible = "arm,cortex-a55-pmu";
231 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 };
233
234 psci {
235 compatible = "arm,psci-1.0";
236 method = "smc";
237
238 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = <0>;
240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 };
243
244 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = <0>;
246 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 };
249
250 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = <0>;
252 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 };
255
256 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = <0>;
258 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 };
261
262 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = <0>;
264 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 };
266 };
267
268 reserved-memory {
269 #address-cells = <2>;
270 #size-cells = <2>;
271 ranges;
272
273 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map;
276 };
277
278 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map;
281 };
282
283 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map;
286 };
287
288 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map;
291 };
292
293 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map;
296 };
297
298 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map;
301 };
302
303 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map;
306 };
307
308 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map;
311 };
312
313 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map;
316 };
317
318 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map;
321 };
322
323 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map;
326 };
327
328 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map;
331 };
332
333 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map;
337 };
338
339 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map;
342 };
343
344 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map;
347 };
348
349 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map;
352 };
353
354 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map;
357 };
358
359 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map;
362 };
363
364 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map;
367 };
368
369 qdss_mem: qdss@88800000 {
370 reg = <0x0 0x88800000 0x0 0x300000>;
371 no-map;
372 };
373
374 audio_heap_mem: audio-heap@88b00000 {
375 compatible = "shared-dma-pool";
376 reg = <0x0 0x88b00000 0x0 0x400000>;
377 no-map;
378 };
379
380 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
381 reg = <0x0 0x88f00000 0x0 0x5080000>;
382 no-map;
383 };
384
385 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
386 reg = <0x0 0x8df80000 0x0 0x80000>;
387 no-map;
388 };
389
390 mpssadsp_mem: mpssadsp@8e000000 {
391 reg = <0x0 0x8e000000 0x0 0xf400000>;
392 no-map;
393 };
394
395 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
396 reg = <0x0 0xbdb00000 0x0 0x2000000>;
397 no-map;
398 };
399
400 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
401 reg = <0x0 0xbfb00000 0x0 0x100000>;
402 no-map;
403 };
404
405 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
406 reg = <0x0 0xbfc00000 0x0 0x400000>;
407 no-map;
408 };
409 };
410
411 smp2p-modem {
412 compatible = "qcom,smp2p";
413 qcom,smem = <435>, <428>;
414 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
415 IPCC_MPROC_SIGNAL_SMP2P
416 IRQ_TYPE_EDGE_RISING>;
417 mboxes = <&ipcc IPCC_CLIENT_MPSS
418 IPCC_MPROC_SIGNAL_SMP2P>;
419
420 qcom,local-pid = <0>;
421 qcom,remote-pid = <1>;
422
423 smp2p_modem_out: master-kernel {
424 qcom,entry-name = "master-kernel";
425 #qcom,smem-state-cells = <1>;
426 };
427
428 smp2p_modem_in: slave-kernel {
429 qcom,entry-name = "slave-kernel";
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 };
433
434 ipa_smp2p_out: ipa-ap-to-modem {
435 qcom,entry-name = "ipa";
436 #qcom,smem-state-cells = <1>;
437 };
438
439 ipa_smp2p_in: ipa-modem-to-ap {
440 qcom,entry-name = "ipa";
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 };
444 };
445
446 smem: smem {
447 compatible = "qcom,smem";
448 memory-region = <&smem_mem>;
449 hwlocks = <&tcsr_mutex 3>;
450 };
451
452 soc: soc@0 {
453 compatible = "simple-bus";
454 #address-cells = <2>;
455 #size-cells = <2>;
456 ranges = <0 0 0 0 0x10 0>;
457 dma-ranges = <0 0 0 0 0x10 0>;
458
459 gcc: clock-controller@80000 {
460 compatible = "qcom,sdx75-gcc";
461 reg = <0x0 0x0080000 0x0 0x1f7400>;
462 clocks = <&rpmhcc RPMH_CXO_CLK>,
463 <&sleep_clk>,
464 <0>,
465 <0>,
466 <0>,
467 <0>,
468 <0>,
469 <0>,
470 <0>,
471 <0>,
472 <0>,
473 <0>,
474 <0>,
475 <0>,
476 <0>;
477 #clock-cells = <1>;
478 #reset-cells = <1>;
479 #power-domain-cells = <1>;
480 };
481
482 ipcc: mailbox@408000 {
483 compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
484 reg = <0 0x00408000 0 0x1000>;
485 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-controller;
487 #interrupt-cells = <3>;
488 #mbox-cells = <2>;
489 };
490
491 gpi_dma: dma-controller@900000 {
492 compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
493 reg = <0x0 0x00900000 0x0 0x60000>;
494 #dma-cells = <3>;
495 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
507 dma-channels = <12>;
508 dma-channel-mask = <0x7f>;
509 iommus = <&apps_smmu 0xf6 0x0>;
510 status = "disabled";
511 };
512
513 qupv3_id_0: geniqup@9c0000 {
514 compatible = "qcom,geni-se-qup";
515 reg = <0x0 0x009c0000 0x0 0x2000>;
516 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
517 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
518 clock-names = "m-ahb",
519 "s-ahb";
520 iommus = <&apps_smmu 0xe3 0x0>;
521 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
522 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
523 interconnect-names = "qup-core";
524 #address-cells = <2>;
525 #size-cells = <2>;
526 ranges;
527 status = "disabled";
528
529 i2c0: i2c@980000 {
530 compatible = "qcom,geni-i2c";
531 reg = <0x0 0x00980000 0x0 0x4000>;
532 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
533 clock-names = "se";
534 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 pinctrl-0 = <&qup_i2c0_data_clk>;
538 pinctrl-names = "default";
539 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
540 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
542 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
543 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
545 interconnect-names = "qup-core", "qup-config", "qup-memory";
546 dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
547 <&gpi_dma 1 0 QCOM_GPI_I2C>;
548 dma-names = "tx", "rx";
549 status = "disabled";
550 };
551
552 spi0: spi@980000 {
553 compatible = "qcom,geni-spi";
554 reg = <0x0 0x00980000 0x0 0x4000>;
555 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
556 clock-names = "se";
557 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
561 pinctrl-names = "default";
562 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
563 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
564 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
565 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
566 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
567 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
568 interconnect-names = "qup-core", "qup-config", "qup-memory";
569 dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
570 <&gpi_dma 1 0 QCOM_GPI_SPI>;
571 dma-names = "tx", "rx";
572 status = "disabled";
573 };
574
575 uart1: serial@984000 {
576 compatible = "qcom,geni-debug-uart";
577 reg = <0x0 0x00984000 0x0 0x4000>;
578 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
579 clock-names = "se";
580 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
581 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
582 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
583 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
584 interconnect-names = "qup-core",
585 "qup-config";
586 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
587 pinctrl-0 = <&qupv3_se1_2uart_active>;
588 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
589 pinctrl-names = "default",
590 "sleep";
591 status = "disabled";
592 };
593
594 i2c2: i2c@988000 {
595 compatible = "qcom,geni-i2c";
596 reg = <0x0 0x00988000 0x0 0x4000>;
597 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
598 clock-names = "se";
599 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
601 #size-cells = <0>;
602 pinctrl-0 = <&qup_i2c2_data_clk>;
603 pinctrl-names = "default";
604 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
605 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
606 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
607 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
608 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
610 interconnect-names = "qup-core", "qup-config", "qup-memory";
611 dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
612 <&gpi_dma 1 2 QCOM_GPI_I2C>;
613 dma-names = "tx", "rx";
614 status = "disabled";
615 };
616
617 spi2: spi@988000 {
618 compatible = "qcom,geni-spi";
619 reg = <0x0 0x00988000 0x0 0x4000>;
620 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
621 clock-names = "se";
622 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
626 pinctrl-names = "default";
627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
630 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
631 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
633 interconnect-names = "qup-core", "qup-config", "qup-memory";
634 dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
635 <&gpi_dma 1 2 QCOM_GPI_SPI>;
636 dma-names = "tx", "rx";
637 status = "disabled";
638 };
639
640 i2c3: i2c@98c000 {
641 compatible = "qcom,geni-i2c";
642 reg = <0x0 0x0098c000 0x0 0x4000>;
643 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
644 clock-names = "se";
645 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
646 #address-cells = <1>;
647 #size-cells = <0>;
648 pinctrl-0 = <&qup_i2c3_data_clk>;
649 pinctrl-names = "default";
650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
653 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
654 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
656 interconnect-names = "qup-core", "qup-config", "qup-memory";
657 dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
658 <&gpi_dma 1 3 QCOM_GPI_I2C>;
659 dma-names = "tx", "rx";
660 status = "disabled";
661 };
662
663 spi3: spi@98c000 {
664 compatible = "qcom,geni-spi";
665 reg = <0x0 0x0098c000 0x0 0x4000>;
666 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
667 clock-names = "se";
668 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
669 #address-cells = <1>;
670 #size-cells = <0>;
671 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
672 pinctrl-names = "default";
673 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
674 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
675 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
676 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
677 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
678 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
679 interconnect-names = "qup-core", "qup-config", "qup-memory";
680 dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
681 <&gpi_dma 1 3 QCOM_GPI_SPI>;
682 dma-names = "tx", "rx";
683 status = "disabled";
684 };
685
686 uart4: serial@990000 {
687 compatible = "qcom,geni-uart";
688 reg = <0x0 0x00990000 0x0 0x4000>;
689 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
690 clock-names = "se";
691 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
692 pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
693 pinctrl-names = "default";
694 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
695 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
696 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
697 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
698 interconnect-names = "qup-core", "qup-config";
699 status = "disabled";
700 };
701
702 i2c5: i2c@994000 {
703 compatible = "qcom,geni-i2c";
704 reg = <0x0 0x00994000 0x0 0x4000>;
705 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
706 clock-names = "se";
707 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 pinctrl-0 = <&qup_i2c5_data_clk>;
711 pinctrl-names = "default";
712 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
713 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
714 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
715 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
716 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
718 interconnect-names = "qup-core", "qup-config", "qup-memory";
719 dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
720 <&gpi_dma 1 5 QCOM_GPI_I2C>;
721 dma-names = "tx", "rx";
722 status = "disabled";
723 };
724
725 i2c6: i2c@998000 {
726 compatible = "qcom,geni-i2c";
727 reg = <0x0 0x00998000 0x0 0x4000>;
728 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
729 clock-names = "se";
730 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 pinctrl-0 = <&qup_i2c6_data_clk>;
734 pinctrl-names = "default";
735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
737 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
738 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
739 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
741 interconnect-names = "qup-core", "qup-config", "qup-memory";
742 dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
743 <&gpi_dma 1 6 QCOM_GPI_I2C>;
744 dma-names = "tx", "rx";
745 status = "disabled";
746 };
747
748 spi6: spi@998000 {
749 compatible = "qcom,geni-spi";
750 reg = <0x0 0x00998000 0x0 0x4000>;
751 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
752 clock-names = "se";
753 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
754 #address-cells = <1>;
755 #size-cells = <0>;
756 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
757 pinctrl-names = "default";
758 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
759 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
760 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
761 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
762 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
763 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
764 interconnect-names = "qup-core", "qup-config", "qup-memory";
765 dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
766 <&gpi_dma 1 6 QCOM_GPI_SPI>;
767 dma-names = "tx", "rx";
768 status = "disabled";
769 };
770
771 i2c7: i2c@99c000 {
772 compatible = "qcom,geni-i2c";
773 reg = <0x0 0x0099c000 0x0 0x4000>;
774 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
775 clock-names = "se";
776 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
777 #address-cells = <1>;
778 #size-cells = <0>;
779 pinctrl-0 = <&qup_i2c7_data_clk>;
780 pinctrl-names = "default";
781 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
782 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
783 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
784 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
785 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
786 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
787 interconnect-names = "qup-core", "qup-config", "qup-memory";
788 dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
789 <&gpi_dma 1 7 QCOM_GPI_I2C>;
790 dma-names = "tx", "rx";
791 status = "disabled";
792 };
793
794 spi7: spi@99c000 {
795 compatible = "qcom,geni-spi";
796 reg = <0x0 0x0099c000 0x0 0x4000>;
797 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
798 clock-names = "se";
799 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
803 pinctrl-names = "default";
804 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
805 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
806 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
807 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
808 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
810 interconnect-names = "qup-core", "qup-config", "qup-memory";
811 dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
812 <&gpi_dma 1 7 QCOM_GPI_SPI>;
813 dma-names = "tx", "rx";
814 status = "disabled";
815 };
816 };
817
818 usb_hsphy: phy@ff4000 {
819 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
820 reg = <0x0 0x00ff4000 0x0 0x154>;
821 #phy-cells = <0>;
822
823 clocks = <&rpmhcc RPMH_CXO_CLK>;
824 clock-names = "ref";
825
826 resets = <&gcc GCC_QUSB2PHY_BCR>;
827
828 status = "disabled";
829 };
830
831 usb_qmpphy: phy@ff6000 {
832 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
833 reg = <0x0 0x00ff6000 0x0 0x2000>;
834
835 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
836 <&gcc GCC_USB2_CLKREF_EN>,
837 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
838 <&gcc GCC_USB3_PHY_PIPE_CLK>;
839 clock-names = "aux",
840 "ref",
841 "cfg_ahb",
842 "pipe";
843
844 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
845
846 resets = <&gcc GCC_USB3_PHY_BCR>,
847 <&gcc GCC_USB3PHY_PHY_BCR>;
848 reset-names = "phy",
849 "phy_phy";
850
851 #clock-cells = <0>;
852 clock-output-names = "usb3_uni_phy_pipe_clk_src";
853
854 #phy-cells = <0>;
855
856 status = "disabled";
857 };
858
859 system_noc: interconnect@1640000 {
860 compatible = "qcom,sdx75-system-noc";
861 reg = <0x0 0x01640000 0x0 0x4b400>;
862 #interconnect-cells = <2>;
863 qcom,bcm-voters = <&apps_bcm_voter>;
864 };
865
866 pcie_anoc: interconnect@16c0000 {
867 compatible = "qcom,sdx75-pcie-anoc";
868 reg = <0x0 0x016c0000 0x0 0x14200>;
869 #interconnect-cells = <2>;
870 qcom,bcm-voters = <&apps_bcm_voter>;
871 };
872
873 tcsr_mutex: hwlock@1f40000 {
874 compatible = "qcom,tcsr-mutex";
875 reg = <0x0 0x01f40000 0x0 0x40000>;
876 #hwlock-cells = <1>;
877 };
878
879 tcsr: syscon@1fc0000 {
880 compatible = "qcom,sdx75-tcsr", "syscon";
881 reg = <0x0 0x01fc0000 0x0 0x30000>;
882 };
883
884 sdhc: mmc@8804000 {
885 compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
886 reg = <0x0 0x08804000 0x0 0x1000>;
887
888 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
890 interrupt-names = "hc_irq",
891 "pwr_irq";
892
893 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
894 <&gcc GCC_SDCC1_APPS_CLK>,
895 <&rpmhcc RPMH_CXO_CLK>;
896 clock-names = "iface",
897 "core",
898 "xo";
899 iommus = <&apps_smmu 0x00a0 0x0>;
900 qcom,dll-config = <0x0007442c>;
901 qcom,ddr-config = <0x80040868>;
902 power-domains = <&rpmhpd RPMHPD_CX>;
903 operating-points-v2 = <&sdhc1_opp_table>;
904
905 interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
906 <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
907 interconnect-names = "sdhc-ddr",
908 "cpu-sdhc";
909 bus-width = <4>;
910 dma-coherent;
911
912 /* Forbid SDR104/SDR50 - broken hw! */
913 sdhci-caps-mask = <0x3 0>;
914
915 status = "disabled";
916
917 sdhc1_opp_table: opp-table {
918 compatible = "operating-points-v2";
919
920 opp-100000000 {
921 opp-hz = /bits/ 64 <100000000>;
922 required-opps = <&rpmhpd_opp_low_svs>;
923 };
924
925 opp-384000000 {
926 opp-hz = /bits/ 64 <384000000>;
927 required-opps = <&rpmhpd_opp_nom>;
928 };
929 };
930 };
931
932 usb: usb@a6f8800 {
933 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
934 reg = <0x0 0x0a6f8800 0x0 0x400>;
935 #address-cells = <2>;
936 #size-cells = <2>;
937 ranges;
938
939 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
940 <&gcc GCC_USB30_MASTER_CLK>,
941 <&gcc GCC_USB30_MSTR_AXI_CLK>,
942 <&gcc GCC_USB30_SLEEP_CLK>,
943 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
944 clock-names = "cfg_noc",
945 "core",
946 "iface",
947 "sleep",
948 "mock_utmi";
949
950 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
951 <&gcc GCC_USB30_MASTER_CLK>;
952 assigned-clock-rates = <19200000>, <200000000>;
953
954 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
955 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
956 <&pdc 9 IRQ_TYPE_EDGE_RISING>,
957 <&pdc 10 IRQ_TYPE_EDGE_RISING>;
958 interrupt-names = "hs_phy_irq",
959 "ss_phy_irq",
960 "dm_hs_phy_irq",
961 "dp_hs_phy_irq";
962
963 power-domains = <&gcc GCC_USB30_GDSC>;
964
965 resets = <&gcc GCC_USB30_BCR>;
966
967 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
968 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
969 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
970 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
971 interconnect-names = "usb-ddr",
972 "apps-usb";
973
974 status = "disabled";
975
976 usb_dwc3: usb@a600000 {
977 compatible = "snps,dwc3";
978 reg = <0x0 0x0a600000 0x0 0xcd00>;
979 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
980 iommus = <&apps_smmu 0x80 0x0>;
981 snps,dis_u2_susphy_quirk;
982 snps,dis_enblslpm_quirk;
983 phys = <&usb_hsphy>,
984 <&usb_qmpphy>;
985 phy-names = "usb2-phy",
986 "usb3-phy";
987
988 ports {
989 #address-cells = <1>;
990 #size-cells = <0>;
991
992 port@0 {
993 reg = <0>;
994
995 usb_1_dwc3_hs: endpoint {
996 };
997 };
998
999 port@1 {
1000 reg = <1>;
1001
1002 usb_1_dwc3_ss: endpoint {
1003 };
1004 };
1005 };
1006 };
1007 };
1008
1009 pdc: interrupt-controller@b220000 {
1010 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1011 reg = <0x0 0xb220000 0x0 0x30000>,
1012 <0x0 0x174000f0 0x0 0x64>;
1013 qcom,pdc-ranges = <0 147 52>,
1014 <52 266 32>,
1015 <84 500 59>;
1016 #interrupt-cells = <2>;
1017 interrupt-parent = <&intc>;
1018 interrupt-controller;
1019 };
1020
1021 aoss_qmp: power-controller@c310000 {
1022 compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
1023 reg = <0 0x0c310000 0 0x1000>;
1024 interrupt-parent = <&ipcc>;
1025 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1026 IRQ_TYPE_EDGE_RISING>;
1027 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1028
1029 #clock-cells = <0>;
1030 };
1031
1032 spmi_bus: spmi@c400000 {
1033 compatible = "qcom,spmi-pmic-arb";
1034 reg = <0x0 0x0c400000 0x0 0x3000>,
1035 <0x0 0x0c500000 0x0 0x400000>,
1036 <0x0 0x0c440000 0x0 0x80000>,
1037 <0x0 0x0c4c0000 0x0 0x10000>,
1038 <0x0 0x0c42d000 0x0 0x4000>;
1039 reg-names = "core",
1040 "chnls",
1041 "obsrvr",
1042 "intr",
1043 "cnfg";
1044 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1045 interrupt-names = "periph_irq";
1046 qcom,ee = <0>;
1047 qcom,channel = <0>;
1048 qcom,bus-id = <0>;
1049 #address-cells = <2>;
1050 #size-cells = <0>;
1051 interrupt-controller;
1052 #interrupt-cells = <4>;
1053 };
1054
1055 tlmm: pinctrl@f000000 {
1056 compatible = "qcom,sdx75-tlmm";
1057 reg = <0x0 0x0f000000 0x0 0x400000>;
1058 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1059 gpio-controller;
1060 #gpio-cells = <2>;
1061 gpio-ranges = <&tlmm 0 0 133>;
1062 interrupt-controller;
1063 #interrupt-cells = <2>;
1064 wakeup-parent = <&pdc>;
1065
1066 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
1067 /* SDA, SCL */
1068 pins = "gpio8", "gpio9";
1069 function = "qup_se0";
1070 drive-strength = <2>;
1071 bias-pull-up;
1072 };
1073
1074 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1075 /* SDA, SCL */
1076 pins = "gpio14", "gpio15";
1077 function = "qup_se2";
1078 drive-strength = <2>;
1079 bias-pull-up;
1080 };
1081
1082 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1083 /* SDA, SCL */
1084 pins = "gpio52", "gpio53";
1085 function = "qup_se3";
1086 drive-strength = <2>;
1087 bias-pull-up;
1088 };
1089
1090 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1091 /* SDA, SCL */
1092 pins = "gpio110", "gpio111";
1093 function = "qup_se5";
1094 drive-strength = <2>;
1095 bias-pull-up;
1096 };
1097
1098 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1099 /* SDA, SCL */
1100 pins = "gpio112", "gpio113";
1101 function = "qup_se6";
1102 drive-strength = <2>;
1103 bias-pull-up;
1104 };
1105
1106 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1107 /* SDA, SCL */
1108 pins = "gpio116", "gpio117";
1109 function = "qup_se7";
1110 drive-strength = <2>;
1111 bias-pull-up;
1112 };
1113
1114 qup_spi0_cs: qup-spi0-cs-state {
1115 pins = "gpio11";
1116 function = "qup_se0";
1117 drive-strength = <6>;
1118 bias-pull-down;
1119 };
1120
1121 qup_spi0_data_clk: qup-spi0-data-clk-state {
1122 /* MISO, MOSI, CLK */
1123 pins = "gpio8", "gpio9", "gpio10";
1124 function = "qup_se0";
1125 drive-strength = <6>;
1126 bias-pull-down;
1127 };
1128
1129 qup_spi2_cs: qup-spi2-cs-state {
1130 pins = "gpio17";
1131 function = "qup_se2";
1132 drive-strength = <6>;
1133 bias-pull-down;
1134 };
1135
1136 qup_spi2_data_clk: qup-spi2-data-clk-state {
1137 /* MISO, MOSI, CLK */
1138 pins = "gpio14", "gpio15", "gpio16";
1139 function = "qup_se2";
1140 drive-strength = <6>;
1141 bias-pull-down;
1142 };
1143
1144 qup_spi3_cs: qup-spi3-cs-state {
1145 pins = "gpio55";
1146 function = "qup_se3";
1147 drive-strength = <6>;
1148 bias-pull-down;
1149 };
1150
1151 qup_spi3_data_clk: qup-spi3-data-clk-state {
1152 /* MISO, MOSI, CLK */
1153 pins = "gpio52", "gpio53", "gpio54";
1154 function = "qup_se3";
1155 drive-strength = <6>;
1156 bias-pull-down;
1157 };
1158
1159 qup_spi6_cs: qup-spi6-cs-state {
1160 pins = "gpio115";
1161 function = "qup_se6";
1162 drive-strength = <6>;
1163 bias-pull-down;
1164 };
1165
1166 qup_spi6_data_clk: qup-spi6-data-clk-state {
1167 /* MISO, MOSI, CLK */
1168 pins = "gpio112", "gpio113", "gpio114";
1169 function = "qup_se6";
1170 drive-strength = <6>;
1171 bias-pull-down;
1172 };
1173
1174 qup_spi7_cs: qup-spi7-cs-state {
1175 pins = "gpio119";
1176 function = "qup_se7";
1177 drive-strength = <6>;
1178 bias-pull-down;
1179 };
1180
1181 qup_spi7_data_clk: qup-spi7-data-clk-state {
1182 /* MISO, MOSI, CLK */
1183 pins = "gpio116", "gpio117", "gpio118";
1184 function = "qup_se7";
1185 drive-strength = <6>;
1186 bias-pull-down;
1187 };
1188
1189 qup_uart4_cts_rts: qup-uart4-cts-rts-state {
1190 /* CTS, RTS */
1191 pins = "gpio52", "gpio53";
1192 function = "qup_se3";
1193 drive-strength = <2>;
1194 bias-pull-down;
1195 };
1196
1197 qup_uart4_default: qup-uart4-default-state {
1198 /* TX, RX */
1199 pins = "gpio54", "gpio55";
1200 function = "qup_se3";
1201 drive-strength = <2>;
1202 bias-pull-up;
1203 };
1204
1205 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1206 tx-pins {
1207 pins = "gpio12";
1208 function = "qup_se1_l2_mira";
1209 drive-strength = <2>;
1210 bias-disable;
1211 };
1212
1213 rx-pins {
1214 pins = "gpio13";
1215 function = "qup_se1_l3_mira";
1216 drive-strength = <2>;
1217 bias-disable;
1218 };
1219 };
1220
1221 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1222 pins = "gpio12", "gpio13";
1223 function = "gpio";
1224 drive-strength = <2>;
1225 bias-pull-down;
1226 };
1227
1228 sdc1_default: sdc1-default-state {
1229 clk-pins {
1230 pins = "sdc1_clk";
1231 drive-strength = <16>;
1232 bias-disable;
1233 };
1234
1235 cmd-pins {
1236 pins = "sdc1_cmd";
1237 drive-strength = <10>;
1238 bias-pull-up;
1239 };
1240
1241 data-pins {
1242 pins = "sdc1_data";
1243 drive-strength = <10>;
1244 bias-pull-up;
1245 };
1246 };
1247
1248 sdc1_sleep: sdc1-sleep-state {
1249 clk-pins {
1250 pins = "sdc1_clk";
1251 drive-strength = <2>;
1252 bias-disable;
1253 };
1254
1255 cmd-pins {
1256 pins = "sdc1_cmd";
1257 drive-strength = <2>;
1258 bias-pull-up;
1259 };
1260
1261 data-pins {
1262 pins = "sdc1_data";
1263 drive-strength = <2>;
1264 bias-pull-up;
1265 };
1266 };
1267 };
1268
1269 apps_smmu: iommu@15000000 {
1270 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1271 reg = <0x0 0x15000000 0x0 0x40000>;
1272 #iommu-cells = <2>;
1273 #global-interrupts = <2>;
1274 dma-coherent;
1275 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1308 };
1309
1310 intc: interrupt-controller@17200000 {
1311 compatible = "arm,gic-v3";
1312 #interrupt-cells = <3>;
1313 interrupt-controller;
1314 #redistributor-regions = <1>;
1315 redistributor-stride = <0x0 0x20000>;
1316 reg = <0x0 0x17200000 0x0 0x10000>,
1317 <0x0 0x17260000 0x0 0x80000>;
1318 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1319 };
1320
1321 timer@17420000 {
1322 compatible = "arm,armv7-timer-mem";
1323 reg = <0x0 0x17420000 0x0 0x1000>;
1324 #address-cells = <1>;
1325 #size-cells = <1>;
1326 ranges = <0 0 0 0x20000000>;
1327
1328 frame@17421000 {
1329 reg = <0x17421000 0x1000>,
1330 <0x17422000 0x1000>;
1331 frame-number = <0>;
1332 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1334 };
1335
1336 frame@17423000 {
1337 reg = <0x17423000 0x1000>;
1338 frame-number = <1>;
1339 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1340 status = "disabled";
1341 };
1342
1343 frame@17425000 {
1344 reg = <0x17425000 0x1000>;
1345 frame-number = <2>;
1346 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1347 status = "disabled";
1348 };
1349
1350 frame@17427000 {
1351 reg = <0x17427000 0x1000>;
1352 frame-number = <3>;
1353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1354 status = "disabled";
1355 };
1356
1357 frame@17429000 {
1358 reg = <0x17429000 0x1000>;
1359 frame-number = <4>;
1360 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1361 status = "disabled";
1362 };
1363
1364 frame@1742b000 {
1365 reg = <0x1742b000 0x1000>;
1366 frame-number = <5>;
1367 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1368 status = "disabled";
1369 };
1370
1371 frame@1742d000 {
1372 reg = <0x1742d000 0x1000>;
1373 frame-number = <6>;
1374 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1375 status = "disabled";
1376 };
1377 };
1378
1379 apps_rsc: rsc@17a00000 {
1380 label = "apps_rsc";
1381 compatible = "qcom,rpmh-rsc";
1382 reg = <0x0 0x17a00000 0x0 0x10000>,
1383 <0x0 0x17a10000 0x0 0x10000>,
1384 <0x0 0x17a20000 0x0 0x10000>;
1385 reg-names = "drv-0", "drv-1", "drv-2";
1386 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1389
1390 power-domains = <&CLUSTER_PD>;
1391 qcom,tcs-offset = <0xd00>;
1392 qcom,drv-id = <2>;
1393 qcom,tcs-config = <ACTIVE_TCS 3>,
1394 <SLEEP_TCS 2>,
1395 <WAKE_TCS 2>,
1396 <CONTROL_TCS 0>;
1397
1398 apps_bcm_voter: bcm-voter {
1399 compatible = "qcom,bcm-voter";
1400 };
1401
1402 rpmhcc: clock-controller {
1403 compatible = "qcom,sdx75-rpmh-clk";
1404 clocks = <&xo_board>;
1405 clock-names = "xo";
1406 #clock-cells = <1>;
1407 };
1408
1409 rpmhpd: power-controller {
1410 compatible = "qcom,sdx75-rpmhpd";
1411 #power-domain-cells = <1>;
1412 operating-points-v2 = <&rpmhpd_opp_table>;
1413
1414 rpmhpd_opp_table: opp-table {
1415 compatible = "operating-points-v2";
1416
1417 rpmhpd_opp_ret: opp-16 {
1418 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1419 };
1420
1421 rpmhpd_opp_min_svs: opp-48 {
1422 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1423 };
1424
1425 rpmhpd_opp_low_svs: opp-64 {
1426 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1427 };
1428
1429 rpmhpd_opp_svs: opp-128 {
1430 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1431 };
1432
1433 rpmhpd_opp_svs_l1: opp-192 {
1434 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1435 };
1436
1437 rpmhpd_opp_nom: opp-256 {
1438 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1439 };
1440
1441 rpmhpd_opp_nom_l1: opp-320 {
1442 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1443 };
1444
1445 rpmhpd_opp_nom_l2: opp-336 {
1446 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1447 };
1448
1449 rpmhpd_opp_turbo: opp-384 {
1450 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1451 };
1452
1453 rpmhpd_opp_turbo_l1: opp-416 {
1454 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1455 };
1456 };
1457 };
1458 };
1459
1460 cpufreq_hw: cpufreq@17d91000 {
1461 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1462 reg = <0x0 0x17d91000 0x0 0x1000>;
1463 reg-names = "freq-domain0";
1464 clocks = <&rpmhcc RPMH_CXO_CLK>,
1465 <&gcc GPLL0>;
1466 clock-names = "xo",
1467 "alternate";
1468 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1469 interrupt-names = "dcvsh-irq-0";
1470 #freq-domain-cells = <1>;
1471 #clock-cells = <1>;
1472 };
1473
1474 dc_noc: interconnect@190e0000 {
1475 compatible = "qcom,sdx75-dc-noc";
1476 reg = <0x0 0x190e0000 0x0 0x8200>;
1477 #interconnect-cells = <2>;
1478 qcom,bcm-voters = <&apps_bcm_voter>;
1479 };
1480
1481 gem_noc: interconnect@19100000 {
1482 compatible = "qcom,sdx75-gem-noc";
1483 reg = <0x0 0x19100000 0x0 0x34080>;
1484 #interconnect-cells = <2>;
1485 qcom,bcm-voters = <&apps_bcm_voter>;
1486 };
1487 };
1488
1489 timer {
1490 compatible = "arm,armv8-timer";
1491 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1492 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1493 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1494 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1495 };
1496 };
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