1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
14
15 / {
16 interrupt-parent = <&intc>;
17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 clocks {
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 clock-frequency = <76800000>;
27 #clock-cells = <0>;
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
34 };
35
36 bi_tcxo_div2: bi-tcxo-div2-clk {
37 #clock-cells = <0>;
38 compatible = "fixed-factor-clock";
39 clocks = <&rpmhcc RPMH_CXO_CLK>;
40 clock-mult = <1>;
41 clock-div = <2>;
42 };
43 };
44
45 cpus {
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
54 enable-method = "psci";
55 next-level-cache = <&L2_0>;
56 power-domains = <&CPU_PD0>;
57 power-domain-names = "psci";
58 qcom,freq-domain = <&cpufreq_hw 0>;
59 #cooling-cells = <2>;
60
61 L2_0: l2-cache {
62 compatible = "cache";
63 cache-level = <2>;
64 cache-unified;
65 next-level-cache = <&L3_0>;
66
67 L3_0: l3-cache {
68 compatible = "cache";
69 cache-level = <3>;
70 cache-unified;
71 };
72 };
73 };
74
75 CPU1: cpu@100 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a55";
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci";
81 next-level-cache = <&L2_100>;
82 power-domains = <&CPU_PD0>;
83 power-domain-names = "psci";
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 #cooling-cells = <2>;
86
87 L2_100: l2-cache {
88 compatible = "cache";
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
92 };
93 };
94
95 CPU2: cpu@200 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a55";
98 reg = <0x0 0x200>;
99 clocks = <&cpufreq_hw 0>;
100 enable-method = "psci";
101 next-level-cache = <&L2_200>;
102 power-domains = <&CPU_PD0>;
103 power-domain-names = "psci";
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 #cooling-cells = <2>;
106
107 L2_200: l2-cache {
108 compatible = "cache";
109 cache-level = <2>;
110 cache-unified;
111 next-level-cache = <&L3_0>;
112 };
113 };
114
115 CPU3: cpu@300 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a55";
118 reg = <0x0 0x300>;
119 clocks = <&cpufreq_hw 0>;
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD0>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
126
127 L2_300: l2-cache {
128 compatible = "cache";
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
132 };
133 };
134
135 CPU4: cpu@400 {
136 device_type = "cpu";
137 compatible = "arm,cortex-a55";
138 reg = <0x0 0x400>;
139 clocks = <&cpufreq_hw 0>;
140 enable-method = "psci";
141 next-level-cache = <&L2_400>;
142 power-domains = <&CPU_PD0>;
143 power-domain-names = "psci";
144 qcom,freq-domain = <&cpufreq_hw 0>;
145 #cooling-cells = <2>;
146
147 L2_400: l2-cache {
148 compatible = "cache";
149 cache-level = <2>;
150 cache-unified;
151 next-level-cache = <&L3_0>;
152 };
153 };
154
155 CPU5: cpu@500 {
156 device_type = "cpu";
157 compatible = "arm,cortex-a55";
158 reg = <0x0 0x500>;
159 clocks = <&cpufreq_hw 0>;
160 enable-method = "psci";
161 next-level-cache = <&L2_500>;
162 power-domains = <&CPU_PD0>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 #cooling-cells = <2>;
166
167 L2_500: l2-cache {
168 compatible = "cache";
169 cache-level = <2>;
170 cache-unified;
171 next-level-cache = <&L3_0>;
172 };
173 };
174
175 CPU6: cpu@600 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a78";
178 reg = <0x0 0x600>;
179 clocks = <&cpufreq_hw 1>;
180 enable-method = "psci";
181 next-level-cache = <&L2_600>;
182 power-domains = <&CPU_PD0>;
183 power-domain-names = "psci";
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 #cooling-cells = <2>;
186
187 L2_600: l2-cache {
188 compatible = "cache";
189 cache-level = <2>;
190 cache-unified;
191 next-level-cache = <&L3_0>;
192 };
193 };
194
195 CPU7: cpu@700 {
196 device_type = "cpu";
197 compatible = "arm,cortex-a78";
198 reg = <0x0 0x700>;
199 clocks = <&cpufreq_hw 1>;
200 enable-method = "psci";
201 next-level-cache = <&L2_700>;
202 power-domains = <&CPU_PD0>;
203 power-domain-names = "psci";
204 qcom,freq-domain = <&cpufreq_hw 1>;
205 #cooling-cells = <2>;
206
207 L2_700: l2-cache {
208 compatible = "cache";
209 cache-level = <2>;
210 cache-unified;
211 next-level-cache = <&L3_0>;
212 };
213 };
214
215 cpu-map {
216 cluster0 {
217 core0 {
218 cpu = <&CPU0>;
219 };
220
221 core1 {
222 cpu = <&CPU1>;
223 };
224
225 core2 {
226 cpu = <&CPU2>;
227 };
228
229 core3 {
230 cpu = <&CPU3>;
231 };
232
233 core4 {
234 cpu = <&CPU4>;
235 };
236
237 core5 {
238 cpu = <&CPU5>;
239 };
240
241 core6 {
242 cpu = <&CPU6>;
243 };
244
245 core7 {
246 cpu = <&CPU7>;
247 };
248 };
249 };
250
251 idle-states {
252 entry-method = "psci";
253
254 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
255 compatible = "arm,idle-state";
256 arm,psci-suspend-param = <0x40000004>;
257 entry-latency-us = <800>;
258 exit-latency-us = <750>;
259 min-residency-us = <4090>;
260 local-timer-stop;
261 };
262
263 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
264 compatible = "arm,idle-state";
265 arm,psci-suspend-param = <0x40000004>;
266 entry-latency-us = <600>;
267 exit-latency-us = <1550>;
268 min-residency-us = <4791>;
269 local-timer-stop;
270 };
271 };
272
273 domain-idle-states {
274 CLUSTER_SLEEP_0: cluster-sleep-0 {
275 compatible = "domain-idle-state";
276 arm,psci-suspend-param = <0x41000044>;
277 entry-latency-us = <1050>;
278 exit-latency-us = <2500>;
279 min-residency-us = <5309>;
280 };
281
282 CLUSTER_SLEEP_1: cluster-sleep-1 {
283 compatible = "domain-idle-state";
284 arm,psci-suspend-param = <0x41003344>;
285 entry-latency-us = <1561>;
286 exit-latency-us = <2801>;
287 min-residency-us = <8550>;
288 };
289 };
290 };
291
292 memory@a0000000 {
293 device_type = "memory";
294 /* We expect the bootloader to fill in the size */
295 reg = <0x0 0xa0000000 0x0 0x0>;
296 };
297
298 pmu-a55 {
299 compatible = "arm,cortex-a55-pmu";
300 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
301 };
302
303 pmu-a78 {
304 compatible = "arm,cortex-a78-pmu";
305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
306 };
307
308 psci {
309 compatible = "arm,psci-1.0";
310 method = "smc";
311
312 CPU_PD0: power-domain-cpu0 {
313 #power-domain-cells = <0>;
314 power-domains = <&CLUSTER_PD>;
315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
316 };
317
318 CPU_PD1: power-domain-cpu1 {
319 #power-domain-cells = <0>;
320 power-domains = <&CLUSTER_PD>;
321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
322 };
323
324 CPU_PD2: power-domain-cpu2 {
325 #power-domain-cells = <0>;
326 power-domains = <&CLUSTER_PD>;
327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
328 };
329
330 CPU_PD3: power-domain-cpu3 {
331 #power-domain-cells = <0>;
332 power-domains = <&CLUSTER_PD>;
333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
334 };
335
336 CPU_PD4: power-domain-cpu4 {
337 #power-domain-cells = <0>;
338 power-domains = <&CLUSTER_PD>;
339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
340 };
341
342 CPU_PD5: power-domain-cpu5 {
343 #power-domain-cells = <0>;
344 power-domains = <&CLUSTER_PD>;
345 domain-idle-states = <&BIG_CPU_SLEEP_0>;
346 };
347
348 CPU_PD6: power-domain-cpu6 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD>;
351 domain-idle-states = <&BIG_CPU_SLEEP_0>;
352 };
353
354 CPU_PD7: power-domain-cpu7 {
355 #power-domain-cells = <0>;
356 power-domains = <&CLUSTER_PD>;
357 domain-idle-states = <&BIG_CPU_SLEEP_0>;
358 };
359
360 CLUSTER_PD: power-domain-cpu-cluster0 {
361 #power-domain-cells = <0>;
362 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
363 };
364 };
365
366 reserved_memory: reserved-memory {
367 #address-cells = <2>;
368 #size-cells = <2>;
369 ranges;
370
371 aop_cmd_db_mem: cmd-db@80860000 {
372 compatible = "qcom,cmd-db";
373 reg = <0x0 0x80860000 0x0 0x20000>;
374 no-map;
375 };
376 };
377
378 soc: soc@0 {
379 #address-cells = <2>;
380 #size-cells = <2>;
381 ranges = <0 0 0 0 0x10 0>;
382 dma-ranges = <0 0 0 0 0x10 0>;
383 compatible = "simple-bus";
384
385 gcc: clock-controller@100000 {
386 compatible = "qcom,sm4450-gcc";
387 reg = <0x0 0x00100000 0x0 0x1f4200>;
388 #clock-cells = <1>;
389 #reset-cells = <1>;
390 #power-domain-cells = <1>;
391 clocks = <&rpmhcc RPMH_CXO_CLK>,
392 <&sleep_clk>,
393 <0>,
394 <0>,
395 <0>,
396 <0>;
397 };
398
399 qupv3_id_0: geniqup@ac0000 {
400 compatible = "qcom,geni-se-qup";
401 reg = <0x0 0x00ac0000 0x0 0x2000>;
402 ranges;
403 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
404 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
405 clock-names = "m-ahb", "s-ahb";
406 #address-cells = <2>;
407 #size-cells = <2>;
408 status = "disabled";
409
410 uart7: serial@a88000 {
411 compatible = "qcom,geni-debug-uart";
412 reg = <0x0 0x00a88000 0x0 0x4000>;
413 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
414 clock-names = "se";
415 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
416 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
417 pinctrl-names = "default";
418 status = "disabled";
419 };
420 };
421
422 tcsr_mutex: hwlock@1f40000 {
423 compatible = "qcom,tcsr-mutex";
424 reg = <0x0 0x01f40000 0x0 0x40000>;
425 #hwlock-cells = <1>;
426 };
427
428 gpucc: clock-controller@3d90000 {
429 compatible = "qcom,sm4450-gpucc";
430 reg = <0x0 0x03d90000 0x0 0xa000>;
431 clocks = <&rpmhcc RPMH_CXO_CLK>,
432 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
433 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
434 #clock-cells = <1>;
435 #reset-cells = <1>;
436 #power-domain-cells = <1>;
437 };
438
439 camcc: clock-controller@ade0000 {
440 compatible = "qcom,sm4450-camcc";
441 reg = <0x0 0x0ade0000 0x0 0x20000>;
442 clocks = <&rpmhcc RPMH_CXO_CLK>,
443 <&gcc GCC_CAMERA_AHB_CLK>;
444 #clock-cells = <1>;
445 #reset-cells = <1>;
446 #power-domain-cells = <1>;
447 };
448
449 dispcc: clock-controller@af00000 {
450 compatible = "qcom,sm4450-dispcc";
451 reg = <0x0 0x0af00000 0x0 0x20000>;
452 clocks = <&rpmhcc RPMH_CXO_CLK>,
453 <&rpmhcc RPMH_CXO_CLK_A>,
454 <&gcc GCC_DISP_AHB_CLK>,
455 <&sleep_clk>,
456 <0>,
457 <0>;
458 #clock-cells = <1>;
459 #reset-cells = <1>;
460 #power-domain-cells = <1>;
461 };
462
463 pdc: interrupt-controller@b220000 {
464 compatible = "qcom,sm4450-pdc", "qcom,pdc";
465 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
466 qcom,pdc-ranges = <0 480 94>, <94 494 31>,
467 <125 63 1>;
468 #interrupt-cells = <2>;
469 interrupt-parent = <&intc>;
470 interrupt-controller;
471 };
472
473 tlmm: pinctrl@f100000 {
474 compatible = "qcom,sm4450-tlmm";
475 reg = <0x0 0x0f100000 0x0 0x300000>;
476 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 gpio-ranges = <&tlmm 0 0 137>;
482 wakeup-parent = <&pdc>;
483
484 qup_uart7_rx: qup-uart7-rx-state {
485 pins = "gpio23";
486 function = "qup1_se2_l2";
487 drive-strength = <2>;
488 bias-disable;
489 };
490
491 qup_uart7_tx: qup-uart7-tx-state {
492 pins = "gpio22";
493 function = "qup1_se2_l2";
494 drive-strength = <2>;
495 bias-disable;
496 };
497 };
498
499 intc: interrupt-controller@17200000 {
500 compatible = "arm,gic-v3";
501 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
502 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
503 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
504 #interrupt-cells = <3>;
505 interrupt-controller;
506 #redistributor-regions = <1>;
507 redistributor-stride = <0x0 0x20000>;
508 };
509
510 timer@17420000 {
511 compatible = "arm,armv7-timer-mem";
512 reg = <0x0 0x17420000 0x0 0x1000>;
513 ranges = <0 0 0 0x20000000>;
514 #address-cells = <1>;
515 #size-cells = <1>;
516
517 frame@17421000 {
518 reg = <0x17421000 0x1000>,
519 <0x17422000 0x1000>;
520 frame-number = <0>;
521 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
523 };
524
525 frame@17423000 {
526 reg = <0x17423000 0x1000>;
527 frame-number = <1>;
528 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
529 status = "disabled";
530 };
531
532 frame@17425000 {
533 reg = <0x17425000 0x1000>;
534 frame-number = <2>;
535 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
536 status = "disabled";
537 };
538
539 frame@17427000 {
540 reg = <0x17427000 0x1000>;
541 frame-number = <3>;
542 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
543 status = "disabled";
544 };
545
546 frame@17429000 {
547 reg = <0x17429000 0x1000>;
548 frame-number = <4>;
549 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
550 status = "disabled";
551 };
552
553 frame@1742b000 {
554 reg = <0x1742b000 0x1000>;
555 frame-number = <5>;
556 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
557 status = "disabled";
558 };
559
560 frame@1742d000 {
561 reg = <0x1742d000 0x1000>;
562 frame-number = <6>;
563 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
564 status = "disabled";
565 };
566 };
567
568 apps_rsc: rsc@17a00000 {
569 compatible = "qcom,rpmh-rsc";
570 reg = <0x0 0x17a00000 0x0 0x10000>,
571 <0x0 0x17a10000 0x0 0x10000>,
572 <0x0 0x17a20000 0x0 0x10000>;
573 reg-names = "drv-0", "drv-1", "drv-2";
574 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
577 label = "apps_rsc";
578 qcom,tcs-offset = <0xd00>;
579 qcom,drv-id = <2>;
580 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
581 <WAKE_TCS 3>, <CONTROL_TCS 0>;
582 power-domains = <&CLUSTER_PD>;
583
584 apps_bcm_voter: bcm-voter {
585 compatible = "qcom,bcm-voter";
586 };
587
588 rpmhcc: clock-controller {
589 compatible = "qcom,sm4450-rpmh-clk";
590 #clock-cells = <1>;
591 clocks = <&xo_board>;
592 clock-names = "xo";
593 };
594 };
595
596 cpufreq_hw: cpufreq@17d91000 {
597 compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
598 reg = <0 0x17d91000 0 0x1000>,
599 <0 0x17d92000 0 0x1000>;
600 reg-names = "freq-domain0", "freq-domain1";
601 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
602 clock-names = "xo", "alternate";
603 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
606 #freq-domain-cells = <1>;
607 #clock-cells = <1>;
608 };
609 };
610
611 timer {
612 compatible = "arm,armv8-timer";
613 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
614 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
615 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
616 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
617 };
618 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.