1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
4 */
5
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13
14 / {
15 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 chosen { };
20
21 clocks {
22 xo_board: xo-board {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <19200000>;
26 };
27
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32000>;
32 clock-output-names = "sleep_clk";
33 };
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 CPU0: cpu@0 {
41 device_type = "cpu";
42 compatible = "qcom,kryo260";
43 reg = <0x0 0x0>;
44 enable-method = "psci";
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
48 compatible = "cache";
49 cache-level = <2>;
50 cache-unified;
51 };
52 };
53
54 CPU1: cpu@1 {
55 device_type = "cpu";
56 compatible = "qcom,kryo260";
57 reg = <0x0 0x1>;
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
61 };
62
63 CPU2: cpu@2 {
64 device_type = "cpu";
65 compatible = "qcom,kryo260";
66 reg = <0x0 0x2>;
67 enable-method = "psci";
68 capacity-dmips-mhz = <1024>;
69 next-level-cache = <&L2_0>;
70 };
71
72 CPU3: cpu@3 {
73 device_type = "cpu";
74 compatible = "qcom,kryo260";
75 reg = <0x0 0x3>;
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_0>;
79 };
80
81 CPU4: cpu@100 {
82 device_type = "cpu";
83 compatible = "qcom,kryo260";
84 reg = <0x0 0x100>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <1638>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
89 compatible = "cache";
90 cache-level = <2>;
91 cache-unified;
92 };
93 };
94
95 CPU5: cpu@101 {
96 device_type = "cpu";
97 compatible = "qcom,kryo260";
98 reg = <0x0 0x101>;
99 enable-method = "psci";
100 capacity-dmips-mhz = <1638>;
101 next-level-cache = <&L2_1>;
102 };
103
104 CPU6: cpu@102 {
105 device_type = "cpu";
106 compatible = "qcom,kryo260";
107 reg = <0x0 0x102>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1638>;
110 next-level-cache = <&L2_1>;
111 };
112
113 CPU7: cpu@103 {
114 device_type = "cpu";
115 compatible = "qcom,kryo260";
116 reg = <0x0 0x103>;
117 enable-method = "psci";
118 capacity-dmips-mhz = <1638>;
119 next-level-cache = <&L2_1>;
120 };
121
122 cpu-map {
123 cluster0 {
124 core0 {
125 cpu = <&CPU0>;
126 };
127
128 core1 {
129 cpu = <&CPU1>;
130 };
131
132 core2 {
133 cpu = <&CPU2>;
134 };
135
136 core3 {
137 cpu = <&CPU3>;
138 };
139 };
140
141 cluster1 {
142 core0 {
143 cpu = <&CPU4>;
144 };
145
146 core1 {
147 cpu = <&CPU5>;
148 };
149
150 core2 {
151 cpu = <&CPU6>;
152 };
153
154 core3 {
155 cpu = <&CPU7>;
156 };
157 };
158 };
159 };
160
161 firmware {
162 scm: scm {
163 compatible = "qcom,scm-sm6125", "qcom,scm";
164 #reset-cells = <1>;
165 };
166 };
167
168 memory@40000000 {
169 /* We expect the bootloader to fill in the size */
170 reg = <0x0 0x40000000 0x0 0x0>;
171 device_type = "memory";
172 };
173
174 pmu {
175 compatible = "arm,armv8-pmuv3";
176 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
177 };
178
179 psci {
180 compatible = "arm,psci-1.0";
181 method = "smc";
182 };
183
184 rpm: remoteproc {
185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
186
187 glink-edge {
188 compatible = "qcom,glink-rpm";
189
190 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
191 qcom,rpm-msg-ram = <&rpm_msg_ram>;
192 mboxes = <&apcs_glb 0>;
193
194 rpm_requests: rpm-requests {
195 compatible = "qcom,rpm-sm6125";
196 qcom,glink-channels = "rpm_requests";
197
198 rpmcc: clock-controller {
199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
200 #clock-cells = <1>;
201 clocks = <&xo_board>;
202 clock-names = "xo";
203 };
204
205 rpmpd: power-controller {
206 compatible = "qcom,sm6125-rpmpd";
207 #power-domain-cells = <1>;
208 operating-points-v2 = <&rpmpd_opp_table>;
209
210 rpmpd_opp_table: opp-table {
211 compatible = "operating-points-v2";
212
213 rpmpd_opp_ret: opp1 {
214 opp-level = <RPM_SMD_LEVEL_RETENTION>;
215 };
216
217 rpmpd_opp_ret_plus: opp2 {
218 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
219 };
220
221 rpmpd_opp_min_svs: opp3 {
222 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
223 };
224
225 rpmpd_opp_low_svs: opp4 {
226 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
227 };
228
229 rpmpd_opp_svs: opp5 {
230 opp-level = <RPM_SMD_LEVEL_SVS>;
231 };
232
233 rpmpd_opp_svs_plus: opp6 {
234 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
235 };
236
237 rpmpd_opp_nom: opp7 {
238 opp-level = <RPM_SMD_LEVEL_NOM>;
239 };
240
241 rpmpd_opp_nom_plus: opp8 {
242 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
243 };
244
245 rpmpd_opp_turbo: opp9 {
246 opp-level = <RPM_SMD_LEVEL_TURBO>;
247 };
248
249 rpmpd_opp_turbo_no_cpr: opp10 {
250 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
251 };
252 };
253 };
254 };
255 };
256 };
257
258 reserved_memory: reserved-memory {
259 #address-cells = <2>;
260 #size-cells = <2>;
261 ranges;
262
263 hyp_mem: memory@45700000 {
264 reg = <0x0 0x45700000 0x0 0x600000>;
265 no-map;
266 };
267
268 xbl_aop_mem: memory@45e00000 {
269 reg = <0x0 0x45e00000 0x0 0x140000>;
270 no-map;
271 };
272
273 sec_apps_mem: memory@45fff000 {
274 reg = <0x0 0x45fff000 0x0 0x1000>;
275 no-map;
276 };
277
278 smem_mem: memory@46000000 {
279 reg = <0x0 0x46000000 0x0 0x200000>;
280 no-map;
281 };
282
283 reserved_mem1: memory@46200000 {
284 reg = <0x0 0x46200000 0x0 0x2d00000>;
285 no-map;
286 };
287
288 camera_mem: memory@4ab00000 {
289 reg = <0x0 0x4ab00000 0x0 0x500000>;
290 no-map;
291 };
292
293 modem_mem: memory@4b000000 {
294 reg = <0x0 0x4b000000 0x0 0x7e00000>;
295 no-map;
296 };
297
298 venus_mem: memory@52e00000 {
299 reg = <0x0 0x52e00000 0x0 0x500000>;
300 no-map;
301 };
302
303 wlan_msa_mem: memory@53300000 {
304 reg = <0x0 0x53300000 0x0 0x200000>;
305 no-map;
306 };
307
308 cdsp_mem: memory@53500000 {
309 reg = <0x0 0x53500000 0x0 0x1e00000>;
310 no-map;
311 };
312
313 adsp_pil_mem: memory@55300000 {
314 reg = <0x0 0x55300000 0x0 0x1e00000>;
315 no-map;
316 };
317
318 ipa_fw_mem: memory@57100000 {
319 reg = <0x0 0x57100000 0x0 0x10000>;
320 no-map;
321 };
322
323 ipa_gsi_mem: memory@57110000 {
324 reg = <0x0 0x57110000 0x0 0x5000>;
325 no-map;
326 };
327
328 gpu_mem: memory@57115000 {
329 reg = <0x0 0x57115000 0x0 0x2000>;
330 no-map;
331 };
332
333 cont_splash_mem: memory@5c000000 {
334 reg = <0x0 0x5c000000 0x0 0x00f00000>;
335 no-map;
336 };
337
338 dfps_data_mem: memory@5cf00000 {
339 reg = <0x0 0x5cf00000 0x0 0x0100000>;
340 no-map;
341 };
342
343 cdsp_sec_mem: memory@5f800000 {
344 reg = <0x0 0x5f800000 0x0 0x1e00000>;
345 no-map;
346 };
347
348 qseecom_mem: memory@5e400000 {
349 reg = <0x0 0x5e400000 0x0 0x1400000>;
350 no-map;
351 };
352
353 sdsp_mem: memory@f3000000 {
354 reg = <0x0 0xf3000000 0x0 0x400000>;
355 no-map;
356 };
357
358 adsp_mem: memory@f3400000 {
359 reg = <0x0 0xf3400000 0x0 0x800000>;
360 no-map;
361 };
362
363 qseecom_ta_mem: memory@13fc00000 {
364 reg = <0x1 0x3fc00000 0x0 0x400000>;
365 no-map;
366 };
367 };
368
369 smem: smem {
370 compatible = "qcom,smem";
371 memory-region = <&smem_mem>;
372 hwlocks = <&tcsr_mutex 3>;
373 };
374
375 soc@0 {
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges = <0x00 0x00 0x00 0xffffffff>;
379 compatible = "simple-bus";
380
381 tcsr_mutex: hwlock@340000 {
382 compatible = "qcom,tcsr-mutex";
383 reg = <0x00340000 0x20000>;
384 #hwlock-cells = <1>;
385 };
386
387 tlmm: pinctrl@500000 {
388 compatible = "qcom,sm6125-tlmm";
389 reg = <0x00500000 0x400000>,
390 <0x00900000 0x400000>,
391 <0x00d00000 0x400000>;
392 reg-names = "west", "south", "east";
393 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
394 gpio-controller;
395 gpio-ranges = <&tlmm 0 0 134>;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399
400 sdc2_off_state: sdc2-off-state {
401 clk-pins {
402 pins = "sdc2_clk";
403 drive-strength = <2>;
404 bias-disable;
405 };
406
407 cmd-pins {
408 pins = "sdc2_cmd";
409 drive-strength = <2>;
410 bias-pull-up;
411 };
412
413 data-pins {
414 pins = "sdc2_data";
415 drive-strength = <2>;
416 bias-pull-up;
417 };
418 };
419
420 sdc2_on_state: sdc2-on-state {
421 clk-pins {
422 pins = "sdc2_clk";
423 drive-strength = <16>;
424 bias-disable;
425 };
426
427 cmd-pins {
428 pins = "sdc2_cmd";
429 drive-strength = <10>;
430 bias-pull-up;
431 };
432
433 data-pins {
434 pins = "sdc2_data";
435 drive-strength = <10>;
436 bias-pull-up;
437 };
438 };
439
440 qup_i2c0_default: qup-i2c0-default-state {
441 pins = "gpio0", "gpio1";
442 function = "qup00";
443 drive-strength = <2>;
444 bias-disable;
445 };
446
447 qup_i2c0_sleep: qup-i2c0-sleep-state {
448 pins = "gpio0", "gpio1";
449 function = "gpio";
450 drive-strength = <2>;
451 bias-pull-up;
452 };
453
454 qup_i2c1_default: qup-i2c1-default-state {
455 pins = "gpio4", "gpio5";
456 function = "qup01";
457 drive-strength = <2>;
458 bias-disable;
459 };
460
461 qup_i2c1_sleep: qup-i2c1-sleep-state {
462 pins = "gpio4", "gpio5";
463 function = "gpio";
464 drive-strength = <2>;
465 bias-pull-up;
466 };
467
468 qup_i2c2_default: qup-i2c2-default-state {
469 pins = "gpio6", "gpio7";
470 function = "qup02";
471 drive-strength = <2>;
472 bias-disable;
473 };
474
475 qup_i2c2_sleep: qup-i2c2-sleep-state {
476 pins = "gpio6", "gpio7";
477 function = "gpio";
478 drive-strength = <2>;
479 bias-pull-up;
480 };
481
482 qup_i2c3_default: qup-i2c3-default-state {
483 pins = "gpio14", "gpio15";
484 function = "qup03";
485 drive-strength = <2>;
486 bias-disable;
487 };
488
489 qup_i2c3_sleep: qup-i2c3-sleep-state {
490 pins = "gpio14", "gpio15";
491 function = "gpio";
492 drive-strength = <2>;
493 bias-pull-up;
494 };
495
496 qup_i2c4_default: qup-i2c4-default-state {
497 pins = "gpio16", "gpio17";
498 function = "qup04";
499 drive-strength = <2>;
500 bias-disable;
501 };
502
503 qup_i2c4_sleep: qup-i2c4-sleep-state {
504 pins = "gpio16", "gpio17";
505 function = "gpio";
506 drive-strength = <2>;
507 bias-pull-up;
508 };
509
510 qup_i2c5_default: qup-i2c5-default-state {
511 pins = "gpio22", "gpio23";
512 function = "qup10";
513 drive-strength = <2>;
514 bias-disable;
515 };
516
517 qup_i2c5_sleep: qup-i2c5-sleep-state {
518 pins = "gpio22", "gpio23";
519 function = "gpio";
520 drive-strength = <2>;
521 bias-pull-up;
522 };
523
524 qup_i2c6_default: qup-i2c6-default-state {
525 pins = "gpio30", "gpio31";
526 function = "qup11";
527 drive-strength = <2>;
528 bias-disable;
529 };
530
531 qup_i2c6_sleep: qup-i2c6-sleep-state {
532 pins = "gpio30", "gpio31";
533 function = "gpio";
534 drive-strength = <2>;
535 bias-pull-up;
536 };
537
538 qup_i2c7_default: qup-i2c7-default-state {
539 pins = "gpio28", "gpio29";
540 function = "qup12";
541 drive-strength = <2>;
542 bias-disable;
543 };
544
545 qup_i2c7_sleep: qup-i2c7-sleep-state {
546 pins = "gpio28", "gpio29";
547 function = "gpio";
548 drive-strength = <2>;
549 bias-pull-up;
550 };
551
552 qup_i2c8_default: qup-i2c8-default-state {
553 pins = "gpio18", "gpio19";
554 function = "qup13";
555 drive-strength = <2>;
556 bias-disable;
557 };
558
559 qup_i2c8_sleep: qup-i2c8-sleep-state {
560 pins = "gpio18", "gpio19";
561 function = "gpio";
562 drive-strength = <2>;
563 bias-pull-up;
564 };
565
566 qup_i2c9_default: qup-i2c9-default-state {
567 pins = "gpio10", "gpio11";
568 function = "qup14";
569 drive-strength = <2>;
570 bias-disable;
571 };
572
573 qup_i2c9_sleep: qup-i2c9-sleep-state {
574 pins = "gpio10", "gpio11";
575 function = "gpio";
576 drive-strength = <2>;
577 bias-pull-up;
578 };
579
580 qup_spi0_default: qup-spi0-default-state {
581 pins = "gpio0", "gpio1", "gpio2", "gpio3";
582 function = "qup00";
583 drive-strength = <6>;
584 bias-disable;
585 };
586
587 qup_spi0_sleep: qup-spi0-sleep-state {
588 pins = "gpio0", "gpio1", "gpio2", "gpio3";
589 function = "gpio";
590 drive-strength = <6>;
591 bias-disable;
592 };
593
594 qup_spi2_default: qup-spi2-default-state {
595 pins = "gpio6", "gpio7", "gpio8", "gpio9";
596 function = "qup02";
597 drive-strength = <6>;
598 bias-disable;
599 };
600
601 qup_spi2_sleep: qup-spi2-sleep-state {
602 pins = "gpio6", "gpio7", "gpio8", "gpio9";
603 function = "gpio";
604 drive-strength = <6>;
605 bias-disable;
606 };
607
608 qup_spi5_default: qup-spi5-default-state {
609 pins = "gpio22", "gpio23", "gpio24", "gpio25";
610 function = "qup10";
611 drive-strength = <6>;
612 bias-disable;
613 };
614
615 qup_spi5_sleep: qup-spi5-sleep-state {
616 pins = "gpio22", "gpio23", "gpio24", "gpio25";
617 function = "gpio";
618 drive-strength = <6>;
619 bias-disable;
620 };
621
622 qup_spi6_default: qup-spi6-default-state {
623 pins = "gpio30", "gpio31", "gpio32", "gpio33";
624 function = "qup11";
625 drive-strength = <6>;
626 bias-disable;
627 };
628
629 qup_spi6_sleep: qup-spi6-sleep-state {
630 pins = "gpio30", "gpio31", "gpio32", "gpio33";
631 function = "gpio";
632 drive-strength = <6>;
633 bias-disable;
634 };
635
636 qup_spi8_default: qup-spi8-default-state {
637 pins = "gpio18", "gpio19", "gpio20", "gpio21";
638 function = "qup13";
639 drive-strength = <6>;
640 bias-disable;
641 };
642
643 qup_spi8_sleep: qup-spi8-sleep-state {
644 pins = "gpio18", "gpio19", "gpio20", "gpio21";
645 function = "gpio";
646 drive-strength = <6>;
647 bias-disable;
648 };
649
650 qup_spi9_default: qup-spi9-default-state {
651 pins = "gpio10", "gpio11", "gpio12", "gpio13";
652 function = "qup14";
653 drive-strength = <6>;
654 bias-disable;
655 };
656
657 qup_spi9_sleep: qup-spi9-sleep-state {
658 pins = "gpio10", "gpio11", "gpio12", "gpio13";
659 function = "gpio";
660 drive-strength = <6>;
661 bias-disable;
662 };
663 };
664
665 gcc: clock-controller@1400000 {
666 compatible = "qcom,gcc-sm6125";
667 reg = <0x01400000 0x1f0000>;
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 #power-domain-cells = <1>;
671 clock-names = "bi_tcxo", "sleep_clk";
672 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
673 };
674
675 hsusb_phy1: phy@1613000 {
676 compatible = "qcom,msm8996-qusb2-phy";
677 reg = <0x01613000 0x180>;
678 #phy-cells = <0>;
679
680 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
681 <&rpmcc RPM_SMD_XO_CLK_SRC>;
682 clock-names = "cfg_ahb", "ref";
683
684 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
685 status = "disabled";
686 };
687
688 spmi_bus: spmi@1c40000 {
689 compatible = "qcom,spmi-pmic-arb";
690 reg = <0x01c40000 0x1100>,
691 <0x01e00000 0x2000000>,
692 <0x03e00000 0x100000>,
693 <0x03f00000 0xa0000>,
694 <0x01c0a000 0x26000>;
695 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
696 interrupt-names = "periph_irq";
697 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
698 qcom,ee = <0>;
699 qcom,channel = <0>;
700 #address-cells = <2>;
701 #size-cells = <0>;
702 interrupt-controller;
703 #interrupt-cells = <4>;
704 };
705
706 rpm_msg_ram: sram@45f0000 {
707 compatible = "qcom,rpm-msg-ram";
708 reg = <0x045f0000 0x7000>;
709 };
710
711 sdhc_1: mmc@4744000 {
712 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
713 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
714 reg-names = "hc", "cqhci";
715
716 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
718 interrupt-names = "hc_irq", "pwr_irq";
719
720 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
721 <&gcc GCC_SDCC1_APPS_CLK>,
722 <&rpmcc RPM_SMD_XO_CLK_SRC>;
723 clock-names = "iface", "core", "xo";
724 iommus = <&apps_smmu 0x160 0x0>;
725
726 power-domains = <&rpmpd SM6125_VDDCX>;
727
728 qcom,dll-config = <0x000f642c>;
729 qcom,ddr-config = <0x80040873>;
730
731 bus-width = <8>;
732 non-removable;
733 supports-cqe;
734
735 status = "disabled";
736 };
737
738 sdhc_2: mmc@4784000 {
739 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
740 reg = <0x04784000 0x1000>;
741 reg-names = "hc";
742
743 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "hc_irq", "pwr_irq";
746
747 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
748 <&gcc GCC_SDCC2_APPS_CLK>,
749 <&rpmcc RPM_SMD_XO_CLK_SRC>;
750 clock-names = "iface", "core", "xo";
751 iommus = <&apps_smmu 0x180 0x0>;
752
753 pinctrl-0 = <&sdc2_on_state>;
754 pinctrl-1 = <&sdc2_off_state>;
755 pinctrl-names = "default", "sleep";
756
757 power-domains = <&rpmpd SM6125_VDDCX>;
758
759 qcom,dll-config = <0x0007642c>;
760 qcom,ddr-config = <0x80040873>;
761
762 bus-width = <4>;
763 status = "disabled";
764 };
765
766 ufs_mem_hc: ufs@4804000 {
767 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
768 reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
769 reg-names = "std", "ice";
770 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
771
772 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
773 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
774 <&gcc GCC_UFS_PHY_AHB_CLK>,
775 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
776 <&rpmcc RPM_SMD_XO_CLK_SRC>,
777 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
778 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
779 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
780 clock-names = "core_clk",
781 "bus_aggr_clk",
782 "iface_clk",
783 "core_clk_unipro",
784 "ref_clk",
785 "tx_lane0_sync_clk",
786 "rx_lane0_sync_clk",
787 "ice_core_clk";
788 freq-table-hz = <50000000 240000000>,
789 <0 0>,
790 <0 0>,
791 <37500000 150000000>,
792 <0 0>,
793 <0 0>,
794 <0 0>,
795 <75000000 300000000>;
796
797 resets = <&gcc GCC_UFS_PHY_BCR>;
798 reset-names = "rst";
799 #reset-cells = <1>;
800
801 phys = <&ufs_mem_phy>;
802 phy-names = "ufsphy";
803
804 lanes-per-direction = <1>;
805
806 iommus = <&apps_smmu 0x200 0x0>;
807
808 status = "disabled";
809 };
810
811 ufs_mem_phy: phy@4807000 {
812 compatible = "qcom,sm6125-qmp-ufs-phy";
813 reg = <0x04807000 0xdb8>;
814
815 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
816 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
817 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
818 clock-names = "ref",
819 "ref_aux",
820 "qref";
821
822 resets = <&ufs_mem_hc 0>;
823 reset-names = "ufsphy";
824
825 power-domains = <&gcc UFS_PHY_GDSC>;
826
827 #phy-cells = <0>;
828
829 status = "disabled";
830 };
831
832 gpi_dma0: dma-controller@4a00000 {
833 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
834 reg = <0x04a00000 0x60000>;
835 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
843 dma-channels = <8>;
844 dma-channel-mask = <0x1f>;
845 iommus = <&apps_smmu 0x136 0x0>;
846 #dma-cells = <3>;
847 status = "disabled";
848 };
849
850 qupv3_id_0: geniqup@4ac0000 {
851 compatible = "qcom,geni-se-qup";
852 reg = <0x04ac0000 0x2000>;
853 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
854 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
855 clock-names = "m-ahb", "s-ahb";
856 iommus = <&apps_smmu 0x123 0x0>;
857 #address-cells = <1>;
858 #size-cells = <1>;
859 ranges;
860 status = "disabled";
861
862 i2c0: i2c@4a80000 {
863 compatible = "qcom,geni-i2c";
864 reg = <0x04a80000 0x4000>;
865 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
866 clock-names = "se";
867 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
868 pinctrl-0 = <&qup_i2c0_default>;
869 pinctrl-1 = <&qup_i2c0_sleep>;
870 pinctrl-names = "default", "sleep";
871 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
872 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
873 dma-names = "tx", "rx";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
877 };
878
879 spi0: spi@4a80000 {
880 compatible = "qcom,geni-spi";
881 reg = <0x04a80000 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
883 clock-names = "se";
884 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
885 pinctrl-0 = <&qup_spi0_default>;
886 pinctrl-1 = <&qup_spi0_sleep>;
887 pinctrl-names = "default", "sleep";
888 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
889 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
890 dma-names = "tx", "rx";
891 #address-cells = <1>;
892 #size-cells = <0>;
893 status = "disabled";
894 };
895
896 i2c1: i2c@4a84000 {
897 compatible = "qcom,geni-i2c";
898 reg = <0x04a84000 0x4000>;
899 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
900 clock-names = "se";
901 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
902 pinctrl-0 = <&qup_i2c1_default>;
903 pinctrl-1 = <&qup_i2c1_sleep>;
904 pinctrl-names = "default", "sleep";
905 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
906 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
907 dma-names = "tx", "rx";
908 #address-cells = <1>;
909 #size-cells = <0>;
910 status = "disabled";
911 };
912
913 i2c2: i2c@4a88000 {
914 compatible = "qcom,geni-i2c";
915 reg = <0x04a88000 0x4000>;
916 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
917 clock-names = "se";
918 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
919 pinctrl-0 = <&qup_i2c2_default>;
920 pinctrl-1 = <&qup_i2c2_sleep>;
921 pinctrl-names = "default", "sleep";
922 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
923 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
924 dma-names = "tx", "rx";
925 #address-cells = <1>;
926 #size-cells = <0>;
927 status = "disabled";
928 };
929
930 spi2: spi@4a88000 {
931 compatible = "qcom,geni-spi";
932 reg = <0x04a88000 0x4000>;
933 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
934 clock-names = "se";
935 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
936 pinctrl-0 = <&qup_spi2_default>;
937 pinctrl-1 = <&qup_spi2_sleep>;
938 pinctrl-names = "default", "sleep";
939 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
940 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
941 dma-names = "tx", "rx";
942 #address-cells = <1>;
943 #size-cells = <0>;
944 status = "disabled";
945 };
946
947 i2c3: i2c@4a8c000 {
948 compatible = "qcom,geni-i2c";
949 reg = <0x04a8c000 0x4000>;
950 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
951 clock-names = "se";
952 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
953 pinctrl-0 = <&qup_i2c3_default>;
954 pinctrl-1 = <&qup_i2c3_sleep>;
955 pinctrl-names = "default", "sleep";
956 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
957 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
958 dma-names = "tx", "rx";
959 #address-cells = <1>;
960 #size-cells = <0>;
961 status = "disabled";
962 };
963
964 i2c4: i2c@4a90000 {
965 compatible = "qcom,geni-i2c";
966 reg = <0x04a90000 0x4000>;
967 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
968 clock-names = "se";
969 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
970 pinctrl-0 = <&qup_i2c4_default>;
971 pinctrl-1 = <&qup_i2c4_sleep>;
972 pinctrl-names = "default", "sleep";
973 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
974 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
975 dma-names = "tx", "rx";
976 #address-cells = <1>;
977 #size-cells = <0>;
978 status = "disabled";
979 };
980 };
981
982 gpi_dma1: dma-controller@4c00000 {
983 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
984 reg = <0x04c00000 0x60000>;
985 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
993 dma-channels = <8>;
994 dma-channel-mask = <0x0f>;
995 iommus = <&apps_smmu 0x156 0x0>;
996 #dma-cells = <3>;
997 status = "disabled";
998 };
999
1000 qupv3_id_1: geniqup@4cc0000 {
1001 compatible = "qcom,geni-se-qup";
1002 reg = <0x04cc0000 0x2000>;
1003 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1004 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1005 clock-names = "m-ahb", "s-ahb";
1006 iommus = <&apps_smmu 0x143 0x0>;
1007 #address-cells = <1>;
1008 #size-cells = <1>;
1009 ranges;
1010 status = "disabled";
1011
1012 i2c5: i2c@4c80000 {
1013 compatible = "qcom,geni-i2c";
1014 reg = <0x04c80000 0x4000>;
1015 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1016 clock-names = "se";
1017 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
1018 pinctrl-0 = <&qup_i2c5_default>;
1019 pinctrl-1 = <&qup_i2c5_sleep>;
1020 pinctrl-names = "default", "sleep";
1021 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1022 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1023 dma-names = "tx", "rx";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 status = "disabled";
1027 };
1028
1029 spi5: spi@4c80000 {
1030 compatible = "qcom,geni-spi";
1031 reg = <0x04c80000 0x4000>;
1032 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1033 clock-names = "se";
1034 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
1035 pinctrl-0 = <&qup_spi5_default>;
1036 pinctrl-1 = <&qup_spi5_sleep>;
1037 pinctrl-names = "default", "sleep";
1038 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1039 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1040 dma-names = "tx", "rx";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 status = "disabled";
1044 };
1045
1046 i2c6: i2c@4c84000 {
1047 compatible = "qcom,geni-i2c";
1048 reg = <0x04c84000 0x4000>;
1049 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1050 clock-names = "se";
1051 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1052 pinctrl-0 = <&qup_i2c6_default>;
1053 pinctrl-1 = <&qup_i2c6_sleep>;
1054 pinctrl-names = "default", "sleep";
1055 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1056 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1057 dma-names = "tx", "rx";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 status = "disabled";
1061 };
1062
1063 spi6: spi@4c84000 {
1064 compatible = "qcom,geni-spi";
1065 reg = <0x04c84000 0x4000>;
1066 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1067 clock-names = "se";
1068 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1069 pinctrl-0 = <&qup_spi6_default>;
1070 pinctrl-1 = <&qup_spi6_sleep>;
1071 pinctrl-names = "default", "sleep";
1072 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1073 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1074 dma-names = "tx", "rx";
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 status = "disabled";
1078 };
1079
1080 i2c7: i2c@4c88000 {
1081 compatible = "qcom,geni-i2c";
1082 reg = <0x04c88000 0x4000>;
1083 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1084 clock-names = "se";
1085 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
1086 pinctrl-0 = <&qup_i2c7_default>;
1087 pinctrl-1 = <&qup_i2c7_sleep>;
1088 pinctrl-names = "default", "sleep";
1089 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1090 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1091 dma-names = "tx", "rx";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 status = "disabled";
1095 };
1096
1097 i2c8: i2c@4c8c000 {
1098 compatible = "qcom,geni-i2c";
1099 reg = <0x04c8c000 0x4000>;
1100 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1101 clock-names = "se";
1102 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
1103 pinctrl-0 = <&qup_i2c8_default>;
1104 pinctrl-1 = <&qup_i2c8_sleep>;
1105 pinctrl-names = "default", "sleep";
1106 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1107 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1108 dma-names = "tx", "rx";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 status = "disabled";
1112 };
1113
1114 spi8: spi@4c8c000 {
1115 compatible = "qcom,geni-spi";
1116 reg = <0x04c8c000 0x4000>;
1117 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1118 clock-names = "se";
1119 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
1120 pinctrl-0 = <&qup_spi8_default>;
1121 pinctrl-1 = <&qup_spi8_sleep>;
1122 pinctrl-names = "default", "sleep";
1123 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1124 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1125 dma-names = "tx", "rx";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 status = "disabled";
1129 };
1130
1131 i2c9: i2c@4c90000 {
1132 compatible = "qcom,geni-i2c";
1133 reg = <0x04c90000 0x4000>;
1134 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1135 clock-names = "se";
1136 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
1137 pinctrl-0 = <&qup_i2c9_default>;
1138 pinctrl-1 = <&qup_i2c9_sleep>;
1139 pinctrl-names = "default", "sleep";
1140 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1141 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1142 dma-names = "tx", "rx";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 status = "disabled";
1146 };
1147
1148 spi9: spi@4c90000 {
1149 compatible = "qcom,geni-spi";
1150 reg = <0x04c90000 0x4000>;
1151 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1152 clock-names = "se";
1153 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
1154 pinctrl-0 = <&qup_spi9_default>;
1155 pinctrl-1 = <&qup_spi9_sleep>;
1156 pinctrl-names = "default", "sleep";
1157 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1158 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1159 dma-names = "tx", "rx";
1160 #address-cells = <1>;
1161 #size-cells = <0>;
1162 status = "disabled";
1163 };
1164 };
1165
1166 usb3: usb@4ef8800 {
1167 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
1168 reg = <0x04ef8800 0x400>;
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1171 ranges;
1172
1173 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1174 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1175 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1176 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1177 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1178 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1179 clock-names = "cfg_noc",
1180 "core",
1181 "iface",
1182 "sleep",
1183 "mock_utmi",
1184 "xo";
1185
1186 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1187 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1188 assigned-clock-rates = <19200000>, <66666667>;
1189
1190 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1194 interrupt-names = "pwr_event",
1195 "qusb2_phy",
1196 "hs_phy_irq",
1197 "ss_phy_irq";
1198
1199 power-domains = <&gcc USB30_PRIM_GDSC>;
1200 qcom,select-utmi-as-pipe-clk;
1201 status = "disabled";
1202
1203 usb3_dwc3: usb@4e00000 {
1204 compatible = "snps,dwc3";
1205 reg = <0x04e00000 0xcd00>;
1206 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1207 iommus = <&apps_smmu 0x100 0x0>;
1208 phys = <&hsusb_phy1>;
1209 phy-names = "usb2-phy";
1210 snps,dis_u2_susphy_quirk;
1211 snps,dis_enblslpm_quirk;
1212 maximum-speed = "high-speed";
1213 dr_mode = "peripheral";
1214 };
1215 };
1216
1217 sram@4690000 {
1218 compatible = "qcom,rpm-stats";
1219 reg = <0x04690000 0x10000>;
1220 };
1221
1222 mdss: display-subsystem@5e00000 {
1223 compatible = "qcom,sm6125-mdss";
1224 reg = <0x05e00000 0x1000>;
1225 reg-names = "mdss";
1226
1227 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-controller;
1229 #interrupt-cells = <1>;
1230
1231 clocks = <&gcc GCC_DISP_AHB_CLK>,
1232 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1233 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1234 clock-names = "iface",
1235 "ahb",
1236 "core";
1237
1238 power-domains = <&dispcc MDSS_GDSC>;
1239
1240 iommus = <&apps_smmu 0x400 0x0>;
1241
1242 #address-cells = <1>;
1243 #size-cells = <1>;
1244 ranges;
1245
1246 status = "disabled";
1247
1248 mdss_mdp: display-controller@5e01000 {
1249 compatible = "qcom,sm6125-dpu";
1250 reg = <0x05e01000 0x83208>,
1251 <0x05eb0000 0x2008>;
1252 reg-names = "mdp", "vbif";
1253
1254 interrupt-parent = <&mdss>;
1255 interrupts = <0>;
1256
1257 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1258 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1259 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1260 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1261 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1262 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
1263 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
1264 clock-names = "bus",
1265 "iface",
1266 "rot",
1267 "lut",
1268 "core",
1269 "vsync",
1270 "throttle";
1271 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1272 assigned-clock-rates = <19200000>;
1273
1274 operating-points-v2 = <&mdp_opp_table>;
1275 power-domains = <&rpmpd SM6125_VDDCX>;
1276
1277 ports {
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280
1281 port@0 {
1282 reg = <0>;
1283 dpu_intf1_out: endpoint {
1284 remote-endpoint = <&mdss_dsi0_in>;
1285 };
1286 };
1287 };
1288
1289 mdp_opp_table: opp-table {
1290 compatible = "operating-points-v2";
1291
1292 opp-192000000 {
1293 opp-hz = /bits/ 64 <192000000>;
1294 required-opps = <&rpmpd_opp_low_svs>;
1295 };
1296
1297 opp-256000000 {
1298 opp-hz = /bits/ 64 <256000000>;
1299 required-opps = <&rpmpd_opp_svs>;
1300 };
1301
1302 opp-307200000 {
1303 opp-hz = /bits/ 64 <307200000>;
1304 required-opps = <&rpmpd_opp_svs_plus>;
1305 };
1306
1307 opp-384000000 {
1308 opp-hz = /bits/ 64 <384000000>;
1309 required-opps = <&rpmpd_opp_nom>;
1310 };
1311
1312 opp-400000000 {
1313 opp-hz = /bits/ 64 <400000000>;
1314 required-opps = <&rpmpd_opp_turbo>;
1315 };
1316 };
1317 };
1318
1319 mdss_dsi0: dsi@5e94000 {
1320 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1321 reg = <0x05e94000 0x400>;
1322 reg-names = "dsi_ctrl";
1323
1324 interrupt-parent = <&mdss>;
1325 interrupts = <4>;
1326
1327 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1328 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1329 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1330 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1331 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1332 <&gcc GCC_DISP_HF_AXI_CLK>;
1333 clock-names = "byte",
1334 "byte_intf",
1335 "pixel",
1336 "core",
1337 "iface",
1338 "bus";
1339 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1340 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1341 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1342
1343 operating-points-v2 = <&dsi_opp_table>;
1344 power-domains = <&rpmpd SM6125_VDDCX>;
1345
1346 phys = <&mdss_dsi0_phy>;
1347 phy-names = "dsi";
1348
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1351
1352 status = "disabled";
1353
1354 ports {
1355 #address-cells = <1>;
1356 #size-cells = <0>;
1357
1358 port@0 {
1359 reg = <0>;
1360 mdss_dsi0_in: endpoint {
1361 remote-endpoint = <&dpu_intf1_out>;
1362 };
1363 };
1364
1365 port@1 {
1366 reg = <1>;
1367 mdss_dsi0_out: endpoint {
1368 };
1369 };
1370 };
1371
1372 dsi_opp_table: opp-table {
1373 compatible = "operating-points-v2";
1374
1375 opp-164000000 {
1376 opp-hz = /bits/ 64 <164000000>;
1377 required-opps = <&rpmpd_opp_low_svs>;
1378 };
1379
1380 opp-187500000 {
1381 opp-hz = /bits/ 64 <187500000>;
1382 required-opps = <&rpmpd_opp_svs>;
1383 };
1384 };
1385 };
1386
1387 mdss_dsi0_phy: phy@5e94400 {
1388 compatible = "qcom,sm6125-dsi-phy-14nm";
1389 reg = <0x05e94400 0x100>,
1390 <0x05e94500 0x300>,
1391 <0x05e94800 0x188>;
1392 reg-names = "dsi_phy",
1393 "dsi_phy_lane",
1394 "dsi_pll";
1395
1396 #clock-cells = <1>;
1397 #phy-cells = <0>;
1398
1399 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1400 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1401 clock-names = "iface",
1402 "ref";
1403
1404 required-opps = <&rpmpd_opp_nom>;
1405 power-domains = <&rpmpd SM6125_VDDMX>;
1406
1407 status = "disabled";
1408 };
1409 };
1410
1411 dispcc: clock-controller@5f00000 {
1412 compatible = "qcom,sm6125-dispcc";
1413 reg = <0x05f00000 0x20000>;
1414
1415 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1416 <&mdss_dsi0_phy 0>,
1417 <&mdss_dsi0_phy 1>,
1418 <0>,
1419 <0>,
1420 <0>,
1421 <&gcc GCC_DISP_AHB_CLK>,
1422 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1423 clock-names = "bi_tcxo",
1424 "dsi0_phy_pll_out_byteclk",
1425 "dsi0_phy_pll_out_dsiclk",
1426 "dsi1_phy_pll_out_dsiclk",
1427 "dp_phy_pll_link_clk",
1428 "dp_phy_pll_vco_div_clk",
1429 "cfg_ahb_clk",
1430 "gcc_disp_gpll0_div_clk_src";
1431
1432 required-opps = <&rpmpd_opp_ret>;
1433 power-domains = <&rpmpd SM6125_VDDCX>;
1434
1435 #clock-cells = <1>;
1436 #power-domain-cells = <1>;
1437 };
1438
1439 apps_smmu: iommu@c600000 {
1440 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1441 reg = <0x0c600000 0x80000>;
1442 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
1507
1508 #global-interrupts = <1>;
1509 #iommu-cells = <2>;
1510 };
1511
1512 apcs_glb: mailbox@f111000 {
1513 compatible = "qcom,sm6125-apcs-hmss-global",
1514 "qcom,msm8994-apcs-kpss-global";
1515 reg = <0x0f111000 0x1000>;
1516
1517 #mbox-cells = <1>;
1518 };
1519
1520 timer@f120000 {
1521 compatible = "arm,armv7-timer-mem";
1522 #address-cells = <1>;
1523 #size-cells = <1>;
1524 ranges;
1525 reg = <0x0f120000 0x1000>;
1526 clock-frequency = <19200000>;
1527
1528 frame@f121000 {
1529 frame-number = <0>;
1530 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1532 reg = <0x0f121000 0x1000>,
1533 <0x0f122000 0x1000>;
1534 };
1535
1536 frame@f123000 {
1537 frame-number = <1>;
1538 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1539 reg = <0x0f123000 0x1000>;
1540 status = "disabled";
1541 };
1542
1543 frame@f124000 {
1544 frame-number = <2>;
1545 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1546 reg = <0x0f124000 0x1000>;
1547 status = "disabled";
1548 };
1549
1550 frame@f125000 {
1551 frame-number = <3>;
1552 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1553 reg = <0x0f125000 0x1000>;
1554 status = "disabled";
1555 };
1556
1557 frame@f126000 {
1558 frame-number = <4>;
1559 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1560 reg = <0x0f126000 0x1000>;
1561 status = "disabled";
1562 };
1563
1564 frame@f127000 {
1565 frame-number = <5>;
1566 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1567 reg = <0x0f127000 0x1000>;
1568 status = "disabled";
1569 };
1570
1571 frame@f128000 {
1572 frame-number = <6>;
1573 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1574 reg = <0x0f128000 0x1000>;
1575 status = "disabled";
1576 };
1577 };
1578
1579 intc: interrupt-controller@f200000 {
1580 compatible = "arm,gic-v3";
1581 reg = <0x0f200000 0x20000>,
1582 <0x0f300000 0x100000>;
1583 #interrupt-cells = <3>;
1584 interrupt-controller;
1585 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1586 };
1587 };
1588
1589 timer {
1590 compatible = "arm,armv8-timer";
1591 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1592 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1593 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1594 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1595 clock-frequency = <19200000>;
1596 };
1597 };
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