1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
5 */
6
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm6350.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
23
24 / {
25 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 clocks {
30 xo_board: xo-board {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <76800000>;
34 clock-output-names = "xo_board";
35 };
36
37 sleep_clk: sleep-clk {
38 compatible = "fixed-clock";
39 clock-frequency = <32764>;
40 #clock-cells = <0>;
41 };
42 };
43
44 cpus {
45 #address-cells = <2>;
46 #size-cells = <0>;
47
48 CPU0: cpu@0 {
49 device_type = "cpu";
50 compatible = "qcom,kryo560";
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
53 enable-method = "psci";
54 capacity-dmips-mhz = <1024>;
55 dynamic-power-coefficient = <100>;
56 next-level-cache = <&L2_0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <&cpu0_opp_table>;
59 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
60 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
62 power-domains = <&CPU_PD0>;
63 power-domain-names = "psci";
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
71 compatible = "cache";
72 cache-level = <3>;
73 cache-unified;
74 };
75 };
76 };
77
78 CPU1: cpu@100 {
79 device_type = "cpu";
80 compatible = "qcom,kryo560";
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
83 enable-method = "psci";
84 capacity-dmips-mhz = <1024>;
85 dynamic-power-coefficient = <100>;
86 next-level-cache = <&L2_100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <&cpu0_opp_table>;
89 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
90 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
91 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
92 power-domains = <&CPU_PD1>;
93 power-domain-names = "psci";
94 #cooling-cells = <2>;
95 L2_100: l2-cache {
96 compatible = "cache";
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
100 };
101 };
102
103 CPU2: cpu@200 {
104 device_type = "cpu";
105 compatible = "qcom,kryo560";
106 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw 0>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 next-level-cache = <&L2_200>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
114 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
115 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
116 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_PD2>;
118 power-domain-names = "psci";
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
121 compatible = "cache";
122 cache-level = <2>;
123 cache-unified;
124 next-level-cache = <&L3_0>;
125 };
126 };
127
128 CPU3: cpu@300 {
129 device_type = "cpu";
130 compatible = "qcom,kryo560";
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci";
134 capacity-dmips-mhz = <1024>;
135 dynamic-power-coefficient = <100>;
136 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
140 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
142 power-domains = <&CPU_PD3>;
143 power-domain-names = "psci";
144 #cooling-cells = <2>;
145 L2_300: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
150 };
151 };
152
153 CPU4: cpu@400 {
154 device_type = "cpu";
155 compatible = "qcom,kryo560";
156 reg = <0x0 0x400>;
157 clocks = <&cpufreq_hw 0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
160 dynamic-power-coefficient = <100>;
161 next-level-cache = <&L2_400>;
162 qcom,freq-domain = <&cpufreq_hw 0>;
163 operating-points-v2 = <&cpu0_opp_table>;
164 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
165 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
167 power-domains = <&CPU_PD4>;
168 power-domain-names = "psci";
169 #cooling-cells = <2>;
170 L2_400: l2-cache {
171 compatible = "cache";
172 cache-level = <2>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
175 };
176 };
177
178 CPU5: cpu@500 {
179 device_type = "cpu";
180 compatible = "qcom,kryo560";
181 reg = <0x0 0x500>;
182 clocks = <&cpufreq_hw 0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <1024>;
185 dynamic-power-coefficient = <100>;
186 next-level-cache = <&L2_500>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
188 operating-points-v2 = <&cpu0_opp_table>;
189 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
190 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
192 power-domains = <&CPU_PD5>;
193 power-domain-names = "psci";
194 #cooling-cells = <2>;
195 L2_500: l2-cache {
196 compatible = "cache";
197 cache-level = <2>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
200 };
201 };
202
203 CPU6: cpu@600 {
204 device_type = "cpu";
205 compatible = "qcom,kryo560";
206 reg = <0x0 0x600>;
207 clocks = <&cpufreq_hw 1>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1894>;
210 dynamic-power-coefficient = <703>;
211 next-level-cache = <&L2_600>;
212 qcom,freq-domain = <&cpufreq_hw 1>;
213 operating-points-v2 = <&cpu6_opp_table>;
214 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
215 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
216 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
217 power-domains = <&CPU_PD6>;
218 power-domain-names = "psci";
219 #cooling-cells = <2>;
220 L2_600: l2-cache {
221 compatible = "cache";
222 cache-level = <2>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
225 };
226 };
227
228 CPU7: cpu@700 {
229 device_type = "cpu";
230 compatible = "qcom,kryo560";
231 reg = <0x0 0x700>;
232 clocks = <&cpufreq_hw 1>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1894>;
235 dynamic-power-coefficient = <703>;
236 next-level-cache = <&L2_700>;
237 qcom,freq-domain = <&cpufreq_hw 1>;
238 operating-points-v2 = <&cpu6_opp_table>;
239 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
240 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
241 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
242 power-domains = <&CPU_PD7>;
243 power-domain-names = "psci";
244 #cooling-cells = <2>;
245 L2_700: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
250 };
251 };
252
253 cpu-map {
254 cluster0 {
255 core0 {
256 cpu = <&CPU0>;
257 };
258
259 core1 {
260 cpu = <&CPU1>;
261 };
262
263 core2 {
264 cpu = <&CPU2>;
265 };
266
267 core3 {
268 cpu = <&CPU3>;
269 };
270
271 core4 {
272 cpu = <&CPU4>;
273 };
274
275 core5 {
276 cpu = <&CPU5>;
277 };
278
279 core6 {
280 cpu = <&CPU6>;
281 };
282
283 core7 {
284 cpu = <&CPU7>;
285 };
286 };
287 };
288
289 domain-idle-states {
290 CLUSTER_SLEEP_PC: cluster-sleep-0 {
291 compatible = "domain-idle-state";
292 arm,psci-suspend-param = <0x41000044>;
293 entry-latency-us = <2752>;
294 exit-latency-us = <3048>;
295 min-residency-us = <6118>;
296 };
297
298 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
299 compatible = "domain-idle-state";
300 arm,psci-suspend-param = <0x41001244>;
301 entry-latency-us = <3638>;
302 exit-latency-us = <4562>;
303 min-residency-us = <8467>;
304 };
305
306 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
307 compatible = "domain-idle-state";
308 arm,psci-suspend-param = <0x4100b244>;
309 entry-latency-us = <3263>;
310 exit-latency-us = <6562>;
311 min-residency-us = <9987>;
312 };
313 };
314
315 cpu_idle_states: idle-states {
316 entry-method = "psci";
317
318 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
319 compatible = "arm,idle-state";
320 idle-state-name = "little-power-collapse";
321 arm,psci-suspend-param = <0x40000003>;
322 entry-latency-us = <549>;
323 exit-latency-us = <901>;
324 min-residency-us = <1774>;
325 local-timer-stop;
326 };
327
328 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <702>;
333 exit-latency-us = <915>;
334 min-residency-us = <4001>;
335 local-timer-stop;
336 };
337
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-power-collapse";
341 arm,psci-suspend-param = <0x40000003>;
342 entry-latency-us = <523>;
343 exit-latency-us = <1244>;
344 min-residency-us = <2207>;
345 local-timer-stop;
346 };
347
348 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
349 compatible = "arm,idle-state";
350 idle-state-name = "big-rail-power-collapse";
351 arm,psci-suspend-param = <0x40000004>;
352 entry-latency-us = <526>;
353 exit-latency-us = <1854>;
354 min-residency-us = <5555>;
355 local-timer-stop;
356 };
357 };
358 };
359
360 firmware {
361 scm: scm {
362 compatible = "qcom,scm-sm6350", "qcom,scm";
363 #reset-cells = <1>;
364 };
365 };
366
367 memory@80000000 {
368 device_type = "memory";
369 /* We expect the bootloader to fill in the size */
370 reg = <0x0 0x80000000 0x0 0x0>;
371 };
372
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
375 opp-shared;
376
377 opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
380 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
381 };
382
383 opp-576000000 {
384 opp-hz = /bits/ 64 <576000000>;
385 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
386 };
387
388 opp-768000000 {
389 opp-hz = /bits/ 64 <768000000>;
390 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
391 };
392
393 opp-1017600000 {
394 opp-hz = /bits/ 64 <1017600000>;
395 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
396 };
397
398 opp-1248000000 {
399 opp-hz = /bits/ 64 <1248000000>;
400 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
401 };
402
403 opp-1324800000 {
404 opp-hz = /bits/ 64 <1324800000>;
405 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
406 };
407
408 opp-1516800000 {
409 opp-hz = /bits/ 64 <1516800000>;
410 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
411 };
412
413 opp-1612800000 {
414 opp-hz = /bits/ 64 <1612800000>;
415 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
416 };
417
418 opp-1708800000 {
419 opp-hz = /bits/ 64 <1708800000>;
420 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
421 };
422 };
423
424 cpu6_opp_table: opp-table-cpu6 {
425 compatible = "operating-points-v2";
426 opp-shared;
427
428 opp-300000000 {
429 opp-hz = /bits/ 64 <300000000>;
430 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
431 };
432
433 opp-787200000 {
434 opp-hz = /bits/ 64 <787200000>;
435 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
436 };
437
438 opp-979200000 {
439 opp-hz = /bits/ 64 <979200000>;
440 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
441 };
442
443 opp-1036800000 {
444 opp-hz = /bits/ 64 <1036800000>;
445 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
446 };
447
448 opp-1248000000 {
449 opp-hz = /bits/ 64 <1248000000>;
450 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
451 };
452
453 opp-1401600000 {
454 opp-hz = /bits/ 64 <1401600000>;
455 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
456 };
457
458 opp-1555200000 {
459 opp-hz = /bits/ 64 <1555200000>;
460 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
461 };
462
463 opp-1766400000 {
464 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
466 };
467
468 opp-1900800000 {
469 opp-hz = /bits/ 64 <1900800000>;
470 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
471 };
472
473 opp-2073600000 {
474 opp-hz = /bits/ 64 <2073600000>;
475 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
476 };
477 };
478
479 qup_opp_table: opp-table-qup {
480 compatible = "operating-points-v2";
481
482 opp-75000000 {
483 opp-hz = /bits/ 64 <75000000>;
484 required-opps = <&rpmhpd_opp_low_svs>;
485 };
486
487 opp-100000000 {
488 opp-hz = /bits/ 64 <100000000>;
489 required-opps = <&rpmhpd_opp_svs>;
490 };
491
492 opp-128000000 {
493 opp-hz = /bits/ 64 <128000000>;
494 required-opps = <&rpmhpd_opp_nom>;
495 };
496 };
497
498 pmu {
499 compatible = "arm,armv8-pmuv3";
500 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
501 };
502
503 psci {
504 compatible = "arm,psci-1.0";
505 method = "smc";
506
507 CPU_PD0: power-domain-cpu0 {
508 #power-domain-cells = <0>;
509 power-domains = <&CLUSTER_PD>;
510 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
511 };
512
513 CPU_PD1: power-domain-cpu1 {
514 #power-domain-cells = <0>;
515 power-domains = <&CLUSTER_PD>;
516 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
517 };
518
519 CPU_PD2: power-domain-cpu2 {
520 #power-domain-cells = <0>;
521 power-domains = <&CLUSTER_PD>;
522 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
523 };
524
525 CPU_PD3: power-domain-cpu3 {
526 #power-domain-cells = <0>;
527 power-domains = <&CLUSTER_PD>;
528 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
529 };
530
531 CPU_PD4: power-domain-cpu4 {
532 #power-domain-cells = <0>;
533 power-domains = <&CLUSTER_PD>;
534 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
535 };
536
537 CPU_PD5: power-domain-cpu5 {
538 #power-domain-cells = <0>;
539 power-domains = <&CLUSTER_PD>;
540 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
541 };
542
543 CPU_PD6: power-domain-cpu6 {
544 #power-domain-cells = <0>;
545 power-domains = <&CLUSTER_PD>;
546 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
547 };
548
549 CPU_PD7: power-domain-cpu7 {
550 #power-domain-cells = <0>;
551 power-domains = <&CLUSTER_PD>;
552 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
553 };
554
555 CLUSTER_PD: power-domain-cpu-cluster0 {
556 #power-domain-cells = <0>;
557 domain-idle-states = <&CLUSTER_SLEEP_PC
558 &CLUSTER_SLEEP_CX_RET
559 &CLUSTER_AOSS_SLEEP>;
560 };
561 };
562
563 reserved_memory: reserved-memory {
564 #address-cells = <2>;
565 #size-cells = <2>;
566 ranges;
567
568 hyp_mem: memory@80000000 {
569 reg = <0 0x80000000 0 0x600000>;
570 no-map;
571 };
572
573 xbl_aop_mem: memory@80700000 {
574 reg = <0 0x80700000 0 0x160000>;
575 no-map;
576 };
577
578 cmd_db: memory@80860000 {
579 compatible = "qcom,cmd-db";
580 reg = <0 0x80860000 0 0x20000>;
581 no-map;
582 };
583
584 sec_apps_mem: memory@808ff000 {
585 reg = <0 0x808ff000 0 0x1000>;
586 no-map;
587 };
588
589 smem_mem: memory@80900000 {
590 reg = <0 0x80900000 0 0x200000>;
591 no-map;
592 };
593
594 cdsp_sec_mem: memory@80b00000 {
595 reg = <0 0x80b00000 0 0x1e00000>;
596 no-map;
597 };
598
599 pil_camera_mem: memory@86000000 {
600 reg = <0 0x86000000 0 0x500000>;
601 no-map;
602 };
603
604 pil_npu_mem: memory@86500000 {
605 reg = <0 0x86500000 0 0x500000>;
606 no-map;
607 };
608
609 pil_video_mem: memory@86a00000 {
610 reg = <0 0x86a00000 0 0x500000>;
611 no-map;
612 };
613
614 pil_cdsp_mem: memory@86f00000 {
615 reg = <0 0x86f00000 0 0x1e00000>;
616 no-map;
617 };
618
619 pil_adsp_mem: memory@88d00000 {
620 reg = <0 0x88d00000 0 0x2800000>;
621 no-map;
622 };
623
624 wlan_fw_mem: memory@8b500000 {
625 reg = <0 0x8b500000 0 0x200000>;
626 no-map;
627 };
628
629 pil_ipa_fw_mem: memory@8b700000 {
630 reg = <0 0x8b700000 0 0x10000>;
631 no-map;
632 };
633
634 pil_ipa_gsi_mem: memory@8b710000 {
635 reg = <0 0x8b710000 0 0x5400>;
636 no-map;
637 };
638
639 pil_modem_mem: memory@8b800000 {
640 reg = <0 0x8b800000 0 0xf800000>;
641 no-map;
642 };
643
644 cont_splash_memory: memory@a0000000 {
645 reg = <0 0xa0000000 0 0x2300000>;
646 no-map;
647 };
648
649 dfps_data_memory: memory@a2300000 {
650 reg = <0 0xa2300000 0 0x100000>;
651 no-map;
652 };
653
654 removed_region: memory@c0000000 {
655 reg = <0 0xc0000000 0 0x3900000>;
656 no-map;
657 };
658
659 pil_gpu_mem: memory@f0d00000 {
660 reg = <0 0xf0d00000 0 0x1000>;
661 no-map;
662 };
663
664 debug_region: memory@ffb00000 {
665 reg = <0 0xffb00000 0 0xc0000>;
666 no-map;
667 };
668
669 last_log_region: memory@ffbc0000 {
670 reg = <0 0xffbc0000 0 0x40000>;
671 no-map;
672 };
673
674 ramoops: ramoops@ffc00000 {
675 compatible = "ramoops";
676 reg = <0 0xffc00000 0 0x100000>;
677 record-size = <0x1000>;
678 console-size = <0x40000>;
679 pmsg-size = <0x20000>;
680 ecc-size = <16>;
681 no-map;
682 };
683
684 cmdline_region: memory@ffd00000 {
685 reg = <0 0xffd00000 0 0x1000>;
686 no-map;
687 };
688 };
689
690 smem {
691 compatible = "qcom,smem";
692 memory-region = <&smem_mem>;
693 hwlocks = <&tcsr_mutex 3>;
694 };
695
696 smp2p-adsp {
697 compatible = "qcom,smp2p";
698 qcom,smem = <443>, <429>;
699 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
700 IPCC_MPROC_SIGNAL_SMP2P
701 IRQ_TYPE_EDGE_RISING>;
702 mboxes = <&ipcc IPCC_CLIENT_LPASS
703 IPCC_MPROC_SIGNAL_SMP2P>;
704
705 qcom,local-pid = <0>;
706 qcom,remote-pid = <2>;
707
708 smp2p_adsp_out: master-kernel {
709 qcom,entry-name = "master-kernel";
710 #qcom,smem-state-cells = <1>;
711 };
712
713 smp2p_adsp_in: slave-kernel {
714 qcom,entry-name = "slave-kernel";
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 };
718 };
719
720 smp2p-cdsp {
721 compatible = "qcom,smp2p";
722 qcom,smem = <94>, <432>;
723 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
724 IPCC_MPROC_SIGNAL_SMP2P
725 IRQ_TYPE_EDGE_RISING>;
726 mboxes = <&ipcc IPCC_CLIENT_CDSP
727 IPCC_MPROC_SIGNAL_SMP2P>;
728
729 qcom,local-pid = <0>;
730 qcom,remote-pid = <5>;
731
732 smp2p_cdsp_out: master-kernel {
733 qcom,entry-name = "master-kernel";
734 #qcom,smem-state-cells = <1>;
735 };
736
737 smp2p_cdsp_in: slave-kernel {
738 qcom,entry-name = "slave-kernel";
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 };
742 };
743
744 smp2p-mpss {
745 compatible = "qcom,smp2p";
746 qcom,smem = <435>, <428>;
747
748 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
749 IPCC_MPROC_SIGNAL_SMP2P
750 IRQ_TYPE_EDGE_RISING>;
751 mboxes = <&ipcc IPCC_CLIENT_MPSS
752 IPCC_MPROC_SIGNAL_SMP2P>;
753
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
756
757 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells = <1>;
760 };
761
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "slave-kernel";
764 interrupt-controller;
765 #interrupt-cells = <2>;
766 };
767
768 ipa_smp2p_out: ipa-ap-to-modem {
769 qcom,entry-name = "ipa";
770 #qcom,smem-state-cells = <1>;
771 };
772
773 ipa_smp2p_in: ipa-modem-to-ap {
774 qcom,entry-name = "ipa";
775 interrupt-controller;
776 #interrupt-cells = <2>;
777 };
778 };
779
780 soc: soc@0 {
781 #address-cells = <2>;
782 #size-cells = <2>;
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
786
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc-sm6350";
789 reg = <0 0x00100000 0 0x1f0000>;
790 #clock-cells = <1>;
791 #reset-cells = <1>;
792 #power-domain-cells = <1>;
793 clock-names = "bi_tcxo",
794 "bi_tcxo_ao",
795 "sleep_clk";
796 clocks = <&rpmhcc RPMH_CXO_CLK>,
797 <&rpmhcc RPMH_CXO_CLK_A>,
798 <&sleep_clk>;
799 };
800
801 ipcc: mailbox@408000 {
802 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
803 reg = <0 0x00408000 0 0x1000>;
804 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
805 interrupt-controller;
806 #interrupt-cells = <3>;
807 #mbox-cells = <2>;
808 };
809
810 qfprom: qfprom@784000 {
811 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
812 reg = <0 0x00784000 0 0x3000>;
813 #address-cells = <1>;
814 #size-cells = <1>;
815
816 gpu_speed_bin: gpu-speed-bin@2015 {
817 reg = <0x2015 0x1>;
818 bits = <0 8>;
819 };
820 };
821
822 rng: rng@793000 {
823 compatible = "qcom,prng-ee";
824 reg = <0 0x00793000 0 0x1000>;
825 clocks = <&gcc GCC_PRNG_AHB_CLK>;
826 clock-names = "core";
827 };
828
829 sdhc_1: mmc@7c4000 {
830 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
831 reg = <0 0x007c4000 0 0x1000>,
832 <0 0x007c5000 0 0x1000>,
833 <0 0x007c8000 0 0x8000>;
834 reg-names = "hc", "cqhci", "ice";
835
836 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-names = "hc_irq", "pwr_irq";
839 iommus = <&apps_smmu 0x60 0x0>;
840
841 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
842 <&gcc GCC_SDCC1_APPS_CLK>,
843 <&rpmhcc RPMH_CXO_CLK>;
844 clock-names = "iface", "core", "xo";
845 resets = <&gcc GCC_SDCC1_BCR>;
846 qcom,dll-config = <0x000f642c>;
847 qcom,ddr-config = <0x80040868>;
848 power-domains = <&rpmhpd SM6350_CX>;
849 operating-points-v2 = <&sdhc1_opp_table>;
850 bus-width = <8>;
851 non-removable;
852 supports-cqe;
853
854 status = "disabled";
855
856 sdhc1_opp_table: opp-table {
857 compatible = "operating-points-v2";
858
859 opp-19200000 {
860 opp-hz = /bits/ 64 <19200000>;
861 required-opps = <&rpmhpd_opp_min_svs>;
862 };
863
864 opp-100000000 {
865 opp-hz = /bits/ 64 <100000000>;
866 required-opps = <&rpmhpd_opp_low_svs>;
867 };
868
869 opp-384000000 {
870 opp-hz = /bits/ 64 <384000000>;
871 required-opps = <&rpmhpd_opp_svs_l1>;
872 };
873 };
874 };
875
876 gpi_dma0: dma-controller@800000 {
877 compatible = "qcom,sm6350-gpi-dma";
878 reg = <0 0x00800000 0 0x60000>;
879 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
889 dma-channels = <10>;
890 dma-channel-mask = <0x1f>;
891 iommus = <&apps_smmu 0x56 0x0>;
892 #dma-cells = <3>;
893 status = "disabled";
894 };
895
896 qupv3_id_0: geniqup@8c0000 {
897 compatible = "qcom,geni-se-qup";
898 reg = <0x0 0x008c0000 0x0 0x2000>;
899 clock-names = "m-ahb", "s-ahb";
900 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
901 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
902 #address-cells = <2>;
903 #size-cells = <2>;
904 iommus = <&apps_smmu 0x43 0x0>;
905 ranges;
906 status = "disabled";
907
908 i2c0: i2c@880000 {
909 compatible = "qcom,geni-i2c";
910 reg = <0 0x00880000 0 0x4000>;
911 clock-names = "se";
912 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
913 pinctrl-names = "default";
914 pinctrl-0 = <&qup_i2c0_default>;
915 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
916 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
917 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
918 dma-names = "tx", "rx";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
922 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
923 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
924 interconnect-names = "qup-core", "qup-config", "qup-memory";
925 status = "disabled";
926 };
927
928 uart1: serial@884000 {
929 compatible = "qcom,geni-uart";
930 reg = <0 0x00884000 0 0x4000>;
931 clock-names = "se";
932 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
935 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
936 power-domains = <&rpmhpd SM6350_CX>;
937 operating-points-v2 = <&qup_opp_table>;
938 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
939 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
940 interconnect-names = "qup-core", "qup-config";
941 status = "disabled";
942 };
943
944 i2c2: i2c@888000 {
945 compatible = "qcom,geni-i2c";
946 reg = <0 0x00888000 0 0x4000>;
947 clock-names = "se";
948 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&qup_i2c2_default>;
951 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
952 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
953 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
954 dma-names = "tx", "rx";
955 #address-cells = <1>;
956 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
959 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
961 status = "disabled";
962 };
963 };
964
965 gpi_dma1: dma-controller@900000 {
966 compatible = "qcom,sm6350-gpi-dma";
967 reg = <0 0x00900000 0 0x60000>;
968 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
978 dma-channels = <10>;
979 dma-channel-mask = <0x3f>;
980 iommus = <&apps_smmu 0x4d6 0x0>;
981 #dma-cells = <3>;
982 status = "disabled";
983 };
984
985 qupv3_id_1: geniqup@9c0000 {
986 compatible = "qcom,geni-se-qup";
987 reg = <0x0 0x009c0000 0x0 0x2000>;
988 clock-names = "m-ahb", "s-ahb";
989 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
990 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
991 #address-cells = <2>;
992 #size-cells = <2>;
993 iommus = <&apps_smmu 0x4c3 0x0>;
994 ranges;
995 status = "disabled";
996
997 i2c6: i2c@980000 {
998 compatible = "qcom,geni-i2c";
999 reg = <0 0x00980000 0 0x4000>;
1000 clock-names = "se";
1001 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_i2c6_default>;
1004 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1005 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1006 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1007 dma-names = "tx", "rx";
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1012 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1014 status = "disabled";
1015 };
1016
1017 i2c7: i2c@984000 {
1018 compatible = "qcom,geni-i2c";
1019 reg = <0 0x00984000 0 0x4000>;
1020 clock-names = "se";
1021 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_i2c7_default>;
1024 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1025 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1026 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1027 dma-names = "tx", "rx";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1031 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1032 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1033 interconnect-names = "qup-core", "qup-config", "qup-memory";
1034 status = "disabled";
1035 };
1036
1037 i2c8: i2c@988000 {
1038 compatible = "qcom,geni-i2c";
1039 reg = <0 0x00988000 0 0x4000>;
1040 clock-names = "se";
1041 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&qup_i2c8_default>;
1044 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1045 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1046 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1047 dma-names = "tx", "rx";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1052 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1054 status = "disabled";
1055 };
1056
1057 uart9: serial@98c000 {
1058 compatible = "qcom,geni-debug-uart";
1059 reg = <0 0x0098c000 0 0x4000>;
1060 clock-names = "se";
1061 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_uart9_default>;
1064 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1065 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1067 interconnect-names = "qup-core", "qup-config";
1068 status = "disabled";
1069 };
1070
1071 i2c10: i2c@990000 {
1072 compatible = "qcom,geni-i2c";
1073 reg = <0 0x00990000 0 0x4000>;
1074 clock-names = "se";
1075 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c10_default>;
1078 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1079 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1080 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1081 dma-names = "tx", "rx";
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1084 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1086 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1087 interconnect-names = "qup-core", "qup-config", "qup-memory";
1088 status = "disabled";
1089 };
1090 };
1091
1092 config_noc: interconnect@1500000 {
1093 compatible = "qcom,sm6350-config-noc";
1094 reg = <0 0x01500000 0 0x28000>;
1095 #interconnect-cells = <2>;
1096 qcom,bcm-voters = <&apps_bcm_voter>;
1097 };
1098
1099 system_noc: interconnect@1620000 {
1100 compatible = "qcom,sm6350-system-noc";
1101 reg = <0 0x01620000 0 0x17080>;
1102 #interconnect-cells = <2>;
1103 qcom,bcm-voters = <&apps_bcm_voter>;
1104
1105 clk_virt: interconnect-clk-virt {
1106 compatible = "qcom,sm6350-clk-virt";
1107 #interconnect-cells = <2>;
1108 qcom,bcm-voters = <&apps_bcm_voter>;
1109 };
1110 };
1111
1112 aggre1_noc: interconnect@16e0000 {
1113 compatible = "qcom,sm6350-aggre1-noc";
1114 reg = <0 0x016e0000 0 0x15080>;
1115 #interconnect-cells = <2>;
1116 qcom,bcm-voters = <&apps_bcm_voter>;
1117 };
1118
1119 aggre2_noc: interconnect@1700000 {
1120 compatible = "qcom,sm6350-aggre2-noc";
1121 reg = <0 0x01700000 0 0x1f880>;
1122 #interconnect-cells = <2>;
1123 qcom,bcm-voters = <&apps_bcm_voter>;
1124
1125 compute_noc: interconnect-compute-noc {
1126 compatible = "qcom,sm6350-compute-noc";
1127 #interconnect-cells = <2>;
1128 qcom,bcm-voters = <&apps_bcm_voter>;
1129 };
1130 };
1131
1132 mmss_noc: interconnect@1740000 {
1133 compatible = "qcom,sm6350-mmss-noc";
1134 reg = <0 0x01740000 0 0x1c100>;
1135 #interconnect-cells = <2>;
1136 qcom,bcm-voters = <&apps_bcm_voter>;
1137 };
1138
1139 ufs_mem_hc: ufs@1d84000 {
1140 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1141 "jedec,ufs-2.0";
1142 reg = <0 0x01d84000 0 0x3000>,
1143 <0 0x01d90000 0 0x8000>;
1144 reg-names = "std", "ice";
1145 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1146 phys = <&ufs_mem_phy>;
1147 phy-names = "ufsphy";
1148 lanes-per-direction = <2>;
1149 #reset-cells = <1>;
1150 resets = <&gcc GCC_UFS_PHY_BCR>;
1151 reset-names = "rst";
1152
1153 power-domains = <&gcc UFS_PHY_GDSC>;
1154
1155 iommus = <&apps_smmu 0x80 0x0>;
1156
1157 clock-names = "core_clk",
1158 "bus_aggr_clk",
1159 "iface_clk",
1160 "core_clk_unipro",
1161 "ref_clk",
1162 "tx_lane0_sync_clk",
1163 "rx_lane0_sync_clk",
1164 "rx_lane1_sync_clk",
1165 "ice_core_clk";
1166 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1167 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1168 <&gcc GCC_UFS_PHY_AHB_CLK>,
1169 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1170 <&rpmhcc RPMH_QLINK_CLK>,
1171 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1172 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1173 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
1174 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1175 freq-table-hz =
1176 <50000000 200000000>,
1177 <0 0>,
1178 <0 0>,
1179 <37500000 150000000>,
1180 <75000000 300000000>,
1181 <0 0>,
1182 <0 0>,
1183 <0 0>,
1184 <0 0>;
1185
1186 status = "disabled";
1187 };
1188
1189 ufs_mem_phy: phy@1d87000 {
1190 compatible = "qcom,sm6350-qmp-ufs-phy";
1191 reg = <0 0x01d87000 0 0x1000>;
1192
1193 clocks = <&rpmhcc RPMH_CXO_CLK>,
1194 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1195 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
1196 clock-names = "ref",
1197 "ref_aux",
1198 "qref";
1199
1200 power-domains = <&gcc UFS_PHY_GDSC>;
1201
1202 resets = <&ufs_mem_hc 0>;
1203 reset-names = "ufsphy";
1204
1205 #phy-cells = <0>;
1206
1207 status = "disabled";
1208 };
1209
1210 cryptobam: dma-controller@1dc4000 {
1211 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1212 reg = <0 0x01dc4000 0 0x24000>;
1213 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1214 #dma-cells = <1>;
1215 qcom,ee = <0>;
1216 qcom,controlled-remotely;
1217 num-channels = <16>;
1218 qcom,num-ees = <4>;
1219 iommus = <&apps_smmu 0x426 0x11>,
1220 <&apps_smmu 0x432 0x0>,
1221 <&apps_smmu 0x436 0x11>,
1222 <&apps_smmu 0x438 0x1>,
1223 <&apps_smmu 0x43f 0x0>;
1224 };
1225
1226 crypto: crypto@1dfa000 {
1227 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce";
1228 reg = <0 0x01dfa000 0 0x6000>;
1229 dmas = <&cryptobam 4>, <&cryptobam 5>;
1230 dma-names = "rx", "tx";
1231 iommus = <&apps_smmu 0x426 0x11>,
1232 <&apps_smmu 0x432 0x0>,
1233 <&apps_smmu 0x436 0x11>,
1234 <&apps_smmu 0x438 0x1>,
1235 <&apps_smmu 0x43f 0x0>;
1236 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS
1237 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
1238 interconnect-names = "memory";
1239 };
1240
1241 ipa: ipa@1e40000 {
1242 compatible = "qcom,sm6350-ipa";
1243
1244 iommus = <&apps_smmu 0x440 0x0>,
1245 <&apps_smmu 0x442 0x0>;
1246 reg = <0 0x01e40000 0 0x8000>,
1247 <0 0x01e50000 0 0x3000>,
1248 <0 0x01e04000 0 0x23000>;
1249 reg-names = "ipa-reg",
1250 "ipa-shared",
1251 "gsi";
1252
1253 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1254 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1255 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1256 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1257 interrupt-names = "ipa",
1258 "gsi",
1259 "ipa-clock-query",
1260 "ipa-setup-ready";
1261
1262 clocks = <&rpmhcc RPMH_IPA_CLK>;
1263 clock-names = "core";
1264
1265 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
1266 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
1267 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
1268 interconnect-names = "memory", "imem", "config";
1269
1270 qcom,smem-states = <&ipa_smp2p_out 0>,
1271 <&ipa_smp2p_out 1>;
1272 qcom,smem-state-names = "ipa-clock-enabled-valid",
1273 "ipa-clock-enabled";
1274
1275 status = "disabled";
1276 };
1277
1278 tcsr_mutex: hwlock@1f40000 {
1279 compatible = "qcom,tcsr-mutex";
1280 reg = <0x0 0x01f40000 0x0 0x40000>;
1281 #hwlock-cells = <1>;
1282 };
1283
1284 adsp: remoteproc@3000000 {
1285 compatible = "qcom,sm6350-adsp-pas";
1286 reg = <0 0x03000000 0 0x100>;
1287
1288 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1289 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1290 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1291 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1292 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1293 interrupt-names = "wdog", "fatal", "ready",
1294 "handover", "stop-ack";
1295
1296 clocks = <&rpmhcc RPMH_CXO_CLK>;
1297 clock-names = "xo";
1298
1299 power-domains = <&rpmhpd SM6350_LCX>,
1300 <&rpmhpd SM6350_LMX>;
1301 power-domain-names = "lcx", "lmx";
1302
1303 memory-region = <&pil_adsp_mem>;
1304
1305 qcom,qmp = <&aoss_qmp>;
1306
1307 qcom,smem-states = <&smp2p_adsp_out 0>;
1308 qcom,smem-state-names = "stop";
1309
1310 status = "disabled";
1311
1312 glink-edge {
1313 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1314 IPCC_MPROC_SIGNAL_GLINK_QMP
1315 IRQ_TYPE_EDGE_RISING>;
1316 mboxes = <&ipcc IPCC_CLIENT_LPASS
1317 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1318
1319 label = "lpass";
1320 qcom,remote-pid = <2>;
1321
1322 fastrpc {
1323 compatible = "qcom,fastrpc";
1324 qcom,glink-channels = "fastrpcglink-apps-dsp";
1325 label = "adsp";
1326 qcom,non-secure-domain;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329
1330 compute-cb@3 {
1331 compatible = "qcom,fastrpc-compute-cb";
1332 reg = <3>;
1333 iommus = <&apps_smmu 0x1003 0x0>;
1334 };
1335
1336 compute-cb@4 {
1337 compatible = "qcom,fastrpc-compute-cb";
1338 reg = <4>;
1339 iommus = <&apps_smmu 0x1004 0x0>;
1340 };
1341
1342 compute-cb@5 {
1343 compatible = "qcom,fastrpc-compute-cb";
1344 reg = <5>;
1345 iommus = <&apps_smmu 0x1005 0x0>;
1346 qcom,nsessions = <5>;
1347 };
1348 };
1349 };
1350 };
1351
1352 gpu: gpu@3d00000 {
1353 compatible = "qcom,adreno-619.0", "qcom,adreno";
1354 reg = <0 0x03d00000 0 0x40000>,
1355 <0 0x03d9e000 0 0x1000>;
1356 reg-names = "kgsl_3d0_reg_memory",
1357 "cx_mem";
1358 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1359
1360 iommus = <&adreno_smmu 0>;
1361 operating-points-v2 = <&gpu_opp_table>;
1362 qcom,gmu = <&gmu>;
1363 nvmem-cells = <&gpu_speed_bin>;
1364 nvmem-cell-names = "speed_bin";
1365 #cooling-cells = <2>;
1366
1367 status = "disabled";
1368
1369 gpu_zap_shader: zap-shader {
1370 memory-region = <&pil_gpu_mem>;
1371 };
1372
1373 gpu_opp_table: opp-table {
1374 compatible = "operating-points-v2";
1375
1376 opp-850000000 {
1377 opp-hz = /bits/ 64 <850000000>;
1378 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1379 opp-supported-hw = <0x02>;
1380 };
1381
1382 opp-800000000 {
1383 opp-hz = /bits/ 64 <800000000>;
1384 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1385 opp-supported-hw = <0x04>;
1386 };
1387
1388 opp-650000000 {
1389 opp-hz = /bits/ 64 <650000000>;
1390 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1391 opp-supported-hw = <0x08>;
1392 };
1393
1394 opp-565000000 {
1395 opp-hz = /bits/ 64 <565000000>;
1396 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1397 opp-supported-hw = <0x10>;
1398 };
1399
1400 opp-430000000 {
1401 opp-hz = /bits/ 64 <430000000>;
1402 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1403 opp-supported-hw = <0xff>;
1404 };
1405
1406 opp-355000000 {
1407 opp-hz = /bits/ 64 <355000000>;
1408 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1409 opp-supported-hw = <0xff>;
1410 };
1411
1412 opp-253000000 {
1413 opp-hz = /bits/ 64 <253000000>;
1414 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1415 opp-supported-hw = <0xff>;
1416 };
1417 };
1418 };
1419
1420 adreno_smmu: iommu@3d40000 {
1421 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1422 reg = <0 0x03d40000 0 0x10000>;
1423 #iommu-cells = <1>;
1424 #global-interrupts = <2>;
1425 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1435
1436 clocks = <&gpucc GPU_CC_AHB_CLK>,
1437 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1438 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1439 clock-names = "ahb",
1440 "bus",
1441 "iface";
1442
1443 power-domains = <&gpucc GPU_CX_GDSC>;
1444 };
1445
1446 gmu: gmu@3d6a000 {
1447 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1448 reg = <0 0x03d6a000 0 0x31000>,
1449 <0 0x0b290000 0 0x10000>,
1450 <0 0x0b490000 0 0x10000>;
1451 reg-names = "gmu",
1452 "gmu_pdc",
1453 "gmu_pdc_seq";
1454
1455 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1457 interrupt-names = "hfi",
1458 "gmu";
1459
1460 clocks = <&gpucc GPU_CC_AHB_CLK>,
1461 <&gpucc GPU_CC_CX_GMU_CLK>,
1462 <&gpucc GPU_CC_CXO_CLK>,
1463 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1464 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1465 clock-names = "ahb",
1466 "gmu",
1467 "cxo",
1468 "axi",
1469 "memnoc";
1470
1471 power-domains = <&gpucc GPU_CX_GDSC>,
1472 <&gpucc GPU_GX_GDSC>;
1473 power-domain-names = "cx",
1474 "gx";
1475
1476 iommus = <&adreno_smmu 5>;
1477
1478 operating-points-v2 = <&gmu_opp_table>;
1479
1480 gmu_opp_table: opp-table {
1481 compatible = "operating-points-v2";
1482
1483 opp-200000000 {
1484 opp-hz = /bits/ 64 <200000000>;
1485 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1486 };
1487 };
1488 };
1489
1490 gpucc: clock-controller@3d90000 {
1491 compatible = "qcom,sm6350-gpucc";
1492 reg = <0 0x03d90000 0 0x9000>;
1493 clocks = <&rpmhcc RPMH_CXO_CLK>,
1494 <&gcc GCC_GPU_GPLL0_CLK>,
1495 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1496 clock-names = "bi_tcxo",
1497 "gcc_gpu_gpll0_clk_src",
1498 "gcc_gpu_gpll0_div_clk_src";
1499 #clock-cells = <1>;
1500 #reset-cells = <1>;
1501 #power-domain-cells = <1>;
1502 };
1503
1504 mpss: remoteproc@4080000 {
1505 compatible = "qcom,sm6350-mpss-pas";
1506 reg = <0x0 0x04080000 0x0 0x4040>;
1507
1508 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1509 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1510 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1511 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1512 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1513 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1514 interrupt-names = "wdog", "fatal", "ready", "handover",
1515 "stop-ack", "shutdown-ack";
1516
1517 clocks = <&rpmhcc RPMH_CXO_CLK>;
1518 clock-names = "xo";
1519
1520 power-domains = <&rpmhpd SM6350_CX>,
1521 <&rpmhpd SM6350_MSS>;
1522 power-domain-names = "cx", "mss";
1523
1524 memory-region = <&pil_modem_mem>;
1525
1526 qcom,qmp = <&aoss_qmp>;
1527
1528 qcom,smem-states = <&modem_smp2p_out 0>;
1529 qcom,smem-state-names = "stop";
1530
1531 status = "disabled";
1532
1533 glink-edge {
1534 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1535 IPCC_MPROC_SIGNAL_GLINK_QMP
1536 IRQ_TYPE_EDGE_RISING>;
1537 mboxes = <&ipcc IPCC_CLIENT_MPSS
1538 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1539 label = "modem";
1540 qcom,remote-pid = <1>;
1541 };
1542 };
1543
1544 cdsp: remoteproc@8300000 {
1545 compatible = "qcom,sm6350-cdsp-pas";
1546 reg = <0 0x08300000 0 0x10000>;
1547
1548 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1549 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1550 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1551 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1552 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wdog", "fatal", "ready",
1554 "handover", "stop-ack";
1555
1556 clocks = <&rpmhcc RPMH_CXO_CLK>;
1557 clock-names = "xo";
1558
1559 power-domains = <&rpmhpd SM6350_CX>,
1560 <&rpmhpd SM6350_MX>;
1561 power-domain-names = "cx", "mx";
1562
1563 memory-region = <&pil_cdsp_mem>;
1564
1565 qcom,qmp = <&aoss_qmp>;
1566
1567 qcom,smem-states = <&smp2p_cdsp_out 0>;
1568 qcom,smem-state-names = "stop";
1569
1570 status = "disabled";
1571
1572 glink-edge {
1573 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1574 IPCC_MPROC_SIGNAL_GLINK_QMP
1575 IRQ_TYPE_EDGE_RISING>;
1576 mboxes = <&ipcc IPCC_CLIENT_CDSP
1577 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1578
1579 label = "cdsp";
1580 qcom,remote-pid = <5>;
1581
1582 fastrpc {
1583 compatible = "qcom,fastrpc";
1584 qcom,glink-channels = "fastrpcglink-apps-dsp";
1585 label = "cdsp";
1586 qcom,non-secure-domain;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589
1590 compute-cb@1 {
1591 compatible = "qcom,fastrpc-compute-cb";
1592 reg = <1>;
1593 iommus = <&apps_smmu 0x1401 0x20>;
1594 };
1595
1596 compute-cb@2 {
1597 compatible = "qcom,fastrpc-compute-cb";
1598 reg = <2>;
1599 iommus = <&apps_smmu 0x1402 0x20>;
1600 };
1601
1602 compute-cb@3 {
1603 compatible = "qcom,fastrpc-compute-cb";
1604 reg = <3>;
1605 iommus = <&apps_smmu 0x1403 0x20>;
1606 };
1607
1608 compute-cb@4 {
1609 compatible = "qcom,fastrpc-compute-cb";
1610 reg = <4>;
1611 iommus = <&apps_smmu 0x1404 0x20>;
1612 };
1613
1614 compute-cb@5 {
1615 compatible = "qcom,fastrpc-compute-cb";
1616 reg = <5>;
1617 iommus = <&apps_smmu 0x1405 0x20>;
1618 };
1619
1620 compute-cb@6 {
1621 compatible = "qcom,fastrpc-compute-cb";
1622 reg = <6>;
1623 iommus = <&apps_smmu 0x1406 0x20>;
1624 };
1625
1626 compute-cb@7 {
1627 compatible = "qcom,fastrpc-compute-cb";
1628 reg = <7>;
1629 iommus = <&apps_smmu 0x1407 0x20>;
1630 };
1631
1632 compute-cb@8 {
1633 compatible = "qcom,fastrpc-compute-cb";
1634 reg = <8>;
1635 iommus = <&apps_smmu 0x1408 0x20>;
1636 };
1637
1638 /* note: secure cb9 in downstream */
1639 };
1640 };
1641 };
1642
1643 sdhc_2: mmc@8804000 {
1644 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1645 reg = <0 0x08804000 0 0x1000>;
1646
1647 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1649 interrupt-names = "hc_irq", "pwr_irq";
1650 iommus = <&apps_smmu 0x560 0x0>;
1651
1652 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1653 <&gcc GCC_SDCC2_APPS_CLK>,
1654 <&rpmhcc RPMH_CXO_CLK>;
1655 clock-names = "iface", "core", "xo";
1656 resets = <&gcc GCC_SDCC2_BCR>;
1657 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1658 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1659 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1660
1661 pinctrl-0 = <&sdc2_on_state>;
1662 pinctrl-1 = <&sdc2_off_state>;
1663 pinctrl-names = "default", "sleep";
1664
1665 qcom,dll-config = <0x0007642c>;
1666 qcom,ddr-config = <0x80040868>;
1667 power-domains = <&rpmhpd SM6350_CX>;
1668 operating-points-v2 = <&sdhc2_opp_table>;
1669 bus-width = <4>;
1670
1671 status = "disabled";
1672
1673 sdhc2_opp_table: opp-table {
1674 compatible = "operating-points-v2";
1675
1676 opp-100000000 {
1677 opp-hz = /bits/ 64 <100000000>;
1678 required-opps = <&rpmhpd_opp_svs_l1>;
1679 opp-peak-kBps = <790000 131000>;
1680 opp-avg-kBps = <50000 50000>;
1681 };
1682
1683 opp-202000000 {
1684 opp-hz = /bits/ 64 <202000000>;
1685 required-opps = <&rpmhpd_opp_nom>;
1686 opp-peak-kBps = <3190000 294000>;
1687 opp-avg-kBps = <261438 300000>;
1688 };
1689 };
1690 };
1691
1692 usb_1_hsphy: phy@88e3000 {
1693 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1694 reg = <0 0x088e3000 0 0x400>;
1695 status = "disabled";
1696 #phy-cells = <0>;
1697
1698 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
1699 clock-names = "cfg_ahb", "ref";
1700
1701 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1702 };
1703
1704 usb_1_qmpphy: phy@88e8000 {
1705 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1706 reg = <0 0x088e8000 0 0x3000>;
1707
1708 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1709 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1710 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1711 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1712 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1713
1714 power-domains = <&gcc USB30_PRIM_GDSC>;
1715
1716 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1717 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1718 reset-names = "phy", "common";
1719
1720 orientation-switch;
1721
1722 #clock-cells = <1>;
1723 #phy-cells = <1>;
1724
1725 status = "disabled";
1726
1727 ports {
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1730
1731 port@0 {
1732 reg = <0>;
1733
1734 usb_1_qmpphy_out: endpoint {
1735 };
1736 };
1737
1738 port@1 {
1739 reg = <1>;
1740
1741 usb_1_qmpphy_usb_ss_in: endpoint {
1742 remote-endpoint = <&usb_1_dwc3_ss_out>;
1743 };
1744 };
1745
1746 port@2 {
1747 reg = <2>;
1748
1749 usb_1_qmpphy_dp_in: endpoint {
1750 };
1751 };
1752 };
1753 };
1754
1755 dc_noc: interconnect@9160000 {
1756 compatible = "qcom,sm6350-dc-noc";
1757 reg = <0 0x09160000 0 0x3200>;
1758 #interconnect-cells = <2>;
1759 qcom,bcm-voters = <&apps_bcm_voter>;
1760 };
1761
1762 system-cache-controller@9200000 {
1763 compatible = "qcom,sm6350-llcc";
1764 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1765 reg-names = "llcc0_base", "llcc_broadcast_base";
1766 };
1767
1768 gem_noc: interconnect@9680000 {
1769 compatible = "qcom,sm6350-gem-noc";
1770 reg = <0 0x09680000 0 0x3e200>;
1771 #interconnect-cells = <2>;
1772 qcom,bcm-voters = <&apps_bcm_voter>;
1773 };
1774
1775 npu_noc: interconnect@9990000 {
1776 compatible = "qcom,sm6350-npu-noc";
1777 reg = <0 0x09990000 0 0x1600>;
1778 #interconnect-cells = <2>;
1779 qcom,bcm-voters = <&apps_bcm_voter>;
1780 };
1781
1782 pmu@90b6300 {
1783 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1784 reg = <0x0 0x090b6300 0x0 0x600>;
1785 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1786
1787 operating-points-v2 = <&llcc_bwmon_opp_table>;
1788 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
1789 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1790
1791 llcc_bwmon_opp_table: opp-table {
1792 compatible = "operating-points-v2";
1793
1794 opp-0 {
1795 opp-peak-kBps = <2288000>;
1796 };
1797
1798 opp-1 {
1799 opp-peak-kBps = <4577000>;
1800 };
1801
1802 opp-2 {
1803 opp-peak-kBps = <7110000>;
1804 };
1805
1806 opp-3 {
1807 opp-peak-kBps = <9155000>;
1808 };
1809
1810 opp-4 {
1811 opp-peak-kBps = <12298000>;
1812 };
1813
1814 opp-5 {
1815 opp-peak-kBps = <14236000>;
1816 };
1817
1818 };
1819 };
1820
1821 pmu@90cd000 {
1822 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1823 reg = <0x0 0x090cd000 0x0 0x1000>;
1824 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1825
1826 operating-points-v2 = <&cpu_bwmon_opp_table>;
1827 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
1828 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;
1829
1830 cpu_bwmon_opp_table: opp-table {
1831 compatible = "operating-points-v2";
1832
1833 opp-0 {
1834 opp-peak-kBps = <762000>;
1835 };
1836
1837 opp-1 {
1838 opp-peak-kBps = <1144000>;
1839 };
1840
1841 opp-2 {
1842 opp-peak-kBps = <1720000>;
1843 };
1844
1845 opp-3 {
1846 opp-peak-kBps = <2086000>;
1847 };
1848
1849 opp-4 {
1850 opp-peak-kBps = <2597000>;
1851 };
1852
1853 opp-5 {
1854 opp-peak-kBps = <2929000>;
1855 };
1856
1857 opp-6 {
1858 opp-peak-kBps = <3879000>;
1859 };
1860
1861 opp-7 {
1862 opp-peak-kBps = <5161000>;
1863 };
1864
1865 opp-8 {
1866 opp-peak-kBps = <5931000>;
1867 };
1868
1869 opp-9 {
1870 opp-peak-kBps = <6881000>;
1871 };
1872
1873 opp-10 {
1874 opp-peak-kBps = <7980000>;
1875 };
1876 };
1877 };
1878
1879 usb_1: usb@a6f8800 {
1880 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1881 reg = <0 0x0a6f8800 0 0x400>;
1882 status = "disabled";
1883 #address-cells = <2>;
1884 #size-cells = <2>;
1885 ranges;
1886
1887 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1888 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1889 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1890 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1891 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1892 clock-names = "cfg_noc",
1893 "core",
1894 "iface",
1895 "sleep",
1896 "mock_utmi";
1897
1898 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1899 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1900 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1901 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1902 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1903 interrupt-names = "pwr_event",
1904 "hs_phy_irq",
1905 "dp_hs_phy_irq",
1906 "dm_hs_phy_irq",
1907 "ss_phy_irq";
1908
1909 power-domains = <&gcc USB30_PRIM_GDSC>;
1910
1911 resets = <&gcc GCC_USB30_PRIM_BCR>;
1912
1913 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1915 interconnect-names = "usb-ddr", "apps-usb";
1916
1917 usb_1_dwc3: usb@a600000 {
1918 compatible = "snps,dwc3";
1919 reg = <0 0x0a600000 0 0xcd00>;
1920 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1921 iommus = <&apps_smmu 0x540 0x0>;
1922 snps,dis_u2_susphy_quirk;
1923 snps,dis_enblslpm_quirk;
1924 snps,has-lpm-erratum;
1925 snps,hird-threshold = /bits/ 8 <0x10>;
1926 snps,parkmode-disable-ss-quirk;
1927 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
1928 phy-names = "usb2-phy", "usb3-phy";
1929 usb-role-switch;
1930
1931 ports {
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934
1935 port@0 {
1936 reg = <0>;
1937
1938 usb_1_dwc3_hs_out: endpoint {
1939 };
1940 };
1941
1942 port@1 {
1943 reg = <1>;
1944
1945 usb_1_dwc3_ss_out: endpoint {
1946 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
1947 };
1948 };
1949 };
1950 };
1951 };
1952
1953 cci0: cci@ac4a000 {
1954 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1955 reg = <0 0x0ac4a000 0 0x1000>;
1956 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
1957 power-domains = <&camcc TITAN_TOP_GDSC>;
1958
1959 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1960 <&camcc CAMCC_SOC_AHB_CLK>,
1961 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
1962 <&camcc CAMCC_CPAS_AHB_CLK>,
1963 <&camcc CAMCC_CCI_0_CLK>,
1964 <&camcc CAMCC_CCI_0_CLK_SRC>;
1965 clock-names = "camnoc_axi",
1966 "soc_ahb",
1967 "slow_ahb_src",
1968 "cpas_ahb",
1969 "cci",
1970 "cci_src";
1971
1972 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1973 <&camcc CAMCC_CCI_0_CLK>;
1974 assigned-clock-rates = <80000000>, <37500000>;
1975
1976 pinctrl-0 = <&cci0_default &cci1_default>;
1977 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1978 pinctrl-names = "default", "sleep";
1979
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1982
1983 status = "disabled";
1984
1985 cci0_i2c0: i2c-bus@0 {
1986 reg = <0>;
1987 clock-frequency = <1000000>;
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990 };
1991
1992 cci0_i2c1: i2c-bus@1 {
1993 reg = <1>;
1994 clock-frequency = <1000000>;
1995 #address-cells = <1>;
1996 #size-cells = <0>;
1997 };
1998 };
1999
2000 cci1: cci@ac4b000 {
2001 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
2002 reg = <0 0x0ac4b000 0 0x1000>;
2003 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
2004 power-domains = <&camcc TITAN_TOP_GDSC>;
2005
2006 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2007 <&camcc CAMCC_SOC_AHB_CLK>,
2008 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
2009 <&camcc CAMCC_CPAS_AHB_CLK>,
2010 <&camcc CAMCC_CCI_1_CLK>,
2011 <&camcc CAMCC_CCI_1_CLK_SRC>;
2012 clock-names = "camnoc_axi",
2013 "soc_ahb",
2014 "slow_ahb_src",
2015 "cpas_ahb",
2016 "cci",
2017 "cci_src";
2018
2019 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
2020 <&camcc CAMCC_CCI_1_CLK>;
2021 assigned-clock-rates = <80000000>, <37500000>;
2022
2023 pinctrl-0 = <&cci2_default>;
2024 pinctrl-1 = <&cci2_sleep>;
2025 pinctrl-names = "default", "sleep";
2026
2027 #address-cells = <1>;
2028 #size-cells = <0>;
2029
2030 status = "disabled";
2031
2032 cci1_i2c0: i2c-bus@0 {
2033 reg = <0>;
2034 clock-frequency = <1000000>;
2035 #address-cells = <1>;
2036 #size-cells = <0>;
2037 };
2038
2039 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
2040 };
2041
2042 camcc: clock-controller@ad00000 {
2043 compatible = "qcom,sm6350-camcc";
2044 reg = <0 0x0ad00000 0 0x16000>;
2045 clocks = <&rpmhcc RPMH_CXO_CLK>;
2046 #clock-cells = <1>;
2047 #reset-cells = <1>;
2048 #power-domain-cells = <1>;
2049 };
2050
2051 mdss: display-subsystem@ae00000 {
2052 compatible = "qcom,sm6350-mdss";
2053 reg = <0 0x0ae00000 0 0x1000>;
2054 reg-names = "mdss";
2055
2056 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2057 interrupt-controller;
2058 #interrupt-cells = <1>;
2059
2060 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
2061 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2062 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
2063 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2064 interconnect-names = "mdp0-mem",
2065 "cpu-cfg";
2066
2067 clocks = <&gcc GCC_DISP_AHB_CLK>,
2068 <&gcc GCC_DISP_AXI_CLK>,
2069 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2070 clock-names = "iface",
2071 "bus",
2072 "core";
2073
2074 power-domains = <&dispcc MDSS_GDSC>;
2075 iommus = <&apps_smmu 0x800 0x2>;
2076
2077 #address-cells = <2>;
2078 #size-cells = <2>;
2079 ranges;
2080
2081 status = "disabled";
2082
2083 mdss_mdp: display-controller@ae01000 {
2084 compatible = "qcom,sm6350-dpu";
2085 reg = <0 0x0ae01000 0 0x8f000>,
2086 <0 0x0aeb0000 0 0x2008>;
2087 reg-names = "mdp", "vbif";
2088
2089 interrupt-parent = <&mdss>;
2090 interrupts = <0>;
2091
2092 clocks = <&gcc GCC_DISP_AXI_CLK>,
2093 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2094 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2095 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2096 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2097 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2098 clock-names = "bus",
2099 "iface",
2100 "rot",
2101 "lut",
2102 "core",
2103 "vsync";
2104
2105 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2106 assigned-clock-rates = <19200000>;
2107
2108 operating-points-v2 = <&mdp_opp_table>;
2109 power-domains = <&rpmhpd SM6350_CX>;
2110
2111 ports {
2112 #address-cells = <1>;
2113 #size-cells = <0>;
2114
2115 port@0 {
2116 reg = <0>;
2117
2118 dpu_intf1_out: endpoint {
2119 remote-endpoint = <&mdss_dsi0_in>;
2120 };
2121 };
2122
2123 port@2 {
2124 reg = <2>;
2125
2126 dpu_intf0_out: endpoint {
2127 remote-endpoint = <&mdss_dp_in>;
2128 };
2129 };
2130 };
2131
2132 mdp_opp_table: opp-table {
2133 compatible = "operating-points-v2";
2134
2135 opp-19200000 {
2136 opp-hz = /bits/ 64 <19200000>;
2137 required-opps = <&rpmhpd_opp_min_svs>;
2138 };
2139
2140 opp-200000000 {
2141 opp-hz = /bits/ 64 <200000000>;
2142 required-opps = <&rpmhpd_opp_low_svs>;
2143 };
2144
2145 opp-300000000 {
2146 opp-hz = /bits/ 64 <300000000>;
2147 required-opps = <&rpmhpd_opp_svs>;
2148 };
2149
2150 opp-373333333 {
2151 opp-hz = /bits/ 64 <373333333>;
2152 required-opps = <&rpmhpd_opp_svs_l1>;
2153 };
2154
2155 opp-448000000 {
2156 opp-hz = /bits/ 64 <448000000>;
2157 required-opps = <&rpmhpd_opp_nom>;
2158 };
2159
2160 opp-560000000 {
2161 opp-hz = /bits/ 64 <560000000>;
2162 required-opps = <&rpmhpd_opp_turbo>;
2163 };
2164 };
2165 };
2166
2167 mdss_dp: displayport-controller@ae90000 {
2168 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
2169 reg = <0 0xae90000 0 0x200>,
2170 <0 0xae90200 0 0x200>,
2171 <0 0xae90400 0 0x600>,
2172 <0 0xae91000 0 0x400>,
2173 <0 0xae91400 0 0x400>;
2174 interrupt-parent = <&mdss>;
2175 interrupts = <12>;
2176 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2177 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2178 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2179 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2180 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2181 clock-names = "core_iface",
2182 "core_aux",
2183 "ctrl_link",
2184 "ctrl_link_iface",
2185 "stream_pixel";
2186
2187 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2188 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2189 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2190 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2191
2192 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2193 phy-names = "dp";
2194
2195 #sound-dai-cells = <0>;
2196
2197 operating-points-v2 = <&dp_opp_table>;
2198 power-domains = <&rpmhpd SM6350_CX>;
2199
2200 status = "disabled";
2201
2202 ports {
2203 #address-cells = <1>;
2204 #size-cells = <0>;
2205
2206 port@0 {
2207 reg = <0>;
2208
2209 mdss_dp_in: endpoint {
2210 remote-endpoint = <&dpu_intf0_out>;
2211 };
2212 };
2213
2214 port@1 {
2215 reg = <1>;
2216
2217 mdss_dp_out: endpoint {
2218 };
2219 };
2220 };
2221
2222 dp_opp_table: opp-table {
2223 compatible = "operating-points-v2";
2224
2225 opp-160000000 {
2226 opp-hz = /bits/ 64 <160000000>;
2227 required-opps = <&rpmhpd_opp_low_svs>;
2228 };
2229
2230 opp-270000000 {
2231 opp-hz = /bits/ 64 <270000000>;
2232 required-opps = <&rpmhpd_opp_svs>;
2233 };
2234
2235 opp-540000000 {
2236 opp-hz = /bits/ 64 <540000000>;
2237 required-opps = <&rpmhpd_opp_svs_l1>;
2238 };
2239
2240 opp-810000000 {
2241 opp-hz = /bits/ 64 <810000000>;
2242 required-opps = <&rpmhpd_opp_nom>;
2243 };
2244 };
2245 };
2246
2247 mdss_dsi0: dsi@ae94000 {
2248 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2249 reg = <0 0x0ae94000 0 0x400>;
2250 reg-names = "dsi_ctrl";
2251
2252 interrupt-parent = <&mdss>;
2253 interrupts = <4>;
2254
2255 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2256 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2257 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2258 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2259 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2260 <&gcc GCC_DISP_AXI_CLK>;
2261 clock-names = "byte",
2262 "byte_intf",
2263 "pixel",
2264 "core",
2265 "iface",
2266 "bus";
2267
2268 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2269 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2271
2272 operating-points-v2 = <&mdss_dsi_opp_table>;
2273 power-domains = <&rpmhpd SM6350_MX>;
2274
2275 phys = <&mdss_dsi0_phy>;
2276 phy-names = "dsi";
2277
2278 #address-cells = <1>;
2279 #size-cells = <0>;
2280
2281 status = "disabled";
2282
2283 ports {
2284 #address-cells = <1>;
2285 #size-cells = <0>;
2286
2287 port@0 {
2288 reg = <0>;
2289
2290 mdss_dsi0_in: endpoint {
2291 remote-endpoint = <&dpu_intf1_out>;
2292 };
2293 };
2294
2295 port@1 {
2296 reg = <1>;
2297
2298 mdss_dsi0_out: endpoint {
2299 };
2300 };
2301 };
2302
2303 mdss_dsi_opp_table: opp-table {
2304 compatible = "operating-points-v2";
2305
2306 opp-187500000 {
2307 opp-hz = /bits/ 64 <187500000>;
2308 required-opps = <&rpmhpd_opp_low_svs>;
2309 };
2310
2311 opp-300000000 {
2312 opp-hz = /bits/ 64 <300000000>;
2313 required-opps = <&rpmhpd_opp_svs>;
2314 };
2315
2316 opp-358000000 {
2317 opp-hz = /bits/ 64 <358000000>;
2318 required-opps = <&rpmhpd_opp_svs_l1>;
2319 };
2320 };
2321 };
2322
2323 mdss_dsi0_phy: phy@ae94400 {
2324 compatible = "qcom,dsi-phy-10nm";
2325 reg = <0 0x0ae94400 0 0x200>,
2326 <0 0x0ae94600 0 0x280>,
2327 <0 0x0ae94a00 0 0x1e0>;
2328 reg-names = "dsi_phy",
2329 "dsi_phy_lane",
2330 "dsi_pll";
2331
2332 #clock-cells = <1>;
2333 #phy-cells = <0>;
2334
2335 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2336 <&rpmhcc RPMH_CXO_CLK>;
2337 clock-names = "iface", "ref";
2338
2339 status = "disabled";
2340 };
2341 };
2342
2343 dispcc: clock-controller@af00000 {
2344 compatible = "qcom,sm6350-dispcc";
2345 reg = <0 0x0af00000 0 0x20000>;
2346 clocks = <&rpmhcc RPMH_CXO_CLK>,
2347 <&gcc GCC_DISP_GPLL0_CLK>,
2348 <&mdss_dsi0_phy 0>,
2349 <&mdss_dsi0_phy 1>,
2350 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2351 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2352 clock-names = "bi_tcxo",
2353 "gcc_disp_gpll0_clk",
2354 "dsi0_phy_pll_out_byteclk",
2355 "dsi0_phy_pll_out_dsiclk",
2356 "dp_phy_pll_link_clk",
2357 "dp_phy_pll_vco_div_clk";
2358 #clock-cells = <1>;
2359 #reset-cells = <1>;
2360 #power-domain-cells = <1>;
2361 };
2362
2363 pdc: interrupt-controller@b220000 {
2364 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2365 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
2366 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2367 <125 63 1>, <126 655 12>, <138 139 15>;
2368 #interrupt-cells = <2>;
2369 interrupt-parent = <&intc>;
2370 interrupt-controller;
2371 };
2372
2373 tsens0: thermal-sensor@c263000 {
2374 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2375 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2376 <0 0x0c222000 0 0x8>; /* SROT */
2377 #qcom,sensors = <16>;
2378 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2379 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2380 interrupt-names = "uplow", "critical";
2381 #thermal-sensor-cells = <1>;
2382 };
2383
2384 tsens1: thermal-sensor@c265000 {
2385 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2386 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2387 <0 0x0c223000 0 0x8>; /* SROT */
2388 #qcom,sensors = <16>;
2389 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2390 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2391 interrupt-names = "uplow", "critical";
2392 #thermal-sensor-cells = <1>;
2393 };
2394
2395 aoss_qmp: power-management@c300000 {
2396 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2397 reg = <0 0x0c300000 0 0x1000>;
2398 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2399 IRQ_TYPE_EDGE_RISING>;
2400 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2401
2402 #clock-cells = <0>;
2403 };
2404
2405 spmi_bus: spmi@c440000 {
2406 compatible = "qcom,spmi-pmic-arb";
2407 reg = <0 0x0c440000 0 0x1100>,
2408 <0 0x0c600000 0 0x2000000>,
2409 <0 0x0e600000 0 0x100000>,
2410 <0 0x0e700000 0 0xa0000>,
2411 <0 0x0c40a000 0 0x26000>;
2412 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2413 interrupt-names = "periph_irq";
2414 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2415 qcom,ee = <0>;
2416 qcom,channel = <0>;
2417 #address-cells = <2>;
2418 #size-cells = <0>;
2419 interrupt-controller;
2420 #interrupt-cells = <4>;
2421 };
2422
2423 tlmm: pinctrl@f100000 {
2424 compatible = "qcom,sm6350-tlmm";
2425 reg = <0 0x0f100000 0 0x300000>;
2426 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
2428 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
2429 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
2430 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
2431 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
2432 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
2433 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
2434 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
2435 gpio-controller;
2436 #gpio-cells = <2>;
2437 interrupt-controller;
2438 #interrupt-cells = <2>;
2439 gpio-ranges = <&tlmm 0 0 157>;
2440 wakeup-parent = <&pdc>;
2441
2442 cci0_default: cci0-default-state {
2443 pins = "gpio39", "gpio40";
2444 function = "cci_i2c";
2445 drive-strength = <2>;
2446 bias-pull-up;
2447 };
2448
2449 cci0_sleep: cci0-sleep-state {
2450 pins = "gpio39", "gpio40";
2451 function = "cci_i2c";
2452 drive-strength = <2>;
2453 bias-pull-down;
2454 };
2455
2456 cci1_default: cci1-default-state {
2457 pins = "gpio41", "gpio42";
2458 function = "cci_i2c";
2459 drive-strength = <2>;
2460 bias-pull-up;
2461 };
2462
2463 cci1_sleep: cci1-sleep-state {
2464 pins = "gpio41", "gpio42";
2465 function = "cci_i2c";
2466 drive-strength = <2>;
2467 bias-pull-down;
2468 };
2469
2470 cci2_default: cci2-default-state {
2471 pins = "gpio43", "gpio44";
2472 function = "cci_i2c";
2473 drive-strength = <2>;
2474 bias-pull-up;
2475 };
2476
2477 cci2_sleep: cci2-sleep-state {
2478 pins = "gpio43", "gpio44";
2479 function = "cci_i2c";
2480 drive-strength = <2>;
2481 bias-pull-down;
2482 };
2483
2484 sdc2_off_state: sdc2-off-state {
2485 clk-pins {
2486 pins = "sdc2_clk";
2487 drive-strength = <2>;
2488 bias-disable;
2489 };
2490
2491 cmd-pins {
2492 pins = "sdc2_cmd";
2493 drive-strength = <2>;
2494 bias-pull-up;
2495 };
2496
2497 data-pins {
2498 pins = "sdc2_data";
2499 drive-strength = <2>;
2500 bias-pull-up;
2501 };
2502 };
2503
2504 sdc2_on_state: sdc2-on-state {
2505 clk-pins {
2506 pins = "sdc2_clk";
2507 drive-strength = <16>;
2508 bias-disable;
2509 };
2510
2511 cmd-pins {
2512 pins = "sdc2_cmd";
2513 drive-strength = <10>;
2514 bias-pull-up;
2515 };
2516
2517 data-pins {
2518 pins = "sdc2_data";
2519 drive-strength = <10>;
2520 bias-pull-up;
2521 };
2522 };
2523
2524 qup_uart9_default: qup-uart9-default-state {
2525 pins = "gpio25", "gpio26";
2526 function = "qup13_f2";
2527 drive-strength = <2>;
2528 bias-disable;
2529 };
2530
2531 qup_i2c0_default: qup-i2c0-default-state {
2532 pins = "gpio0", "gpio1";
2533 function = "qup00";
2534 drive-strength = <2>;
2535 bias-pull-up;
2536 };
2537
2538 qup_i2c2_default: qup-i2c2-default-state {
2539 pins = "gpio45", "gpio46";
2540 function = "qup02";
2541 drive-strength = <2>;
2542 bias-pull-up;
2543 };
2544
2545 qup_i2c6_default: qup-i2c6-default-state {
2546 pins = "gpio13", "gpio14";
2547 function = "qup10";
2548 drive-strength = <2>;
2549 bias-pull-up;
2550 };
2551
2552 qup_i2c7_default: qup-i2c7-default-state {
2553 pins = "gpio27", "gpio28";
2554 function = "qup11";
2555 drive-strength = <2>;
2556 bias-pull-up;
2557 };
2558
2559 qup_i2c8_default: qup-i2c8-default-state {
2560 pins = "gpio19", "gpio20";
2561 function = "qup12";
2562 drive-strength = <2>;
2563 bias-pull-up;
2564 };
2565
2566 qup_i2c10_default: qup-i2c10-default-state {
2567 pins = "gpio4", "gpio5";
2568 function = "qup14";
2569 drive-strength = <2>;
2570 bias-pull-up;
2571 };
2572
2573 qup_uart1_cts: qup-uart1-cts-default-state {
2574 pins = "gpio61";
2575 function = "qup01";
2576 drive-strength = <2>;
2577 bias-disable;
2578 };
2579
2580 qup_uart1_rts: qup-uart1-rts-default-state {
2581 pins = "gpio62";
2582 function = "qup01";
2583 drive-strength = <2>;
2584 bias-pull-down;
2585 };
2586
2587 qup_uart1_rx: qup-uart1-rx-default-state {
2588 pins = "gpio64";
2589 function = "qup01";
2590 drive-strength = <2>;
2591 bias-disable;
2592 };
2593
2594 qup_uart1_tx: qup-uart1-tx-default-state {
2595 pins = "gpio63";
2596 function = "qup01";
2597 drive-strength = <2>;
2598 bias-pull-up;
2599 };
2600 };
2601
2602 apps_smmu: iommu@15000000 {
2603 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2604 reg = <0 0x15000000 0 0x100000>;
2605 #iommu-cells = <2>;
2606 #global-interrupts = <1>;
2607 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2608 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2609 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2610 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2611 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2612 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2613 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2614 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2615 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2616 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2617 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2618 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2619 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2620 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2621 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2622 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2623 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2624 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2625 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2626 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2627 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2628 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2629 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2630 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2631 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2632 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2633 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2634 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2635 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2636 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2637 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2638 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2639 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2640 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2641 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2643 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2644 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2645 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2646 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2647 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2649 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2650 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2651 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2652 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2653 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2654 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2655 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2656 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2657 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2658 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2659 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2660 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2661 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2662 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2663 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2664 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2665 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2666 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2667 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2668 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2670 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2671 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2672 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2673 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2674 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2675 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2676 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2677 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2678 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2679 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2680 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2681 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2682 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2683 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2684 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2685 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2686 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2687 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
2688 };
2689
2690 intc: interrupt-controller@17a00000 {
2691 compatible = "arm,gic-v3";
2692 #interrupt-cells = <3>;
2693 interrupt-controller;
2694 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2695 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2696 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
2697 };
2698
2699 watchdog@17c10000 {
2700 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2701 reg = <0 0x17c10000 0 0x1000>;
2702 clocks = <&sleep_clk>;
2703 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
2704 };
2705
2706 timer@17c20000 {
2707 compatible = "arm,armv7-timer-mem";
2708 reg = <0x0 0x17c20000 0x0 0x1000>;
2709 clock-frequency = <19200000>;
2710 #address-cells = <1>;
2711 #size-cells = <1>;
2712 ranges = <0 0 0 0x20000000>;
2713
2714 frame@17c21000 {
2715 frame-number = <0>;
2716 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2717 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2718 reg = <0x17c21000 0x1000>,
2719 <0x17c22000 0x1000>;
2720 };
2721
2722 frame@17c23000 {
2723 frame-number = <1>;
2724 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2725 reg = <0x17c23000 0x1000>;
2726 status = "disabled";
2727 };
2728
2729 frame@17c25000 {
2730 frame-number = <2>;
2731 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2732 reg = <0x17c25000 0x1000>;
2733 status = "disabled";
2734 };
2735
2736 frame@17c27000 {
2737 frame-number = <3>;
2738 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2739 reg = <0x17c27000 0x1000>;
2740 status = "disabled";
2741 };
2742
2743 frame@17c29000 {
2744 frame-number = <4>;
2745 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2746 reg = <0x17c29000 0x1000>;
2747 status = "disabled";
2748 };
2749
2750 frame@17c2b000 {
2751 frame-number = <5>;
2752 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2753 reg = <0x17c2b000 0x1000>;
2754 status = "disabled";
2755 };
2756
2757 frame@17c2d000 {
2758 frame-number = <6>;
2759 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2760 reg = <0x17c2d000 0x1000>;
2761 status = "disabled";
2762 };
2763 };
2764
2765 apps_rsc: rsc@18200000 {
2766 compatible = "qcom,rpmh-rsc";
2767 label = "apps_rsc";
2768 reg = <0x0 0x18200000 0x0 0x10000>,
2769 <0x0 0x18210000 0x0 0x10000>,
2770 <0x0 0x18220000 0x0 0x10000>;
2771 reg-names = "drv-0", "drv-1", "drv-2";
2772 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2773 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2774 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2775 qcom,tcs-offset = <0xd00>;
2776 qcom,drv-id = <2>;
2777 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2778 <WAKE_TCS 3>, <CONTROL_TCS 1>;
2779 power-domains = <&CLUSTER_PD>;
2780
2781 rpmhcc: clock-controller {
2782 compatible = "qcom,sm6350-rpmh-clk";
2783 #clock-cells = <1>;
2784 clock-names = "xo";
2785 clocks = <&xo_board>;
2786 };
2787
2788 rpmhpd: power-controller {
2789 compatible = "qcom,sm6350-rpmhpd";
2790 #power-domain-cells = <1>;
2791 operating-points-v2 = <&rpmhpd_opp_table>;
2792
2793 rpmhpd_opp_table: opp-table {
2794 compatible = "operating-points-v2";
2795
2796 rpmhpd_opp_ret: opp1 {
2797 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2798 };
2799
2800 rpmhpd_opp_min_svs: opp2 {
2801 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2802 };
2803
2804 rpmhpd_opp_low_svs: opp3 {
2805 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2806 };
2807
2808 rpmhpd_opp_svs: opp4 {
2809 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2810 };
2811
2812 rpmhpd_opp_svs_l1: opp5 {
2813 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2814 };
2815
2816 rpmhpd_opp_nom: opp6 {
2817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2818 };
2819
2820 rpmhpd_opp_nom_l1: opp7 {
2821 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2822 };
2823
2824 rpmhpd_opp_nom_l2: opp8 {
2825 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2826 };
2827
2828 rpmhpd_opp_turbo: opp9 {
2829 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2830 };
2831
2832 rpmhpd_opp_turbo_l1: opp10 {
2833 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2834 };
2835 };
2836 };
2837
2838 apps_bcm_voter: bcm-voter {
2839 compatible = "qcom,bcm-voter";
2840 };
2841 };
2842
2843 osm_l3: interconnect@18321000 {
2844 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2845 reg = <0x0 0x18321000 0x0 0x1000>;
2846
2847 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2848 clock-names = "xo", "alternate";
2849
2850 #interconnect-cells = <1>;
2851 };
2852
2853 cpufreq_hw: cpufreq@18323000 {
2854 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2855 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2856 reg-names = "freq-domain0", "freq-domain1";
2857 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2858 clock-names = "xo", "alternate";
2859
2860 #freq-domain-cells = <1>;
2861 #clock-cells = <1>;
2862 };
2863
2864 wifi: wifi@18800000 {
2865 compatible = "qcom,wcn3990-wifi";
2866 reg = <0 0x18800000 0 0x800000>;
2867 reg-names = "membase";
2868 memory-region = <&wlan_fw_mem>;
2869 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2870 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2871 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2872 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2873 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2874 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2875 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2876 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2877 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2878 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2880 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2881 iommus = <&apps_smmu 0x20 0x1>;
2882 qcom,msa-fixed-perm;
2883 status = "disabled";
2884 };
2885 };
2886
2887 thermal-zones {
2888 aoss0-thermal {
2889 thermal-sensors = <&tsens0 0>;
2890
2891 trips {
2892 aoss0-crit {
2893 temperature = <125000>;
2894 hysteresis = <0>;
2895 type = "critical";
2896 };
2897 };
2898 };
2899
2900 aoss1-thermal {
2901 thermal-sensors = <&tsens1 0>;
2902
2903 trips {
2904 aoss1-crit {
2905 temperature = <125000>;
2906 hysteresis = <0>;
2907 type = "critical";
2908 };
2909 };
2910 };
2911
2912 audio-thermal {
2913 thermal-sensors = <&tsens1 2>;
2914
2915 trips {
2916 audio-crit {
2917 temperature = <125000>;
2918 hysteresis = <0>;
2919 type = "critical";
2920 };
2921 };
2922 };
2923
2924 camera-thermal {
2925 thermal-sensors = <&tsens1 5>;
2926
2927 trips {
2928 camera-crit {
2929 temperature = <125000>;
2930 hysteresis = <0>;
2931 type = "critical";
2932 };
2933 };
2934 };
2935
2936 cpu0-thermal {
2937 thermal-sensors = <&tsens0 1>;
2938
2939 trips {
2940 cpu0_alert0: trip-point0 {
2941 temperature = <95000>;
2942 hysteresis = <2000>;
2943 type = "passive";
2944 };
2945
2946 cpu0-crit {
2947 temperature = <115000>;
2948 hysteresis = <0>;
2949 type = "critical";
2950 };
2951 };
2952
2953 cooling-maps {
2954 map0 {
2955 trip = <&cpu0_alert0>;
2956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2957 };
2958 };
2959 };
2960
2961 cpu1-thermal {
2962 thermal-sensors = <&tsens0 2>;
2963
2964 trips {
2965 cpu1_alert0: trip-point0 {
2966 temperature = <95000>;
2967 hysteresis = <2000>;
2968 type = "passive";
2969 };
2970
2971 cpu1-crit {
2972 temperature = <115000>;
2973 hysteresis = <0>;
2974 type = "critical";
2975 };
2976 };
2977
2978 cooling-maps {
2979 map0 {
2980 trip = <&cpu1_alert0>;
2981 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2982 };
2983 };
2984 };
2985
2986 cpu2-thermal {
2987 thermal-sensors = <&tsens0 3>;
2988
2989 trips {
2990 cpu2_alert0: trip-point0 {
2991 temperature = <95000>;
2992 hysteresis = <2000>;
2993 type = "passive";
2994 };
2995
2996 cpu2-crit {
2997 temperature = <115000>;
2998 hysteresis = <0>;
2999 type = "critical";
3000 };
3001 };
3002
3003 cooling-maps {
3004 map0 {
3005 trip = <&cpu2_alert0>;
3006 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3007 };
3008 };
3009 };
3010
3011 cpu3-thermal {
3012 thermal-sensors = <&tsens0 4>;
3013
3014 trips {
3015 cpu3_alert0: trip-point0 {
3016 temperature = <95000>;
3017 hysteresis = <2000>;
3018 type = "passive";
3019 };
3020
3021 cpu3-crit {
3022 temperature = <115000>;
3023 hysteresis = <0>;
3024 type = "critical";
3025 };
3026 };
3027
3028 cooling-maps {
3029 map0 {
3030 trip = <&cpu3_alert0>;
3031 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3032 };
3033 };
3034 };
3035
3036 cpu4-thermal {
3037 thermal-sensors = <&tsens0 5>;
3038
3039 trips {
3040 cpu4_alert0: trip-point0 {
3041 temperature = <95000>;
3042 hysteresis = <2000>;
3043 type = "passive";
3044 };
3045
3046 cpu4-crit {
3047 temperature = <115000>;
3048 hysteresis = <0>;
3049 type = "critical";
3050 };
3051 };
3052
3053 cooling-maps {
3054 map0 {
3055 trip = <&cpu4_alert0>;
3056 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3057 };
3058 };
3059 };
3060
3061 cpu5-thermal {
3062 thermal-sensors = <&tsens0 6>;
3063
3064 trips {
3065 cpu5_alert0: trip-point0 {
3066 temperature = <95000>;
3067 hysteresis = <2000>;
3068 type = "passive";
3069 };
3070
3071 cpu5-crit {
3072 temperature = <115000>;
3073 hysteresis = <0>;
3074 type = "critical";
3075 };
3076 };
3077
3078 cooling-maps {
3079 map0 {
3080 trip = <&cpu5_alert0>;
3081 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3082 };
3083 };
3084 };
3085
3086 cpu6-left-thermal {
3087 thermal-sensors = <&tsens0 9>;
3088
3089 trips {
3090 cpu6_left_alert0: trip-point0 {
3091 temperature = <95000>;
3092 hysteresis = <2000>;
3093 type = "passive";
3094 };
3095
3096 cpu6-left-crit {
3097 temperature = <115000>;
3098 hysteresis = <0>;
3099 type = "critical";
3100 };
3101 };
3102
3103 cooling-maps {
3104 map0 {
3105 trip = <&cpu6_left_alert0>;
3106 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3107 };
3108 };
3109 };
3110
3111 cpu6-right-thermal {
3112 thermal-sensors = <&tsens0 10>;
3113
3114 trips {
3115 cpu6_right_alert0: trip-point0 {
3116 temperature = <95000>;
3117 hysteresis = <2000>;
3118 type = "passive";
3119 };
3120
3121 cpu6-right-crit {
3122 temperature = <115000>;
3123 hysteresis = <0>;
3124 type = "critical";
3125 };
3126 };
3127
3128 cooling-maps {
3129 map0 {
3130 trip = <&cpu6_right_alert0>;
3131 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3132 };
3133 };
3134 };
3135
3136 cpu7-left-thermal {
3137 thermal-sensors = <&tsens0 11>;
3138
3139 trips {
3140 cpu7_left_alert0: trip-point0 {
3141 temperature = <95000>;
3142 hysteresis = <2000>;
3143 type = "passive";
3144 };
3145
3146 cpu7-left-crit {
3147 temperature = <115000>;
3148 hysteresis = <0>;
3149 type = "critical";
3150 };
3151 };
3152
3153 cooling-maps {
3154 map0 {
3155 trip = <&cpu7_left_alert0>;
3156 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3157 };
3158 };
3159 };
3160
3161 cpu7-right-thermal {
3162 thermal-sensors = <&tsens0 12>;
3163
3164 trips {
3165 cpu7_right_alert0: trip-point0 {
3166 temperature = <95000>;
3167 hysteresis = <2000>;
3168 type = "passive";
3169 };
3170
3171 cpu7-right-crit {
3172 temperature = <115000>;
3173 hysteresis = <0>;
3174 type = "critical";
3175 };
3176 };
3177
3178 cooling-maps {
3179 map0 {
3180 trip = <&cpu7_right_alert0>;
3181 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3182 };
3183 };
3184 };
3185
3186 cpuss0-thermal {
3187 thermal-sensors = <&tsens0 7>;
3188
3189 trips {
3190 cpuss0-crit {
3191 temperature = <125000>;
3192 hysteresis = <0>;
3193 type = "critical";
3194 };
3195 };
3196 };
3197
3198 cpuss1-thermal {
3199 thermal-sensors = <&tsens0 8>;
3200
3201 trips {
3202 cpuss1-crit {
3203 temperature = <125000>;
3204 hysteresis = <0>;
3205 type = "critical";
3206 };
3207 };
3208 };
3209
3210 cwlan-thermal {
3211 thermal-sensors = <&tsens1 1>;
3212
3213 trips {
3214 cwlan-crit {
3215 temperature = <125000>;
3216 hysteresis = <0>;
3217 type = "critical";
3218 };
3219 };
3220 };
3221
3222 ddr-thermal {
3223 thermal-sensors = <&tsens1 3>;
3224
3225 trips {
3226 ddr-crit {
3227 temperature = <125000>;
3228 hysteresis = <0>;
3229 type = "critical";
3230 };
3231 };
3232 };
3233
3234 gpuss0-thermal {
3235 polling-delay-passive = <250>;
3236
3237 thermal-sensors = <&tsens0 13>;
3238
3239 trips {
3240 gpuss0_alert0: trip-point0 {
3241 temperature = <85000>;
3242 hysteresis = <2000>;
3243 type = "passive";
3244 };
3245
3246 gpuss0-crit {
3247 temperature = <110000>;
3248 hysteresis = <1000>;
3249 type = "critical";
3250 };
3251 };
3252
3253 cooling-maps {
3254 map0 {
3255 trip = <&gpuss0_alert0>;
3256 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3257 };
3258 };
3259 };
3260
3261 gpuss1-thermal {
3262 polling-delay-passive = <250>;
3263
3264 thermal-sensors = <&tsens0 14>;
3265
3266 trips {
3267 gpuss1_alert0: trip-point0 {
3268 temperature = <85000>;
3269 hysteresis = <2000>;
3270 type = "passive";
3271 };
3272
3273 gpuss1-crit {
3274 temperature = <110000>;
3275 hysteresis = <1000>;
3276 type = "critical";
3277 };
3278 };
3279
3280 cooling-maps {
3281 map0 {
3282 trip = <&gpuss1_alert0>;
3283 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3284 };
3285 };
3286 };
3287
3288 modem-core0-thermal {
3289 thermal-sensors = <&tsens1 6>;
3290
3291 trips {
3292 modem-core0-crit {
3293 temperature = <125000>;
3294 hysteresis = <0>;
3295 type = "critical";
3296 };
3297 };
3298 };
3299
3300 modem-core1-thermal {
3301 thermal-sensors = <&tsens1 7>;
3302
3303 trips {
3304 modem-core1-crit {
3305 temperature = <125000>;
3306 hysteresis = <0>;
3307 type = "critical";
3308 };
3309 };
3310 };
3311
3312 modem-scl-thermal {
3313 thermal-sensors = <&tsens1 9>;
3314
3315 trips {
3316 modem-scl-crit {
3317 temperature = <125000>;
3318 hysteresis = <0>;
3319 type = "critical";
3320 };
3321 };
3322 };
3323
3324 modem-vec-thermal {
3325 thermal-sensors = <&tsens1 8>;
3326
3327 trips {
3328 modem-vec-crit {
3329 temperature = <125000>;
3330 hysteresis = <0>;
3331 type = "critical";
3332 };
3333 };
3334 };
3335
3336 npu-thermal {
3337 thermal-sensors = <&tsens1 10>;
3338
3339 trips {
3340 npu-crit {
3341 temperature = <125000>;
3342 hysteresis = <0>;
3343 type = "critical";
3344 };
3345 };
3346 };
3347
3348 q6-hvx-thermal {
3349 thermal-sensors = <&tsens1 4>;
3350
3351 trips {
3352 q6-hvx-crit {
3353 temperature = <125000>;
3354 hysteresis = <0>;
3355 type = "critical";
3356 };
3357 };
3358 };
3359
3360 video-thermal {
3361 thermal-sensors = <&tsens1 11>;
3362
3363 trips {
3364 video-crit {
3365 temperature = <125000>;
3366 hysteresis = <0>;
3367 type = "critical";
3368 };
3369 };
3370 };
3371 };
3372
3373 timer {
3374 compatible = "arm,armv8-timer";
3375 clock-frequency = <19200000>;
3376 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3377 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3378 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3379 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3380 };
3381 };
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