1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
5 */
6
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/thermal/thermal.h>
21
22 / {
23 interrupt-parent = <&intc>;
24
25 #address-cells = <2>;
26 #size-cells = <2>;
27
28 chosen { };
29
30 clocks {
31 xo_board: xo-board {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <38400000>;
35 clock-output-names = "xo_board";
36 };
37
38 sleep_clk: sleep-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <32764>;
42 clock-output-names = "sleep_clk";
43 };
44 };
45
46 cpus {
47 #address-cells = <2>;
48 #size-cells = <0>;
49
50 CPU0: cpu@0 {
51 device_type = "cpu";
52 compatible = "qcom,kryo485";
53 reg = <0x0 0x0>;
54 clocks = <&cpufreq_hw 0>;
55 enable-method = "psci";
56 capacity-dmips-mhz = <488>;
57 dynamic-power-coefficient = <232>;
58 next-level-cache = <&L2_0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 operating-points-v2 = <&cpu0_opp_table>;
61 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
62 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
63 power-domains = <&CPU_PD0>;
64 power-domain-names = "psci";
65 #cooling-cells = <2>;
66 L2_0: l2-cache {
67 compatible = "cache";
68 cache-level = <2>;
69 cache-unified;
70 next-level-cache = <&L3_0>;
71 L3_0: l3-cache {
72 compatible = "cache";
73 cache-level = <3>;
74 cache-unified;
75 };
76 };
77 };
78
79 CPU1: cpu@100 {
80 device_type = "cpu";
81 compatible = "qcom,kryo485";
82 reg = <0x0 0x100>;
83 clocks = <&cpufreq_hw 0>;
84 enable-method = "psci";
85 capacity-dmips-mhz = <488>;
86 dynamic-power-coefficient = <232>;
87 next-level-cache = <&L2_100>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
89 operating-points-v2 = <&cpu0_opp_table>;
90 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
91 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
92 power-domains = <&CPU_PD1>;
93 power-domain-names = "psci";
94 #cooling-cells = <2>;
95 L2_100: l2-cache {
96 compatible = "cache";
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
100 };
101 };
102
103 CPU2: cpu@200 {
104 device_type = "cpu";
105 compatible = "qcom,kryo485";
106 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw 0>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <488>;
110 dynamic-power-coefficient = <232>;
111 next-level-cache = <&L2_200>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
114 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
116 power-domains = <&CPU_PD2>;
117 power-domain-names = "psci";
118 #cooling-cells = <2>;
119 L2_200: l2-cache {
120 compatible = "cache";
121 cache-level = <2>;
122 cache-unified;
123 next-level-cache = <&L3_0>;
124 };
125 };
126
127 CPU3: cpu@300 {
128 device_type = "cpu";
129 compatible = "qcom,kryo485";
130 reg = <0x0 0x300>;
131 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci";
133 capacity-dmips-mhz = <488>;
134 dynamic-power-coefficient = <232>;
135 next-level-cache = <&L2_300>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
137 operating-points-v2 = <&cpu0_opp_table>;
138 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
140 power-domains = <&CPU_PD3>;
141 power-domain-names = "psci";
142 #cooling-cells = <2>;
143 L2_300: l2-cache {
144 compatible = "cache";
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
148 };
149 };
150
151 CPU4: cpu@400 {
152 device_type = "cpu";
153 compatible = "qcom,kryo485";
154 reg = <0x0 0x400>;
155 clocks = <&cpufreq_hw 1>;
156 enable-method = "psci";
157 capacity-dmips-mhz = <1024>;
158 dynamic-power-coefficient = <369>;
159 next-level-cache = <&L2_400>;
160 qcom,freq-domain = <&cpufreq_hw 1>;
161 operating-points-v2 = <&cpu4_opp_table>;
162 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
163 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
164 power-domains = <&CPU_PD4>;
165 power-domain-names = "psci";
166 #cooling-cells = <2>;
167 L2_400: l2-cache {
168 compatible = "cache";
169 cache-level = <2>;
170 cache-unified;
171 next-level-cache = <&L3_0>;
172 };
173 };
174
175 CPU5: cpu@500 {
176 device_type = "cpu";
177 compatible = "qcom,kryo485";
178 reg = <0x0 0x500>;
179 clocks = <&cpufreq_hw 1>;
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
182 dynamic-power-coefficient = <369>;
183 next-level-cache = <&L2_500>;
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 operating-points-v2 = <&cpu4_opp_table>;
186 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
188 power-domains = <&CPU_PD5>;
189 power-domain-names = "psci";
190 #cooling-cells = <2>;
191 L2_500: l2-cache {
192 compatible = "cache";
193 cache-level = <2>;
194 cache-unified;
195 next-level-cache = <&L3_0>;
196 };
197 };
198
199 CPU6: cpu@600 {
200 device_type = "cpu";
201 compatible = "qcom,kryo485";
202 reg = <0x0 0x600>;
203 clocks = <&cpufreq_hw 1>;
204 enable-method = "psci";
205 capacity-dmips-mhz = <1024>;
206 dynamic-power-coefficient = <369>;
207 next-level-cache = <&L2_600>;
208 qcom,freq-domain = <&cpufreq_hw 1>;
209 operating-points-v2 = <&cpu4_opp_table>;
210 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
211 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
212 power-domains = <&CPU_PD6>;
213 power-domain-names = "psci";
214 #cooling-cells = <2>;
215 L2_600: l2-cache {
216 compatible = "cache";
217 cache-level = <2>;
218 cache-unified;
219 next-level-cache = <&L3_0>;
220 };
221 };
222
223 CPU7: cpu@700 {
224 device_type = "cpu";
225 compatible = "qcom,kryo485";
226 reg = <0x0 0x700>;
227 clocks = <&cpufreq_hw 2>;
228 enable-method = "psci";
229 capacity-dmips-mhz = <1024>;
230 dynamic-power-coefficient = <421>;
231 next-level-cache = <&L2_700>;
232 qcom,freq-domain = <&cpufreq_hw 2>;
233 operating-points-v2 = <&cpu7_opp_table>;
234 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
236 power-domains = <&CPU_PD7>;
237 power-domain-names = "psci";
238 #cooling-cells = <2>;
239 L2_700: l2-cache {
240 compatible = "cache";
241 cache-level = <2>;
242 cache-unified;
243 next-level-cache = <&L3_0>;
244 };
245 };
246
247 cpu-map {
248 cluster0 {
249 core0 {
250 cpu = <&CPU0>;
251 };
252
253 core1 {
254 cpu = <&CPU1>;
255 };
256
257 core2 {
258 cpu = <&CPU2>;
259 };
260
261 core3 {
262 cpu = <&CPU3>;
263 };
264
265 core4 {
266 cpu = <&CPU4>;
267 };
268
269 core5 {
270 cpu = <&CPU5>;
271 };
272
273 core6 {
274 cpu = <&CPU6>;
275 };
276
277 core7 {
278 cpu = <&CPU7>;
279 };
280 };
281 };
282
283 idle-states {
284 entry-method = "psci";
285
286 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
287 compatible = "arm,idle-state";
288 idle-state-name = "little-rail-power-collapse";
289 arm,psci-suspend-param = <0x40000004>;
290 entry-latency-us = <355>;
291 exit-latency-us = <909>;
292 min-residency-us = <3934>;
293 local-timer-stop;
294 };
295
296 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
297 compatible = "arm,idle-state";
298 idle-state-name = "big-rail-power-collapse";
299 arm,psci-suspend-param = <0x40000004>;
300 entry-latency-us = <241>;
301 exit-latency-us = <1461>;
302 min-residency-us = <4488>;
303 local-timer-stop;
304 };
305 };
306
307 domain-idle-states {
308 CLUSTER_SLEEP_0: cluster-sleep-0 {
309 compatible = "domain-idle-state";
310 arm,psci-suspend-param = <0x4100c244>;
311 entry-latency-us = <3263>;
312 exit-latency-us = <6562>;
313 min-residency-us = <9987>;
314 };
315 };
316 };
317
318 cpu0_opp_table: opp-table-cpu0 {
319 compatible = "operating-points-v2";
320 opp-shared;
321
322 cpu0_opp1: opp-300000000 {
323 opp-hz = /bits/ 64 <300000000>;
324 opp-peak-kBps = <800000 9600000>;
325 };
326
327 cpu0_opp2: opp-403200000 {
328 opp-hz = /bits/ 64 <403200000>;
329 opp-peak-kBps = <800000 9600000>;
330 };
331
332 cpu0_opp3: opp-499200000 {
333 opp-hz = /bits/ 64 <499200000>;
334 opp-peak-kBps = <800000 12902400>;
335 };
336
337 cpu0_opp4: opp-576000000 {
338 opp-hz = /bits/ 64 <576000000>;
339 opp-peak-kBps = <800000 12902400>;
340 };
341
342 cpu0_opp5: opp-672000000 {
343 opp-hz = /bits/ 64 <672000000>;
344 opp-peak-kBps = <800000 15974400>;
345 };
346
347 cpu0_opp6: opp-768000000 {
348 opp-hz = /bits/ 64 <768000000>;
349 opp-peak-kBps = <1804000 19660800>;
350 };
351
352 cpu0_opp7: opp-844800000 {
353 opp-hz = /bits/ 64 <844800000>;
354 opp-peak-kBps = <1804000 19660800>;
355 };
356
357 cpu0_opp8: opp-940800000 {
358 opp-hz = /bits/ 64 <940800000>;
359 opp-peak-kBps = <1804000 22732800>;
360 };
361
362 cpu0_opp9: opp-1036800000 {
363 opp-hz = /bits/ 64 <1036800000>;
364 opp-peak-kBps = <1804000 22732800>;
365 };
366
367 cpu0_opp10: opp-1113600000 {
368 opp-hz = /bits/ 64 <1113600000>;
369 opp-peak-kBps = <2188000 25804800>;
370 };
371
372 cpu0_opp11: opp-1209600000 {
373 opp-hz = /bits/ 64 <1209600000>;
374 opp-peak-kBps = <2188000 31948800>;
375 };
376
377 cpu0_opp12: opp-1305600000 {
378 opp-hz = /bits/ 64 <1305600000>;
379 opp-peak-kBps = <3072000 31948800>;
380 };
381
382 cpu0_opp13: opp-1382400000 {
383 opp-hz = /bits/ 64 <1382400000>;
384 opp-peak-kBps = <3072000 31948800>;
385 };
386
387 cpu0_opp14: opp-1478400000 {
388 opp-hz = /bits/ 64 <1478400000>;
389 opp-peak-kBps = <3072000 31948800>;
390 };
391
392 cpu0_opp15: opp-1555200000 {
393 opp-hz = /bits/ 64 <1555200000>;
394 opp-peak-kBps = <3072000 40550400>;
395 };
396
397 cpu0_opp16: opp-1632000000 {
398 opp-hz = /bits/ 64 <1632000000>;
399 opp-peak-kBps = <3072000 40550400>;
400 };
401
402 cpu0_opp17: opp-1708800000 {
403 opp-hz = /bits/ 64 <1708800000>;
404 opp-peak-kBps = <3072000 43008000>;
405 };
406
407 cpu0_opp18: opp-1785600000 {
408 opp-hz = /bits/ 64 <1785600000>;
409 opp-peak-kBps = <3072000 43008000>;
410 };
411 };
412
413 cpu4_opp_table: opp-table-cpu4 {
414 compatible = "operating-points-v2";
415 opp-shared;
416
417 cpu4_opp1: opp-710400000 {
418 opp-hz = /bits/ 64 <710400000>;
419 opp-peak-kBps = <1804000 15974400>;
420 };
421
422 cpu4_opp2: opp-825600000 {
423 opp-hz = /bits/ 64 <825600000>;
424 opp-peak-kBps = <2188000 19660800>;
425 };
426
427 cpu4_opp3: opp-940800000 {
428 opp-hz = /bits/ 64 <940800000>;
429 opp-peak-kBps = <2188000 22732800>;
430 };
431
432 cpu4_opp4: opp-1056000000 {
433 opp-hz = /bits/ 64 <1056000000>;
434 opp-peak-kBps = <3072000 25804800>;
435 };
436
437 cpu4_opp5: opp-1171200000 {
438 opp-hz = /bits/ 64 <1171200000>;
439 opp-peak-kBps = <3072000 31948800>;
440 };
441
442 cpu4_opp6: opp-1286400000 {
443 opp-hz = /bits/ 64 <1286400000>;
444 opp-peak-kBps = <4068000 31948800>;
445 };
446
447 cpu4_opp7: opp-1401600000 {
448 opp-hz = /bits/ 64 <1401600000>;
449 opp-peak-kBps = <4068000 31948800>;
450 };
451
452 cpu4_opp8: opp-1497600000 {
453 opp-hz = /bits/ 64 <1497600000>;
454 opp-peak-kBps = <4068000 40550400>;
455 };
456
457 cpu4_opp9: opp-1612800000 {
458 opp-hz = /bits/ 64 <1612800000>;
459 opp-peak-kBps = <4068000 40550400>;
460 };
461
462 cpu4_opp10: opp-1708800000 {
463 opp-hz = /bits/ 64 <1708800000>;
464 opp-peak-kBps = <4068000 43008000>;
465 };
466
467 cpu4_opp11: opp-1804800000 {
468 opp-hz = /bits/ 64 <1804800000>;
469 opp-peak-kBps = <6220000 43008000>;
470 };
471
472 cpu4_opp12: opp-1920000000 {
473 opp-hz = /bits/ 64 <1920000000>;
474 opp-peak-kBps = <6220000 49152000>;
475 };
476
477 cpu4_opp13: opp-2016000000 {
478 opp-hz = /bits/ 64 <2016000000>;
479 opp-peak-kBps = <7216000 49152000>;
480 };
481
482 cpu4_opp14: opp-2131200000 {
483 opp-hz = /bits/ 64 <2131200000>;
484 opp-peak-kBps = <8368000 49152000>;
485 };
486
487 cpu4_opp15: opp-2227200000 {
488 opp-hz = /bits/ 64 <2227200000>;
489 opp-peak-kBps = <8368000 51609600>;
490 };
491
492 cpu4_opp16: opp-2323200000 {
493 opp-hz = /bits/ 64 <2323200000>;
494 opp-peak-kBps = <8368000 51609600>;
495 };
496
497 cpu4_opp17: opp-2419200000 {
498 opp-hz = /bits/ 64 <2419200000>;
499 opp-peak-kBps = <8368000 51609600>;
500 };
501 };
502
503 cpu7_opp_table: opp-table-cpu7 {
504 compatible = "operating-points-v2";
505 opp-shared;
506
507 cpu7_opp1: opp-825600000 {
508 opp-hz = /bits/ 64 <825600000>;
509 opp-peak-kBps = <2188000 19660800>;
510 };
511
512 cpu7_opp2: opp-940800000 {
513 opp-hz = /bits/ 64 <940800000>;
514 opp-peak-kBps = <2188000 22732800>;
515 };
516
517 cpu7_opp3: opp-1056000000 {
518 opp-hz = /bits/ 64 <1056000000>;
519 opp-peak-kBps = <3072000 25804800>;
520 };
521
522 cpu7_opp4: opp-1171200000 {
523 opp-hz = /bits/ 64 <1171200000>;
524 opp-peak-kBps = <3072000 31948800>;
525 };
526
527 cpu7_opp5: opp-1286400000 {
528 opp-hz = /bits/ 64 <1286400000>;
529 opp-peak-kBps = <4068000 31948800>;
530 };
531
532 cpu7_opp6: opp-1401600000 {
533 opp-hz = /bits/ 64 <1401600000>;
534 opp-peak-kBps = <4068000 31948800>;
535 };
536
537 cpu7_opp7: opp-1497600000 {
538 opp-hz = /bits/ 64 <1497600000>;
539 opp-peak-kBps = <4068000 40550400>;
540 };
541
542 cpu7_opp8: opp-1612800000 {
543 opp-hz = /bits/ 64 <1612800000>;
544 opp-peak-kBps = <4068000 40550400>;
545 };
546
547 cpu7_opp9: opp-1708800000 {
548 opp-hz = /bits/ 64 <1708800000>;
549 opp-peak-kBps = <4068000 43008000>;
550 };
551
552 cpu7_opp10: opp-1804800000 {
553 opp-hz = /bits/ 64 <1804800000>;
554 opp-peak-kBps = <6220000 43008000>;
555 };
556
557 cpu7_opp11: opp-1920000000 {
558 opp-hz = /bits/ 64 <1920000000>;
559 opp-peak-kBps = <6220000 49152000>;
560 };
561
562 cpu7_opp12: opp-2016000000 {
563 opp-hz = /bits/ 64 <2016000000>;
564 opp-peak-kBps = <7216000 49152000>;
565 };
566
567 cpu7_opp13: opp-2131200000 {
568 opp-hz = /bits/ 64 <2131200000>;
569 opp-peak-kBps = <8368000 49152000>;
570 };
571
572 cpu7_opp14: opp-2227200000 {
573 opp-hz = /bits/ 64 <2227200000>;
574 opp-peak-kBps = <8368000 51609600>;
575 };
576
577 cpu7_opp15: opp-2323200000 {
578 opp-hz = /bits/ 64 <2323200000>;
579 opp-peak-kBps = <8368000 51609600>;
580 };
581
582 cpu7_opp16: opp-2419200000 {
583 opp-hz = /bits/ 64 <2419200000>;
584 opp-peak-kBps = <8368000 51609600>;
585 };
586
587 cpu7_opp17: opp-2534400000 {
588 opp-hz = /bits/ 64 <2534400000>;
589 opp-peak-kBps = <8368000 51609600>;
590 };
591
592 cpu7_opp18: opp-2649600000 {
593 opp-hz = /bits/ 64 <2649600000>;
594 opp-peak-kBps = <8368000 51609600>;
595 };
596
597 cpu7_opp19: opp-2745600000 {
598 opp-hz = /bits/ 64 <2745600000>;
599 opp-peak-kBps = <8368000 51609600>;
600 };
601
602 cpu7_opp20: opp-2841600000 {
603 opp-hz = /bits/ 64 <2841600000>;
604 opp-peak-kBps = <8368000 51609600>;
605 };
606 };
607
608 firmware {
609 scm: scm {
610 compatible = "qcom,scm-sm8150", "qcom,scm";
611 #reset-cells = <1>;
612 };
613 };
614
615 memory@80000000 {
616 device_type = "memory";
617 /* We expect the bootloader to fill in the size */
618 reg = <0x0 0x80000000 0x0 0x0>;
619 };
620
621 pmu {
622 compatible = "arm,armv8-pmuv3";
623 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
624 };
625
626 psci {
627 compatible = "arm,psci-1.0";
628 method = "smc";
629
630 CPU_PD0: power-domain-cpu0 {
631 #power-domain-cells = <0>;
632 power-domains = <&CLUSTER_PD>;
633 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
634 };
635
636 CPU_PD1: power-domain-cpu1 {
637 #power-domain-cells = <0>;
638 power-domains = <&CLUSTER_PD>;
639 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
640 };
641
642 CPU_PD2: power-domain-cpu2 {
643 #power-domain-cells = <0>;
644 power-domains = <&CLUSTER_PD>;
645 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
646 };
647
648 CPU_PD3: power-domain-cpu3 {
649 #power-domain-cells = <0>;
650 power-domains = <&CLUSTER_PD>;
651 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
652 };
653
654 CPU_PD4: power-domain-cpu4 {
655 #power-domain-cells = <0>;
656 power-domains = <&CLUSTER_PD>;
657 domain-idle-states = <&BIG_CPU_SLEEP_0>;
658 };
659
660 CPU_PD5: power-domain-cpu5 {
661 #power-domain-cells = <0>;
662 power-domains = <&CLUSTER_PD>;
663 domain-idle-states = <&BIG_CPU_SLEEP_0>;
664 };
665
666 CPU_PD6: power-domain-cpu6 {
667 #power-domain-cells = <0>;
668 power-domains = <&CLUSTER_PD>;
669 domain-idle-states = <&BIG_CPU_SLEEP_0>;
670 };
671
672 CPU_PD7: power-domain-cpu7 {
673 #power-domain-cells = <0>;
674 power-domains = <&CLUSTER_PD>;
675 domain-idle-states = <&BIG_CPU_SLEEP_0>;
676 };
677
678 CLUSTER_PD: power-domain-cpu-cluster0 {
679 #power-domain-cells = <0>;
680 domain-idle-states = <&CLUSTER_SLEEP_0>;
681 };
682 };
683
684 reserved-memory {
685 #address-cells = <2>;
686 #size-cells = <2>;
687 ranges;
688
689 hyp_mem: memory@85700000 {
690 reg = <0x0 0x85700000 0x0 0x600000>;
691 no-map;
692 };
693
694 xbl_mem: memory@85d00000 {
695 reg = <0x0 0x85d00000 0x0 0x140000>;
696 no-map;
697 };
698
699 aop_mem: memory@85f00000 {
700 reg = <0x0 0x85f00000 0x0 0x20000>;
701 no-map;
702 };
703
704 aop_cmd_db: memory@85f20000 {
705 compatible = "qcom,cmd-db";
706 reg = <0x0 0x85f20000 0x0 0x20000>;
707 no-map;
708 };
709
710 smem_mem: memory@86000000 {
711 reg = <0x0 0x86000000 0x0 0x200000>;
712 no-map;
713 };
714
715 tz_mem: memory@86200000 {
716 reg = <0x0 0x86200000 0x0 0x3900000>;
717 no-map;
718 };
719
720 rmtfs_mem: memory@89b00000 {
721 compatible = "qcom,rmtfs-mem";
722 reg = <0x0 0x89b00000 0x0 0x200000>;
723 no-map;
724
725 qcom,client-id = <1>;
726 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
727 };
728
729 camera_mem: memory@8b700000 {
730 reg = <0x0 0x8b700000 0x0 0x500000>;
731 no-map;
732 };
733
734 wlan_mem: memory@8bc00000 {
735 reg = <0x0 0x8bc00000 0x0 0x180000>;
736 no-map;
737 };
738
739 npu_mem: memory@8bd80000 {
740 reg = <0x0 0x8bd80000 0x0 0x80000>;
741 no-map;
742 };
743
744 adsp_mem: memory@8be00000 {
745 reg = <0x0 0x8be00000 0x0 0x1a00000>;
746 no-map;
747 };
748
749 mpss_mem: memory@8d800000 {
750 reg = <0x0 0x8d800000 0x0 0x9600000>;
751 no-map;
752 };
753
754 venus_mem: memory@96e00000 {
755 reg = <0x0 0x96e00000 0x0 0x500000>;
756 no-map;
757 };
758
759 slpi_mem: memory@97300000 {
760 reg = <0x0 0x97300000 0x0 0x1400000>;
761 no-map;
762 };
763
764 ipa_fw_mem: memory@98700000 {
765 reg = <0x0 0x98700000 0x0 0x10000>;
766 no-map;
767 };
768
769 ipa_gsi_mem: memory@98710000 {
770 reg = <0x0 0x98710000 0x0 0x5000>;
771 no-map;
772 };
773
774 gpu_mem: memory@98715000 {
775 reg = <0x0 0x98715000 0x0 0x2000>;
776 no-map;
777 };
778
779 spss_mem: memory@98800000 {
780 reg = <0x0 0x98800000 0x0 0x100000>;
781 no-map;
782 };
783
784 cdsp_mem: memory@98900000 {
785 reg = <0x0 0x98900000 0x0 0x1400000>;
786 no-map;
787 };
788
789 qseecom_mem: memory@9e400000 {
790 reg = <0x0 0x9e400000 0x0 0x1400000>;
791 no-map;
792 };
793 };
794
795 smem {
796 compatible = "qcom,smem";
797 memory-region = <&smem_mem>;
798 hwlocks = <&tcsr_mutex 3>;
799 };
800
801 smp2p-cdsp {
802 compatible = "qcom,smp2p";
803 qcom,smem = <94>, <432>;
804
805 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
806
807 mboxes = <&apss_shared 6>;
808
809 qcom,local-pid = <0>;
810 qcom,remote-pid = <5>;
811
812 cdsp_smp2p_out: master-kernel {
813 qcom,entry-name = "master-kernel";
814 #qcom,smem-state-cells = <1>;
815 };
816
817 cdsp_smp2p_in: slave-kernel {
818 qcom,entry-name = "slave-kernel";
819
820 interrupt-controller;
821 #interrupt-cells = <2>;
822 };
823 };
824
825 smp2p-lpass {
826 compatible = "qcom,smp2p";
827 qcom,smem = <443>, <429>;
828
829 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
830
831 mboxes = <&apss_shared 10>;
832
833 qcom,local-pid = <0>;
834 qcom,remote-pid = <2>;
835
836 adsp_smp2p_out: master-kernel {
837 qcom,entry-name = "master-kernel";
838 #qcom,smem-state-cells = <1>;
839 };
840
841 adsp_smp2p_in: slave-kernel {
842 qcom,entry-name = "slave-kernel";
843
844 interrupt-controller;
845 #interrupt-cells = <2>;
846 };
847 };
848
849 smp2p-mpss {
850 compatible = "qcom,smp2p";
851 qcom,smem = <435>, <428>;
852
853 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
854
855 mboxes = <&apss_shared 14>;
856
857 qcom,local-pid = <0>;
858 qcom,remote-pid = <1>;
859
860 modem_smp2p_out: master-kernel {
861 qcom,entry-name = "master-kernel";
862 #qcom,smem-state-cells = <1>;
863 };
864
865 modem_smp2p_in: slave-kernel {
866 qcom,entry-name = "slave-kernel";
867
868 interrupt-controller;
869 #interrupt-cells = <2>;
870 };
871 };
872
873 smp2p-slpi {
874 compatible = "qcom,smp2p";
875 qcom,smem = <481>, <430>;
876
877 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
878
879 mboxes = <&apss_shared 26>;
880
881 qcom,local-pid = <0>;
882 qcom,remote-pid = <3>;
883
884 slpi_smp2p_out: master-kernel {
885 qcom,entry-name = "master-kernel";
886 #qcom,smem-state-cells = <1>;
887 };
888
889 slpi_smp2p_in: slave-kernel {
890 qcom,entry-name = "slave-kernel";
891
892 interrupt-controller;
893 #interrupt-cells = <2>;
894 };
895 };
896
897 soc: soc@0 {
898 #address-cells = <2>;
899 #size-cells = <2>;
900 ranges = <0 0 0 0 0x10 0>;
901 dma-ranges = <0 0 0 0 0x10 0>;
902 compatible = "simple-bus";
903
904 gcc: clock-controller@100000 {
905 compatible = "qcom,gcc-sm8150";
906 reg = <0x0 0x00100000 0x0 0x1f0000>;
907 #clock-cells = <1>;
908 #reset-cells = <1>;
909 #power-domain-cells = <1>;
910 clock-names = "bi_tcxo",
911 "sleep_clk";
912 clocks = <&rpmhcc RPMH_CXO_CLK>,
913 <&sleep_clk>;
914 };
915
916 gpi_dma0: dma-controller@800000 {
917 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
918 reg = <0 0x00800000 0 0x60000>;
919 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
932 dma-channels = <13>;
933 dma-channel-mask = <0xfa>;
934 iommus = <&apps_smmu 0x00d6 0x0>;
935 #dma-cells = <3>;
936 status = "disabled";
937 };
938
939 ethernet: ethernet@20000 {
940 compatible = "qcom,sm8150-ethqos";
941 reg = <0x0 0x00020000 0x0 0x10000>,
942 <0x0 0x00036000 0x0 0x100>;
943 reg-names = "stmmaceth", "rgmii";
944 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
945 clocks = <&gcc GCC_EMAC_AXI_CLK>,
946 <&gcc GCC_EMAC_SLV_AHB_CLK>,
947 <&gcc GCC_EMAC_PTP_CLK>,
948 <&gcc GCC_EMAC_RGMII_CLK>;
949 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
951 interrupt-names = "macirq", "eth_lpi";
952
953 power-domains = <&gcc EMAC_GDSC>;
954 resets = <&gcc GCC_EMAC_BCR>;
955
956 iommus = <&apps_smmu 0x3c0 0x0>;
957
958 snps,tso;
959 rx-fifo-depth = <4096>;
960 tx-fifo-depth = <4096>;
961
962 status = "disabled";
963 };
964
965 qfprom: efuse@784000 {
966 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
967 reg = <0 0x00784000 0 0x8ff>;
968 #address-cells = <1>;
969 #size-cells = <1>;
970
971 gpu_speed_bin: gpu-speed-bin@133 {
972 reg = <0x133 0x1>;
973 bits = <5 3>;
974 };
975 };
976
977 qupv3_id_0: geniqup@8c0000 {
978 compatible = "qcom,geni-se-qup";
979 reg = <0x0 0x008c0000 0x0 0x6000>;
980 clock-names = "m-ahb", "s-ahb";
981 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
982 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
983 iommus = <&apps_smmu 0xc3 0x0>;
984 #address-cells = <2>;
985 #size-cells = <2>;
986 ranges;
987 status = "disabled";
988
989 i2c0: i2c@880000 {
990 compatible = "qcom,geni-i2c";
991 reg = <0 0x00880000 0 0x4000>;
992 clock-names = "se";
993 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
994 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
995 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
996 dma-names = "tx", "rx";
997 pinctrl-names = "default";
998 pinctrl-0 = <&qup_i2c0_default>;
999 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 status = "disabled";
1003 };
1004
1005 spi0: spi@880000 {
1006 compatible = "qcom,geni-spi";
1007 reg = <0 0x00880000 0 0x4000>;
1008 reg-names = "se";
1009 clock-names = "se";
1010 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1012 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1013 dma-names = "tx", "rx";
1014 pinctrl-names = "default";
1015 pinctrl-0 = <&qup_spi0_default>;
1016 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1017 spi-max-frequency = <50000000>;
1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 status = "disabled";
1021 };
1022
1023 i2c1: i2c@884000 {
1024 compatible = "qcom,geni-i2c";
1025 reg = <0 0x00884000 0 0x4000>;
1026 clock-names = "se";
1027 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1029 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1030 dma-names = "tx", "rx";
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&qup_i2c1_default>;
1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 status = "disabled";
1037 };
1038
1039 spi1: spi@884000 {
1040 compatible = "qcom,geni-spi";
1041 reg = <0 0x00884000 0 0x4000>;
1042 reg-names = "se";
1043 clock-names = "se";
1044 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1045 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1046 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1047 dma-names = "tx", "rx";
1048 pinctrl-names = "default";
1049 pinctrl-0 = <&qup_spi1_default>;
1050 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1051 spi-max-frequency = <50000000>;
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 status = "disabled";
1055 };
1056
1057 i2c2: i2c@888000 {
1058 compatible = "qcom,geni-i2c";
1059 reg = <0 0x00888000 0 0x4000>;
1060 clock-names = "se";
1061 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1062 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1063 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1064 dma-names = "tx", "rx";
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&qup_i2c2_default>;
1067 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 status = "disabled";
1071 };
1072
1073 spi2: spi@888000 {
1074 compatible = "qcom,geni-spi";
1075 reg = <0 0x00888000 0 0x4000>;
1076 reg-names = "se";
1077 clock-names = "se";
1078 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1079 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1080 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1081 dma-names = "tx", "rx";
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&qup_spi2_default>;
1084 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1085 spi-max-frequency = <50000000>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088 status = "disabled";
1089 };
1090
1091 i2c3: i2c@88c000 {
1092 compatible = "qcom,geni-i2c";
1093 reg = <0 0x0088c000 0 0x4000>;
1094 clock-names = "se";
1095 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1096 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1097 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1098 dma-names = "tx", "rx";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&qup_i2c3_default>;
1101 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 status = "disabled";
1105 };
1106
1107 spi3: spi@88c000 {
1108 compatible = "qcom,geni-spi";
1109 reg = <0 0x0088c000 0 0x4000>;
1110 reg-names = "se";
1111 clock-names = "se";
1112 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1113 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1114 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1115 dma-names = "tx", "rx";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_spi3_default>;
1118 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1119 spi-max-frequency = <50000000>;
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 status = "disabled";
1123 };
1124
1125 i2c4: i2c@890000 {
1126 compatible = "qcom,geni-i2c";
1127 reg = <0 0x00890000 0 0x4000>;
1128 clock-names = "se";
1129 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1130 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1131 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1132 dma-names = "tx", "rx";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_i2c4_default>;
1135 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 status = "disabled";
1139 };
1140
1141 spi4: spi@890000 {
1142 compatible = "qcom,geni-spi";
1143 reg = <0 0x00890000 0 0x4000>;
1144 reg-names = "se";
1145 clock-names = "se";
1146 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1147 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1148 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1149 dma-names = "tx", "rx";
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&qup_spi4_default>;
1152 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1153 spi-max-frequency = <50000000>;
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1156 status = "disabled";
1157 };
1158
1159 i2c5: i2c@894000 {
1160 compatible = "qcom,geni-i2c";
1161 reg = <0 0x00894000 0 0x4000>;
1162 clock-names = "se";
1163 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1164 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1165 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1166 dma-names = "tx", "rx";
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&qup_i2c5_default>;
1169 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 status = "disabled";
1173 };
1174
1175 spi5: spi@894000 {
1176 compatible = "qcom,geni-spi";
1177 reg = <0 0x00894000 0 0x4000>;
1178 reg-names = "se";
1179 clock-names = "se";
1180 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1181 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1182 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1183 dma-names = "tx", "rx";
1184 pinctrl-names = "default";
1185 pinctrl-0 = <&qup_spi5_default>;
1186 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1187 spi-max-frequency = <50000000>;
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190 status = "disabled";
1191 };
1192
1193 i2c6: i2c@898000 {
1194 compatible = "qcom,geni-i2c";
1195 reg = <0 0x00898000 0 0x4000>;
1196 clock-names = "se";
1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1198 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1199 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1200 dma-names = "tx", "rx";
1201 pinctrl-names = "default";
1202 pinctrl-0 = <&qup_i2c6_default>;
1203 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 status = "disabled";
1207 };
1208
1209 spi6: spi@898000 {
1210 compatible = "qcom,geni-spi";
1211 reg = <0 0x00898000 0 0x4000>;
1212 reg-names = "se";
1213 clock-names = "se";
1214 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1215 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1216 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1217 dma-names = "tx", "rx";
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&qup_spi6_default>;
1220 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1221 spi-max-frequency = <50000000>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 status = "disabled";
1225 };
1226
1227 i2c7: i2c@89c000 {
1228 compatible = "qcom,geni-i2c";
1229 reg = <0 0x0089c000 0 0x4000>;
1230 clock-names = "se";
1231 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1232 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1233 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1234 dma-names = "tx", "rx";
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&qup_i2c7_default>;
1237 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 status = "disabled";
1241 };
1242
1243 spi7: spi@89c000 {
1244 compatible = "qcom,geni-spi";
1245 reg = <0 0x0089c000 0 0x4000>;
1246 reg-names = "se";
1247 clock-names = "se";
1248 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1249 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1250 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1251 dma-names = "tx", "rx";
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&qup_spi7_default>;
1254 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1255 spi-max-frequency = <50000000>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1258 status = "disabled";
1259 };
1260 };
1261
1262 gpi_dma1: dma-controller@a00000 {
1263 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1264 reg = <0 0x00a00000 0 0x60000>;
1265 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1278 dma-channels = <13>;
1279 dma-channel-mask = <0xfa>;
1280 iommus = <&apps_smmu 0x0616 0x0>;
1281 #dma-cells = <3>;
1282 status = "disabled";
1283 };
1284
1285 qupv3_id_1: geniqup@ac0000 {
1286 compatible = "qcom,geni-se-qup";
1287 reg = <0x0 0x00ac0000 0x0 0x6000>;
1288 clock-names = "m-ahb", "s-ahb";
1289 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1290 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1291 iommus = <&apps_smmu 0x603 0x0>;
1292 #address-cells = <2>;
1293 #size-cells = <2>;
1294 ranges;
1295 status = "disabled";
1296
1297 i2c8: i2c@a80000 {
1298 compatible = "qcom,geni-i2c";
1299 reg = <0 0x00a80000 0 0x4000>;
1300 clock-names = "se";
1301 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1302 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1303 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1304 dma-names = "tx", "rx";
1305 pinctrl-names = "default";
1306 pinctrl-0 = <&qup_i2c8_default>;
1307 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 status = "disabled";
1311 };
1312
1313 spi8: spi@a80000 {
1314 compatible = "qcom,geni-spi";
1315 reg = <0 0x00a80000 0 0x4000>;
1316 reg-names = "se";
1317 clock-names = "se";
1318 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1319 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1320 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1321 dma-names = "tx", "rx";
1322 pinctrl-names = "default";
1323 pinctrl-0 = <&qup_spi8_default>;
1324 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1325 spi-max-frequency = <50000000>;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 status = "disabled";
1329 };
1330
1331 i2c9: i2c@a84000 {
1332 compatible = "qcom,geni-i2c";
1333 reg = <0 0x00a84000 0 0x4000>;
1334 clock-names = "se";
1335 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1336 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1337 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1338 dma-names = "tx", "rx";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c9_default>;
1341 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1344 status = "disabled";
1345 };
1346
1347 spi9: spi@a84000 {
1348 compatible = "qcom,geni-spi";
1349 reg = <0 0x00a84000 0 0x4000>;
1350 reg-names = "se";
1351 clock-names = "se";
1352 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1353 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1354 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1355 dma-names = "tx", "rx";
1356 pinctrl-names = "default";
1357 pinctrl-0 = <&qup_spi9_default>;
1358 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1359 spi-max-frequency = <50000000>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1364
1365 uart9: serial@a84000 {
1366 compatible = "qcom,geni-uart";
1367 reg = <0x0 0x00a84000 0x0 0x4000>;
1368 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1369 clock-names = "se";
1370 pinctrl-0 = <&qup_uart9_default>;
1371 pinctrl-names = "default";
1372 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1373 status = "disabled";
1374 };
1375
1376 i2c10: i2c@a88000 {
1377 compatible = "qcom,geni-i2c";
1378 reg = <0 0x00a88000 0 0x4000>;
1379 clock-names = "se";
1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1381 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1382 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1383 dma-names = "tx", "rx";
1384 pinctrl-names = "default";
1385 pinctrl-0 = <&qup_i2c10_default>;
1386 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1387 #address-cells = <1>;
1388 #size-cells = <0>;
1389 status = "disabled";
1390 };
1391
1392 spi10: spi@a88000 {
1393 compatible = "qcom,geni-spi";
1394 reg = <0 0x00a88000 0 0x4000>;
1395 reg-names = "se";
1396 clock-names = "se";
1397 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1398 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1399 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1400 dma-names = "tx", "rx";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_spi10_default>;
1403 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1404 spi-max-frequency = <50000000>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 status = "disabled";
1408 };
1409
1410 i2c11: i2c@a8c000 {
1411 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00a8c000 0 0x4000>;
1413 clock-names = "se";
1414 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1415 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1416 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1417 dma-names = "tx", "rx";
1418 pinctrl-names = "default";
1419 pinctrl-0 = <&qup_i2c11_default>;
1420 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 status = "disabled";
1424 };
1425
1426 spi11: spi@a8c000 {
1427 compatible = "qcom,geni-spi";
1428 reg = <0 0x00a8c000 0 0x4000>;
1429 reg-names = "se";
1430 clock-names = "se";
1431 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1432 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1433 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1434 dma-names = "tx", "rx";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_spi11_default>;
1437 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1438 spi-max-frequency = <50000000>;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1441 status = "disabled";
1442 };
1443
1444 uart2: serial@a90000 {
1445 compatible = "qcom,geni-debug-uart";
1446 reg = <0x0 0x00a90000 0x0 0x4000>;
1447 clock-names = "se";
1448 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1449 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1450 status = "disabled";
1451 };
1452
1453 i2c12: i2c@a90000 {
1454 compatible = "qcom,geni-i2c";
1455 reg = <0 0x00a90000 0 0x4000>;
1456 clock-names = "se";
1457 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1458 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1459 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1460 dma-names = "tx", "rx";
1461 pinctrl-names = "default";
1462 pinctrl-0 = <&qup_i2c12_default>;
1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1466 status = "disabled";
1467 };
1468
1469 spi12: spi@a90000 {
1470 compatible = "qcom,geni-spi";
1471 reg = <0 0x00a90000 0 0x4000>;
1472 reg-names = "se";
1473 clock-names = "se";
1474 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1475 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1476 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1477 dma-names = "tx", "rx";
1478 pinctrl-names = "default";
1479 pinctrl-0 = <&qup_spi12_default>;
1480 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1481 spi-max-frequency = <50000000>;
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1484 status = "disabled";
1485 };
1486
1487 i2c16: i2c@94000 {
1488 compatible = "qcom,geni-i2c";
1489 reg = <0 0x00094000 0 0x4000>;
1490 clock-names = "se";
1491 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1492 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1493 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1494 dma-names = "tx", "rx";
1495 pinctrl-names = "default";
1496 pinctrl-0 = <&qup_i2c16_default>;
1497 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 status = "disabled";
1501 };
1502
1503 spi16: spi@a94000 {
1504 compatible = "qcom,geni-spi";
1505 reg = <0 0x00a94000 0 0x4000>;
1506 reg-names = "se";
1507 clock-names = "se";
1508 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1509 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1510 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1511 dma-names = "tx", "rx";
1512 pinctrl-names = "default";
1513 pinctrl-0 = <&qup_spi16_default>;
1514 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1515 spi-max-frequency = <50000000>;
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1518 status = "disabled";
1519 };
1520 };
1521
1522 gpi_dma2: dma-controller@c00000 {
1523 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1524 reg = <0 0x00c00000 0 0x60000>;
1525 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1538 dma-channels = <13>;
1539 dma-channel-mask = <0xfa>;
1540 iommus = <&apps_smmu 0x07b6 0x0>;
1541 #dma-cells = <3>;
1542 status = "disabled";
1543 };
1544
1545 qupv3_id_2: geniqup@cc0000 {
1546 compatible = "qcom,geni-se-qup";
1547 reg = <0x0 0x00cc0000 0x0 0x6000>;
1548
1549 clock-names = "m-ahb", "s-ahb";
1550 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1551 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1552 iommus = <&apps_smmu 0x7a3 0x0>;
1553 #address-cells = <2>;
1554 #size-cells = <2>;
1555 ranges;
1556 status = "disabled";
1557
1558 i2c17: i2c@c80000 {
1559 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00c80000 0 0x4000>;
1561 clock-names = "se";
1562 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1563 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1564 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1565 dma-names = "tx", "rx";
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&qup_i2c17_default>;
1568 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 status = "disabled";
1572 };
1573
1574 spi17: spi@c80000 {
1575 compatible = "qcom,geni-spi";
1576 reg = <0 0x00c80000 0 0x4000>;
1577 reg-names = "se";
1578 clock-names = "se";
1579 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1580 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1581 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1582 dma-names = "tx", "rx";
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&qup_spi17_default>;
1585 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1586 spi-max-frequency = <50000000>;
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 status = "disabled";
1590 };
1591
1592 i2c18: i2c@c84000 {
1593 compatible = "qcom,geni-i2c";
1594 reg = <0 0x00c84000 0 0x4000>;
1595 clock-names = "se";
1596 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1597 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1598 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1599 dma-names = "tx", "rx";
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_i2c18_default>;
1602 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1605 status = "disabled";
1606 };
1607
1608 spi18: spi@c84000 {
1609 compatible = "qcom,geni-spi";
1610 reg = <0 0x00c84000 0 0x4000>;
1611 reg-names = "se";
1612 clock-names = "se";
1613 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1614 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1615 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1616 dma-names = "tx", "rx";
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&qup_spi18_default>;
1619 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1620 spi-max-frequency = <50000000>;
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1623 status = "disabled";
1624 };
1625
1626 i2c19: i2c@c88000 {
1627 compatible = "qcom,geni-i2c";
1628 reg = <0 0x00c88000 0 0x4000>;
1629 clock-names = "se";
1630 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1631 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1632 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1633 dma-names = "tx", "rx";
1634 pinctrl-names = "default";
1635 pinctrl-0 = <&qup_i2c19_default>;
1636 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639 status = "disabled";
1640 };
1641
1642 spi19: spi@c88000 {
1643 compatible = "qcom,geni-spi";
1644 reg = <0 0x00c88000 0 0x4000>;
1645 reg-names = "se";
1646 clock-names = "se";
1647 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1648 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1649 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1650 dma-names = "tx", "rx";
1651 pinctrl-names = "default";
1652 pinctrl-0 = <&qup_spi19_default>;
1653 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1654 spi-max-frequency = <50000000>;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1657 status = "disabled";
1658 };
1659
1660 i2c13: i2c@c8c000 {
1661 compatible = "qcom,geni-i2c";
1662 reg = <0 0x00c8c000 0 0x4000>;
1663 clock-names = "se";
1664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1665 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1666 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1667 dma-names = "tx", "rx";
1668 pinctrl-names = "default";
1669 pinctrl-0 = <&qup_i2c13_default>;
1670 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1673 status = "disabled";
1674 };
1675
1676 spi13: spi@c8c000 {
1677 compatible = "qcom,geni-spi";
1678 reg = <0 0x00c8c000 0 0x4000>;
1679 reg-names = "se";
1680 clock-names = "se";
1681 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1682 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1683 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1684 dma-names = "tx", "rx";
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&qup_spi13_default>;
1687 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1688 spi-max-frequency = <50000000>;
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1691 status = "disabled";
1692 };
1693
1694 i2c14: i2c@c90000 {
1695 compatible = "qcom,geni-i2c";
1696 reg = <0 0x00c90000 0 0x4000>;
1697 clock-names = "se";
1698 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1699 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1700 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1701 dma-names = "tx", "rx";
1702 pinctrl-names = "default";
1703 pinctrl-0 = <&qup_i2c14_default>;
1704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1705 #address-cells = <1>;
1706 #size-cells = <0>;
1707 status = "disabled";
1708 };
1709
1710 spi14: spi@c90000 {
1711 compatible = "qcom,geni-spi";
1712 reg = <0 0x00c90000 0 0x4000>;
1713 reg-names = "se";
1714 clock-names = "se";
1715 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1716 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1717 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1718 dma-names = "tx", "rx";
1719 pinctrl-names = "default";
1720 pinctrl-0 = <&qup_spi14_default>;
1721 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1722 spi-max-frequency = <50000000>;
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1725 status = "disabled";
1726 };
1727
1728 i2c15: i2c@c94000 {
1729 compatible = "qcom,geni-i2c";
1730 reg = <0 0x00c94000 0 0x4000>;
1731 clock-names = "se";
1732 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1733 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1734 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1735 dma-names = "tx", "rx";
1736 pinctrl-names = "default";
1737 pinctrl-0 = <&qup_i2c15_default>;
1738 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1741 status = "disabled";
1742 };
1743
1744 spi15: spi@c94000 {
1745 compatible = "qcom,geni-spi";
1746 reg = <0 0x00c94000 0 0x4000>;
1747 reg-names = "se";
1748 clock-names = "se";
1749 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1750 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1751 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1752 dma-names = "tx", "rx";
1753 pinctrl-names = "default";
1754 pinctrl-0 = <&qup_spi15_default>;
1755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1756 spi-max-frequency = <50000000>;
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1759 status = "disabled";
1760 };
1761 };
1762
1763 config_noc: interconnect@1500000 {
1764 compatible = "qcom,sm8150-config-noc";
1765 reg = <0 0x01500000 0 0x7400>;
1766 #interconnect-cells = <2>;
1767 qcom,bcm-voters = <&apps_bcm_voter>;
1768 };
1769
1770 system_noc: interconnect@1620000 {
1771 compatible = "qcom,sm8150-system-noc";
1772 reg = <0 0x01620000 0 0x19400>;
1773 #interconnect-cells = <2>;
1774 qcom,bcm-voters = <&apps_bcm_voter>;
1775 };
1776
1777 mc_virt: interconnect@163a000 {
1778 compatible = "qcom,sm8150-mc-virt";
1779 reg = <0 0x0163a000 0 0x1000>;
1780 #interconnect-cells = <2>;
1781 qcom,bcm-voters = <&apps_bcm_voter>;
1782 };
1783
1784 aggre1_noc: interconnect@16e0000 {
1785 compatible = "qcom,sm8150-aggre1-noc";
1786 reg = <0 0x016e0000 0 0xd080>;
1787 #interconnect-cells = <2>;
1788 qcom,bcm-voters = <&apps_bcm_voter>;
1789 };
1790
1791 aggre2_noc: interconnect@1700000 {
1792 compatible = "qcom,sm8150-aggre2-noc";
1793 reg = <0 0x01700000 0 0x20000>;
1794 #interconnect-cells = <2>;
1795 qcom,bcm-voters = <&apps_bcm_voter>;
1796 };
1797
1798 compute_noc: interconnect@1720000 {
1799 compatible = "qcom,sm8150-compute-noc";
1800 reg = <0 0x01720000 0 0x7000>;
1801 #interconnect-cells = <2>;
1802 qcom,bcm-voters = <&apps_bcm_voter>;
1803 };
1804
1805 mmss_noc: interconnect@1740000 {
1806 compatible = "qcom,sm8150-mmss-noc";
1807 reg = <0 0x01740000 0 0x1c100>;
1808 #interconnect-cells = <2>;
1809 qcom,bcm-voters = <&apps_bcm_voter>;
1810 };
1811
1812 system-cache-controller@9200000 {
1813 compatible = "qcom,sm8150-llcc";
1814 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1815 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1816 <0 0x09600000 0 0x50000>;
1817 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1818 "llcc3_base", "llcc_broadcast_base";
1819 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1820 };
1821
1822 dma@10a2000 {
1823 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1824 reg = <0x0 0x010a2000 0x0 0x1000>,
1825 <0x0 0x010ad000 0x0 0x3000>;
1826 };
1827
1828 pcie0: pcie@1c00000 {
1829 compatible = "qcom,pcie-sm8150";
1830 reg = <0 0x01c00000 0 0x3000>,
1831 <0 0x60000000 0 0xf1d>,
1832 <0 0x60000f20 0 0xa8>,
1833 <0 0x60001000 0 0x1000>,
1834 <0 0x60100000 0 0x100000>;
1835 reg-names = "parf", "dbi", "elbi", "atu", "config";
1836 device_type = "pci";
1837 linux,pci-domain = <0>;
1838 bus-range = <0x00 0xff>;
1839 num-lanes = <1>;
1840
1841 #address-cells = <3>;
1842 #size-cells = <2>;
1843
1844 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1845 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1846
1847 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1855 interrupt-names = "msi0",
1856 "msi1",
1857 "msi2",
1858 "msi3",
1859 "msi4",
1860 "msi5",
1861 "msi6",
1862 "msi7";
1863 #interrupt-cells = <1>;
1864 interrupt-map-mask = <0 0 0 0x7>;
1865 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1866 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1867 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1868 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1869
1870 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1871 <&gcc GCC_PCIE_0_AUX_CLK>,
1872 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1873 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1874 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1875 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1876 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1877 <&rpmhcc RPMH_CXO_CLK>;
1878 clock-names = "pipe",
1879 "aux",
1880 "cfg",
1881 "bus_master",
1882 "bus_slave",
1883 "slave_q2a",
1884 "tbu",
1885 "ref";
1886
1887 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1888 <0x100 &apps_smmu 0x1d81 0x1>;
1889
1890 resets = <&gcc GCC_PCIE_0_BCR>;
1891 reset-names = "pci";
1892
1893 power-domains = <&gcc PCIE_0_GDSC>;
1894
1895 phys = <&pcie0_phy>;
1896 phy-names = "pciephy";
1897
1898 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1899 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1900
1901 pinctrl-names = "default";
1902 pinctrl-0 = <&pcie0_default_state>;
1903
1904 status = "disabled";
1905
1906 pcie@0 {
1907 device_type = "pci";
1908 reg = <0x0 0x0 0x0 0x0 0x0>;
1909 bus-range = <0x01 0xff>;
1910
1911 #address-cells = <3>;
1912 #size-cells = <2>;
1913 ranges;
1914 };
1915 };
1916
1917 pcie0_phy: phy@1c06000 {
1918 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1919 reg = <0 0x01c06000 0 0x1000>;
1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1922 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1924 <&gcc GCC_PCIE_0_PIPE_CLK>;
1925 clock-names = "aux",
1926 "cfg_ahb",
1927 "ref",
1928 "refgen",
1929 "pipe";
1930
1931 clock-output-names = "pcie_0_pipe_clk";
1932 #clock-cells = <0>;
1933
1934 #phy-cells = <0>;
1935
1936 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1937 reset-names = "phy";
1938
1939 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1940 assigned-clock-rates = <100000000>;
1941
1942 status = "disabled";
1943 };
1944
1945 pcie1: pcie@1c08000 {
1946 compatible = "qcom,pcie-sm8150";
1947 reg = <0 0x01c08000 0 0x3000>,
1948 <0 0x40000000 0 0xf1d>,
1949 <0 0x40000f20 0 0xa8>,
1950 <0 0x40001000 0 0x1000>,
1951 <0 0x40100000 0 0x100000>;
1952 reg-names = "parf", "dbi", "elbi", "atu", "config";
1953 device_type = "pci";
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1956 num-lanes = <2>;
1957
1958 #address-cells = <3>;
1959 #size-cells = <2>;
1960
1961 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1962 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1963
1964 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-names = "msi0",
1973 "msi1",
1974 "msi2",
1975 "msi3",
1976 "msi4",
1977 "msi5",
1978 "msi6",
1979 "msi7";
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1983 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1984 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1985 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1986
1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1988 <&gcc GCC_PCIE_1_AUX_CLK>,
1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1993 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1994 <&rpmhcc RPMH_CXO_CLK>;
1995 clock-names = "pipe",
1996 "aux",
1997 "cfg",
1998 "bus_master",
1999 "bus_slave",
2000 "slave_q2a",
2001 "tbu",
2002 "ref";
2003
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2005 assigned-clock-rates = <19200000>;
2006
2007 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2008 <0x100 &apps_smmu 0x1e01 0x1>;
2009
2010 resets = <&gcc GCC_PCIE_1_BCR>;
2011 reset-names = "pci";
2012
2013 power-domains = <&gcc PCIE_1_GDSC>;
2014
2015 phys = <&pcie1_phy>;
2016 phy-names = "pciephy";
2017
2018 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2019 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2020
2021 pinctrl-names = "default";
2022 pinctrl-0 = <&pcie1_default_state>;
2023
2024 status = "disabled";
2025
2026 pcie@0 {
2027 device_type = "pci";
2028 reg = <0x0 0x0 0x0 0x0 0x0>;
2029 bus-range = <0x01 0xff>;
2030
2031 #address-cells = <3>;
2032 #size-cells = <2>;
2033 ranges;
2034 };
2035 };
2036
2037 pcie1_phy: phy@1c0e000 {
2038 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2039 reg = <0 0x01c0e000 0 0x1000>;
2040 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2042 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2043 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2044 <&gcc GCC_PCIE_1_PIPE_CLK>;
2045 clock-names = "aux",
2046 "cfg_ahb",
2047 "ref",
2048 "refgen",
2049 "pipe";
2050
2051 clock-output-names = "pcie_1_pipe_clk";
2052 #clock-cells = <0>;
2053
2054 #phy-cells = <0>;
2055
2056 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2057 reset-names = "phy";
2058
2059 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2060 assigned-clock-rates = <100000000>;
2061
2062 status = "disabled";
2063 };
2064
2065 ufs_mem_hc: ufshc@1d84000 {
2066 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2067 "jedec,ufs-2.0";
2068 reg = <0 0x01d84000 0 0x2500>,
2069 <0 0x01d90000 0 0x8000>;
2070 reg-names = "std", "ice";
2071 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2072 phys = <&ufs_mem_phy>;
2073 phy-names = "ufsphy";
2074 lanes-per-direction = <2>;
2075 #reset-cells = <1>;
2076 resets = <&gcc GCC_UFS_PHY_BCR>;
2077 reset-names = "rst";
2078
2079 iommus = <&apps_smmu 0x300 0>;
2080
2081 clock-names =
2082 "core_clk",
2083 "bus_aggr_clk",
2084 "iface_clk",
2085 "core_clk_unipro",
2086 "ref_clk",
2087 "tx_lane0_sync_clk",
2088 "rx_lane0_sync_clk",
2089 "rx_lane1_sync_clk",
2090 "ice_core_clk";
2091 clocks =
2092 <&gcc GCC_UFS_PHY_AXI_CLK>,
2093 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_UFS_PHY_AHB_CLK>,
2095 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2096 <&rpmhcc RPMH_CXO_CLK>,
2097 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2098 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2100 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2101 freq-table-hz =
2102 <37500000 300000000>,
2103 <0 0>,
2104 <0 0>,
2105 <37500000 300000000>,
2106 <0 0>,
2107 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 300000000>;
2111
2112 status = "disabled";
2113 };
2114
2115 ufs_mem_phy: phy@1d87000 {
2116 compatible = "qcom,sm8150-qmp-ufs-phy";
2117 reg = <0 0x01d87000 0 0x1000>;
2118
2119 clocks = <&rpmhcc RPMH_CXO_CLK>,
2120 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2121 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2122 clock-names = "ref",
2123 "ref_aux",
2124 "qref";
2125
2126 power-domains = <&gcc UFS_PHY_GDSC>;
2127
2128 resets = <&ufs_mem_hc 0>;
2129 reset-names = "ufsphy";
2130
2131 #phy-cells = <0>;
2132
2133 status = "disabled";
2134 };
2135
2136 cryptobam: dma-controller@1dc4000 {
2137 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2138 reg = <0 0x01dc4000 0 0x24000>;
2139 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2140 #dma-cells = <1>;
2141 qcom,ee = <0>;
2142 qcom,controlled-remotely;
2143 num-channels = <8>;
2144 qcom,num-ees = <2>;
2145 iommus = <&apps_smmu 0x502 0x0641>,
2146 <&apps_smmu 0x504 0x0011>,
2147 <&apps_smmu 0x506 0x0011>,
2148 <&apps_smmu 0x508 0x0011>,
2149 <&apps_smmu 0x512 0x0000>;
2150 };
2151
2152 crypto: crypto@1dfa000 {
2153 compatible = "qcom,sm8150-qce", "qcom,qce";
2154 reg = <0 0x01dfa000 0 0x6000>;
2155 dmas = <&cryptobam 4>, <&cryptobam 5>;
2156 dma-names = "rx", "tx";
2157 iommus = <&apps_smmu 0x502 0x0641>,
2158 <&apps_smmu 0x504 0x0011>,
2159 <&apps_smmu 0x506 0x0011>,
2160 <&apps_smmu 0x508 0x0011>,
2161 <&apps_smmu 0x512 0x0000>;
2162 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2163 interconnect-names = "memory";
2164 };
2165
2166 tcsr_mutex: hwlock@1f40000 {
2167 compatible = "qcom,tcsr-mutex";
2168 reg = <0x0 0x01f40000 0x0 0x20000>;
2169 #hwlock-cells = <1>;
2170 };
2171
2172 tcsr_regs_1: syscon@1f60000 {
2173 compatible = "qcom,sm8150-tcsr", "syscon";
2174 reg = <0x0 0x01f60000 0x0 0x20000>;
2175 };
2176
2177 remoteproc_slpi: remoteproc@2400000 {
2178 compatible = "qcom,sm8150-slpi-pas";
2179 reg = <0x0 0x02400000 0x0 0x4040>;
2180
2181 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2182 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2183 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2184 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2185 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2186 interrupt-names = "wdog", "fatal", "ready",
2187 "handover", "stop-ack";
2188
2189 clocks = <&rpmhcc RPMH_CXO_CLK>;
2190 clock-names = "xo";
2191
2192 power-domains = <&rpmhpd SM8150_LCX>,
2193 <&rpmhpd SM8150_LMX>;
2194 power-domain-names = "lcx", "lmx";
2195
2196 memory-region = <&slpi_mem>;
2197
2198 qcom,qmp = <&aoss_qmp>;
2199
2200 qcom,smem-states = <&slpi_smp2p_out 0>;
2201 qcom,smem-state-names = "stop";
2202
2203 status = "disabled";
2204
2205 glink-edge {
2206 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2207 label = "dsps";
2208 qcom,remote-pid = <3>;
2209 mboxes = <&apss_shared 24>;
2210
2211 fastrpc {
2212 compatible = "qcom,fastrpc";
2213 qcom,glink-channels = "fastrpcglink-apps-dsp";
2214 label = "sdsp";
2215 qcom,non-secure-domain;
2216 #address-cells = <1>;
2217 #size-cells = <0>;
2218
2219 compute-cb@1 {
2220 compatible = "qcom,fastrpc-compute-cb";
2221 reg = <1>;
2222 iommus = <&apps_smmu 0x05a1 0x0>;
2223 };
2224
2225 compute-cb@2 {
2226 compatible = "qcom,fastrpc-compute-cb";
2227 reg = <2>;
2228 iommus = <&apps_smmu 0x05a2 0x0>;
2229 };
2230
2231 compute-cb@3 {
2232 compatible = "qcom,fastrpc-compute-cb";
2233 reg = <3>;
2234 iommus = <&apps_smmu 0x05a3 0x0>;
2235 /* note: shared-cb = <4> in downstream */
2236 };
2237 };
2238 };
2239 };
2240
2241 gpu: gpu@2c00000 {
2242 compatible = "qcom,adreno-640.1", "qcom,adreno";
2243 reg = <0 0x02c00000 0 0x40000>;
2244 reg-names = "kgsl_3d0_reg_memory";
2245
2246 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2247
2248 iommus = <&adreno_smmu 0 0x401>;
2249
2250 operating-points-v2 = <&gpu_opp_table>;
2251
2252 qcom,gmu = <&gmu>;
2253
2254 nvmem-cells = <&gpu_speed_bin>;
2255 nvmem-cell-names = "speed_bin";
2256 #cooling-cells = <2>;
2257
2258 status = "disabled";
2259
2260 zap-shader {
2261 memory-region = <&gpu_mem>;
2262 };
2263
2264 gpu_opp_table: opp-table {
2265 compatible = "operating-points-v2";
2266
2267 opp-675000000 {
2268 opp-hz = /bits/ 64 <675000000>;
2269 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2270 opp-supported-hw = <0x2>;
2271 };
2272
2273 opp-585000000 {
2274 opp-hz = /bits/ 64 <585000000>;
2275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2276 opp-supported-hw = <0x3>;
2277 };
2278
2279 opp-499200000 {
2280 opp-hz = /bits/ 64 <499200000>;
2281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2282 opp-supported-hw = <0x3>;
2283 };
2284
2285 opp-427000000 {
2286 opp-hz = /bits/ 64 <427000000>;
2287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2288 opp-supported-hw = <0x3>;
2289 };
2290
2291 opp-345000000 {
2292 opp-hz = /bits/ 64 <345000000>;
2293 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2294 opp-supported-hw = <0x3>;
2295 };
2296
2297 opp-257000000 {
2298 opp-hz = /bits/ 64 <257000000>;
2299 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2300 opp-supported-hw = <0x3>;
2301 };
2302 };
2303 };
2304
2305 gmu: gmu@2c6a000 {
2306 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2307
2308 reg = <0 0x02c6a000 0 0x30000>,
2309 <0 0x0b290000 0 0x10000>,
2310 <0 0x0b490000 0 0x10000>;
2311 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2312
2313 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2314 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2315 interrupt-names = "hfi", "gmu";
2316
2317 clocks = <&gpucc GPU_CC_AHB_CLK>,
2318 <&gpucc GPU_CC_CX_GMU_CLK>,
2319 <&gpucc GPU_CC_CXO_CLK>,
2320 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2321 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2322 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2323
2324 power-domains = <&gpucc GPU_CX_GDSC>,
2325 <&gpucc GPU_GX_GDSC>;
2326 power-domain-names = "cx", "gx";
2327
2328 iommus = <&adreno_smmu 5 0x400>;
2329
2330 operating-points-v2 = <&gmu_opp_table>;
2331
2332 status = "disabled";
2333
2334 gmu_opp_table: opp-table {
2335 compatible = "operating-points-v2";
2336
2337 opp-200000000 {
2338 opp-hz = /bits/ 64 <200000000>;
2339 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2340 };
2341 };
2342 };
2343
2344 gpucc: clock-controller@2c90000 {
2345 compatible = "qcom,sm8150-gpucc";
2346 reg = <0 0x02c90000 0 0x9000>;
2347 clocks = <&rpmhcc RPMH_CXO_CLK>,
2348 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2349 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2350 clock-names = "bi_tcxo",
2351 "gcc_gpu_gpll0_clk_src",
2352 "gcc_gpu_gpll0_div_clk_src";
2353 #clock-cells = <1>;
2354 #reset-cells = <1>;
2355 #power-domain-cells = <1>;
2356 };
2357
2358 adreno_smmu: iommu@2ca0000 {
2359 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2360 "qcom,smmu-500", "arm,mmu-500";
2361 reg = <0 0x02ca0000 0 0x10000>;
2362 #iommu-cells = <2>;
2363 #global-interrupts = <1>;
2364 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2373 clocks = <&gpucc GPU_CC_AHB_CLK>,
2374 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2375 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2376 clock-names = "ahb", "bus", "iface";
2377
2378 power-domains = <&gpucc GPU_CX_GDSC>;
2379 };
2380
2381 tlmm: pinctrl@3100000 {
2382 compatible = "qcom,sm8150-pinctrl";
2383 reg = <0x0 0x03100000 0x0 0x300000>,
2384 <0x0 0x03500000 0x0 0x300000>,
2385 <0x0 0x03900000 0x0 0x300000>,
2386 <0x0 0x03D00000 0x0 0x300000>;
2387 reg-names = "west", "east", "north", "south";
2388 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2389 gpio-ranges = <&tlmm 0 0 176>;
2390 gpio-controller;
2391 #gpio-cells = <2>;
2392 interrupt-controller;
2393 #interrupt-cells = <2>;
2394 wakeup-parent = <&pdc>;
2395
2396 qup_i2c0_default: qup-i2c0-default-state {
2397 pins = "gpio0", "gpio1";
2398 function = "qup0";
2399 drive-strength = <0x02>;
2400 bias-disable;
2401 };
2402
2403 qup_spi0_default: qup-spi0-default-state {
2404 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2405 function = "qup0";
2406 drive-strength = <6>;
2407 bias-disable;
2408 };
2409
2410 qup_i2c1_default: qup-i2c1-default-state {
2411 pins = "gpio114", "gpio115";
2412 function = "qup1";
2413 drive-strength = <2>;
2414 bias-disable;
2415 };
2416
2417 qup_spi1_default: qup-spi1-default-state {
2418 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2419 function = "qup1";
2420 drive-strength = <6>;
2421 bias-disable;
2422 };
2423
2424 qup_i2c2_default: qup-i2c2-default-state {
2425 pins = "gpio126", "gpio127";
2426 function = "qup2";
2427 drive-strength = <2>;
2428 bias-disable;
2429 };
2430
2431 qup_spi2_default: qup-spi2-default-state {
2432 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2433 function = "qup2";
2434 drive-strength = <6>;
2435 bias-disable;
2436 };
2437
2438 qup_i2c3_default: qup-i2c3-default-state {
2439 pins = "gpio144", "gpio145";
2440 function = "qup3";
2441 drive-strength = <2>;
2442 bias-disable;
2443 };
2444
2445 qup_spi3_default: qup-spi3-default-state {
2446 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2447 function = "qup3";
2448 drive-strength = <6>;
2449 bias-disable;
2450 };
2451
2452 qup_i2c4_default: qup-i2c4-default-state {
2453 pins = "gpio51", "gpio52";
2454 function = "qup4";
2455 drive-strength = <2>;
2456 bias-disable;
2457 };
2458
2459 qup_spi4_default: qup-spi4-default-state {
2460 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2461 function = "qup4";
2462 drive-strength = <6>;
2463 bias-disable;
2464 };
2465
2466 qup_i2c5_default: qup-i2c5-default-state {
2467 pins = "gpio121", "gpio122";
2468 function = "qup5";
2469 drive-strength = <2>;
2470 bias-disable;
2471 };
2472
2473 qup_spi5_default: qup-spi5-default-state {
2474 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2475 function = "qup5";
2476 drive-strength = <6>;
2477 bias-disable;
2478 };
2479
2480 qup_i2c6_default: qup-i2c6-default-state {
2481 pins = "gpio6", "gpio7";
2482 function = "qup6";
2483 drive-strength = <2>;
2484 bias-disable;
2485 };
2486
2487 qup_spi6_default: qup-spi6-default-state {
2488 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2489 function = "qup6";
2490 drive-strength = <6>;
2491 bias-disable;
2492 };
2493
2494 qup_i2c7_default: qup-i2c7-default-state {
2495 pins = "gpio98", "gpio99";
2496 function = "qup7";
2497 drive-strength = <2>;
2498 bias-disable;
2499 };
2500
2501 qup_spi7_default: qup-spi7-default-state {
2502 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2503 function = "qup7";
2504 drive-strength = <6>;
2505 bias-disable;
2506 };
2507
2508 qup_i2c8_default: qup-i2c8-default-state {
2509 pins = "gpio88", "gpio89";
2510 function = "qup8";
2511 drive-strength = <2>;
2512 bias-disable;
2513 };
2514
2515 qup_spi8_default: qup-spi8-default-state {
2516 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2517 function = "qup8";
2518 drive-strength = <6>;
2519 bias-disable;
2520 };
2521
2522 qup_i2c9_default: qup-i2c9-default-state {
2523 pins = "gpio39", "gpio40";
2524 function = "qup9";
2525 drive-strength = <2>;
2526 bias-disable;
2527 };
2528
2529 qup_spi9_default: qup-spi9-default-state {
2530 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2531 function = "qup9";
2532 drive-strength = <6>;
2533 bias-disable;
2534 };
2535
2536 qup_uart9_default: qup-uart9-default-state {
2537 pins = "gpio41", "gpio42";
2538 function = "qup9";
2539 drive-strength = <2>;
2540 bias-disable;
2541 };
2542
2543 qup_i2c10_default: qup-i2c10-default-state {
2544 pins = "gpio9", "gpio10";
2545 function = "qup10";
2546 drive-strength = <2>;
2547 bias-disable;
2548 };
2549
2550 qup_spi10_default: qup-spi10-default-state {
2551 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2552 function = "qup10";
2553 drive-strength = <6>;
2554 bias-disable;
2555 };
2556
2557 qup_i2c11_default: qup-i2c11-default-state {
2558 pins = "gpio94", "gpio95";
2559 function = "qup11";
2560 drive-strength = <2>;
2561 bias-disable;
2562 };
2563
2564 qup_spi11_default: qup-spi11-default-state {
2565 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2566 function = "qup11";
2567 drive-strength = <6>;
2568 bias-disable;
2569 };
2570
2571 qup_i2c12_default: qup-i2c12-default-state {
2572 pins = "gpio83", "gpio84";
2573 function = "qup12";
2574 drive-strength = <2>;
2575 bias-disable;
2576 };
2577
2578 qup_spi12_default: qup-spi12-default-state {
2579 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2580 function = "qup12";
2581 drive-strength = <6>;
2582 bias-disable;
2583 };
2584
2585 qup_i2c13_default: qup-i2c13-default-state {
2586 pins = "gpio43", "gpio44";
2587 function = "qup13";
2588 drive-strength = <2>;
2589 bias-disable;
2590 };
2591
2592 qup_spi13_default: qup-spi13-default-state {
2593 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2594 function = "qup13";
2595 drive-strength = <6>;
2596 bias-disable;
2597 };
2598
2599 qup_i2c14_default: qup-i2c14-default-state {
2600 pins = "gpio47", "gpio48";
2601 function = "qup14";
2602 drive-strength = <2>;
2603 bias-disable;
2604 };
2605
2606 qup_spi14_default: qup-spi14-default-state {
2607 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2608 function = "qup14";
2609 drive-strength = <6>;
2610 bias-disable;
2611 };
2612
2613 qup_i2c15_default: qup-i2c15-default-state {
2614 pins = "gpio27", "gpio28";
2615 function = "qup15";
2616 drive-strength = <2>;
2617 bias-disable;
2618 };
2619
2620 qup_spi15_default: qup-spi15-default-state {
2621 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2622 function = "qup15";
2623 drive-strength = <6>;
2624 bias-disable;
2625 };
2626
2627 qup_i2c16_default: qup-i2c16-default-state {
2628 pins = "gpio86", "gpio85";
2629 function = "qup16";
2630 drive-strength = <2>;
2631 bias-disable;
2632 };
2633
2634 qup_spi16_default: qup-spi16-default-state {
2635 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2636 function = "qup16";
2637 drive-strength = <6>;
2638 bias-disable;
2639 };
2640
2641 qup_i2c17_default: qup-i2c17-default-state {
2642 pins = "gpio55", "gpio56";
2643 function = "qup17";
2644 drive-strength = <2>;
2645 bias-disable;
2646 };
2647
2648 qup_spi17_default: qup-spi17-default-state {
2649 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2650 function = "qup17";
2651 drive-strength = <6>;
2652 bias-disable;
2653 };
2654
2655 qup_i2c18_default: qup-i2c18-default-state {
2656 pins = "gpio23", "gpio24";
2657 function = "qup18";
2658 drive-strength = <2>;
2659 bias-disable;
2660 };
2661
2662 qup_spi18_default: qup-spi18-default-state {
2663 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2664 function = "qup18";
2665 drive-strength = <6>;
2666 bias-disable;
2667 };
2668
2669 qup_i2c19_default: qup-i2c19-default-state {
2670 pins = "gpio57", "gpio58";
2671 function = "qup19";
2672 drive-strength = <2>;
2673 bias-disable;
2674 };
2675
2676 qup_spi19_default: qup-spi19-default-state {
2677 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2678 function = "qup19";
2679 drive-strength = <6>;
2680 bias-disable;
2681 };
2682
2683 pcie0_default_state: pcie0-default-state {
2684 perst-pins {
2685 pins = "gpio35";
2686 function = "gpio";
2687 drive-strength = <2>;
2688 bias-pull-down;
2689 };
2690
2691 clkreq-pins {
2692 pins = "gpio36";
2693 function = "pci_e0";
2694 drive-strength = <2>;
2695 bias-pull-up;
2696 };
2697
2698 wake-pins {
2699 pins = "gpio37";
2700 function = "gpio";
2701 drive-strength = <2>;
2702 bias-pull-up;
2703 };
2704 };
2705
2706 pcie1_default_state: pcie1-default-state {
2707 perst-pins {
2708 pins = "gpio102";
2709 function = "gpio";
2710 drive-strength = <2>;
2711 bias-pull-down;
2712 };
2713
2714 clkreq-pins {
2715 pins = "gpio103";
2716 function = "pci_e1";
2717 drive-strength = <2>;
2718 bias-pull-up;
2719 };
2720
2721 wake-pins {
2722 pins = "gpio104";
2723 function = "gpio";
2724 drive-strength = <2>;
2725 bias-pull-up;
2726 };
2727 };
2728 };
2729
2730 remoteproc_mpss: remoteproc@4080000 {
2731 compatible = "qcom,sm8150-mpss-pas";
2732 reg = <0x0 0x04080000 0x0 0x4040>;
2733
2734 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2735 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2736 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2737 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2738 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2739 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2740 interrupt-names = "wdog", "fatal", "ready", "handover",
2741 "stop-ack", "shutdown-ack";
2742
2743 clocks = <&rpmhcc RPMH_CXO_CLK>;
2744 clock-names = "xo";
2745
2746 power-domains = <&rpmhpd SM8150_CX>,
2747 <&rpmhpd SM8150_MSS>;
2748 power-domain-names = "cx", "mss";
2749
2750 memory-region = <&mpss_mem>;
2751
2752 qcom,qmp = <&aoss_qmp>;
2753
2754 qcom,smem-states = <&modem_smp2p_out 0>;
2755 qcom,smem-state-names = "stop";
2756
2757 status = "disabled";
2758
2759 glink-edge {
2760 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2761 label = "modem";
2762 qcom,remote-pid = <1>;
2763 mboxes = <&apss_shared 12>;
2764 };
2765 };
2766
2767 stm@6002000 {
2768 compatible = "arm,coresight-stm", "arm,primecell";
2769 reg = <0 0x06002000 0 0x1000>,
2770 <0 0x16280000 0 0x180000>;
2771 reg-names = "stm-base", "stm-stimulus-base";
2772
2773 clocks = <&aoss_qmp>;
2774 clock-names = "apb_pclk";
2775
2776 out-ports {
2777 port {
2778 stm_out: endpoint {
2779 remote-endpoint = <&funnel0_in7>;
2780 };
2781 };
2782 };
2783 };
2784
2785 funnel@6041000 {
2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2787 reg = <0 0x06041000 0 0x1000>;
2788
2789 clocks = <&aoss_qmp>;
2790 clock-names = "apb_pclk";
2791
2792 out-ports {
2793 port {
2794 funnel0_out: endpoint {
2795 remote-endpoint = <&merge_funnel_in0>;
2796 };
2797 };
2798 };
2799
2800 in-ports {
2801 #address-cells = <1>;
2802 #size-cells = <0>;
2803
2804 port@7 {
2805 reg = <7>;
2806 funnel0_in7: endpoint {
2807 remote-endpoint = <&stm_out>;
2808 };
2809 };
2810 };
2811 };
2812
2813 funnel@6042000 {
2814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2815 reg = <0 0x06042000 0 0x1000>;
2816
2817 clocks = <&aoss_qmp>;
2818 clock-names = "apb_pclk";
2819
2820 out-ports {
2821 port {
2822 funnel1_out: endpoint {
2823 remote-endpoint = <&merge_funnel_in1>;
2824 };
2825 };
2826 };
2827
2828 in-ports {
2829 #address-cells = <1>;
2830 #size-cells = <0>;
2831
2832 port@4 {
2833 reg = <4>;
2834 funnel1_in4: endpoint {
2835 remote-endpoint = <&swao_replicator_out>;
2836 };
2837 };
2838 };
2839 };
2840
2841 funnel@6043000 {
2842 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2843 reg = <0 0x06043000 0 0x1000>;
2844
2845 clocks = <&aoss_qmp>;
2846 clock-names = "apb_pclk";
2847
2848 out-ports {
2849 port {
2850 funnel2_out: endpoint {
2851 remote-endpoint = <&merge_funnel_in2>;
2852 };
2853 };
2854 };
2855
2856 in-ports {
2857 #address-cells = <1>;
2858 #size-cells = <0>;
2859
2860 port@2 {
2861 reg = <2>;
2862 funnel2_in2: endpoint {
2863 remote-endpoint = <&apss_merge_funnel_out>;
2864 };
2865 };
2866 };
2867 };
2868
2869 funnel@6045000 {
2870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2871 reg = <0 0x06045000 0 0x1000>;
2872
2873 clocks = <&aoss_qmp>;
2874 clock-names = "apb_pclk";
2875
2876 out-ports {
2877 port {
2878 merge_funnel_out: endpoint {
2879 remote-endpoint = <&etf_in>;
2880 };
2881 };
2882 };
2883
2884 in-ports {
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2887
2888 port@0 {
2889 reg = <0>;
2890 merge_funnel_in0: endpoint {
2891 remote-endpoint = <&funnel0_out>;
2892 };
2893 };
2894
2895 port@1 {
2896 reg = <1>;
2897 merge_funnel_in1: endpoint {
2898 remote-endpoint = <&funnel1_out>;
2899 };
2900 };
2901
2902 port@2 {
2903 reg = <2>;
2904 merge_funnel_in2: endpoint {
2905 remote-endpoint = <&funnel2_out>;
2906 };
2907 };
2908 };
2909 };
2910
2911 replicator@6046000 {
2912 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2913 reg = <0 0x06046000 0 0x1000>;
2914
2915 clocks = <&aoss_qmp>;
2916 clock-names = "apb_pclk";
2917
2918 out-ports {
2919 #address-cells = <1>;
2920 #size-cells = <0>;
2921
2922 port@0 {
2923 reg = <0>;
2924 replicator_out0: endpoint {
2925 remote-endpoint = <&etr_in>;
2926 };
2927 };
2928
2929 port@1 {
2930 reg = <1>;
2931 replicator_out1: endpoint {
2932 remote-endpoint = <&replicator1_in>;
2933 };
2934 };
2935 };
2936
2937 in-ports {
2938 port {
2939 replicator_in0: endpoint {
2940 remote-endpoint = <&etf_out>;
2941 };
2942 };
2943 };
2944 };
2945
2946 etf@6047000 {
2947 compatible = "arm,coresight-tmc", "arm,primecell";
2948 reg = <0 0x06047000 0 0x1000>;
2949
2950 clocks = <&aoss_qmp>;
2951 clock-names = "apb_pclk";
2952
2953 out-ports {
2954 port {
2955 etf_out: endpoint {
2956 remote-endpoint = <&replicator_in0>;
2957 };
2958 };
2959 };
2960
2961 in-ports {
2962 port {
2963 etf_in: endpoint {
2964 remote-endpoint = <&merge_funnel_out>;
2965 };
2966 };
2967 };
2968 };
2969
2970 etr@6048000 {
2971 compatible = "arm,coresight-tmc", "arm,primecell";
2972 reg = <0 0x06048000 0 0x1000>;
2973 iommus = <&apps_smmu 0x05e0 0x0>;
2974
2975 clocks = <&aoss_qmp>;
2976 clock-names = "apb_pclk";
2977 arm,scatter-gather;
2978
2979 in-ports {
2980 port {
2981 etr_in: endpoint {
2982 remote-endpoint = <&replicator_out0>;
2983 };
2984 };
2985 };
2986 };
2987
2988 replicator@604a000 {
2989 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2990 reg = <0 0x0604a000 0 0x1000>;
2991
2992 clocks = <&aoss_qmp>;
2993 clock-names = "apb_pclk";
2994
2995 out-ports {
2996 #address-cells = <1>;
2997 #size-cells = <0>;
2998
2999 port@1 {
3000 reg = <1>;
3001 replicator1_out: endpoint {
3002 remote-endpoint = <&swao_funnel_in>;
3003 };
3004 };
3005 };
3006
3007 in-ports {
3008
3009 port {
3010 replicator1_in: endpoint {
3011 remote-endpoint = <&replicator_out1>;
3012 };
3013 };
3014 };
3015 };
3016
3017 funnel@6b08000 {
3018 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3019 reg = <0 0x06b08000 0 0x1000>;
3020
3021 clocks = <&aoss_qmp>;
3022 clock-names = "apb_pclk";
3023
3024 out-ports {
3025 port {
3026 swao_funnel_out: endpoint {
3027 remote-endpoint = <&swao_etf_in>;
3028 };
3029 };
3030 };
3031
3032 in-ports {
3033 #address-cells = <1>;
3034 #size-cells = <0>;
3035
3036 port@6 {
3037 reg = <6>;
3038 swao_funnel_in: endpoint {
3039 remote-endpoint = <&replicator1_out>;
3040 };
3041 };
3042 };
3043 };
3044
3045 etf@6b09000 {
3046 compatible = "arm,coresight-tmc", "arm,primecell";
3047 reg = <0 0x06b09000 0 0x1000>;
3048
3049 clocks = <&aoss_qmp>;
3050 clock-names = "apb_pclk";
3051
3052 out-ports {
3053 port {
3054 swao_etf_out: endpoint {
3055 remote-endpoint = <&swao_replicator_in>;
3056 };
3057 };
3058 };
3059
3060 in-ports {
3061 port {
3062 swao_etf_in: endpoint {
3063 remote-endpoint = <&swao_funnel_out>;
3064 };
3065 };
3066 };
3067 };
3068
3069 replicator@6b0a000 {
3070 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3071 reg = <0 0x06b0a000 0 0x1000>;
3072
3073 clocks = <&aoss_qmp>;
3074 clock-names = "apb_pclk";
3075 qcom,replicator-loses-context;
3076
3077 out-ports {
3078 port {
3079 swao_replicator_out: endpoint {
3080 remote-endpoint = <&funnel1_in4>;
3081 };
3082 };
3083 };
3084
3085 in-ports {
3086 port {
3087 swao_replicator_in: endpoint {
3088 remote-endpoint = <&swao_etf_out>;
3089 };
3090 };
3091 };
3092 };
3093
3094 etm@7040000 {
3095 compatible = "arm,coresight-etm4x", "arm,primecell";
3096 reg = <0 0x07040000 0 0x1000>;
3097
3098 cpu = <&CPU0>;
3099
3100 clocks = <&aoss_qmp>;
3101 clock-names = "apb_pclk";
3102 arm,coresight-loses-context-with-cpu;
3103 qcom,skip-power-up;
3104
3105 out-ports {
3106 port {
3107 etm0_out: endpoint {
3108 remote-endpoint = <&apss_funnel_in0>;
3109 };
3110 };
3111 };
3112 };
3113
3114 etm@7140000 {
3115 compatible = "arm,coresight-etm4x", "arm,primecell";
3116 reg = <0 0x07140000 0 0x1000>;
3117
3118 cpu = <&CPU1>;
3119
3120 clocks = <&aoss_qmp>;
3121 clock-names = "apb_pclk";
3122 arm,coresight-loses-context-with-cpu;
3123 qcom,skip-power-up;
3124
3125 out-ports {
3126 port {
3127 etm1_out: endpoint {
3128 remote-endpoint = <&apss_funnel_in1>;
3129 };
3130 };
3131 };
3132 };
3133
3134 etm@7240000 {
3135 compatible = "arm,coresight-etm4x", "arm,primecell";
3136 reg = <0 0x07240000 0 0x1000>;
3137
3138 cpu = <&CPU2>;
3139
3140 clocks = <&aoss_qmp>;
3141 clock-names = "apb_pclk";
3142 arm,coresight-loses-context-with-cpu;
3143 qcom,skip-power-up;
3144
3145 out-ports {
3146 port {
3147 etm2_out: endpoint {
3148 remote-endpoint = <&apss_funnel_in2>;
3149 };
3150 };
3151 };
3152 };
3153
3154 etm@7340000 {
3155 compatible = "arm,coresight-etm4x", "arm,primecell";
3156 reg = <0 0x07340000 0 0x1000>;
3157
3158 cpu = <&CPU3>;
3159
3160 clocks = <&aoss_qmp>;
3161 clock-names = "apb_pclk";
3162 arm,coresight-loses-context-with-cpu;
3163 qcom,skip-power-up;
3164
3165 out-ports {
3166 port {
3167 etm3_out: endpoint {
3168 remote-endpoint = <&apss_funnel_in3>;
3169 };
3170 };
3171 };
3172 };
3173
3174 etm@7440000 {
3175 compatible = "arm,coresight-etm4x", "arm,primecell";
3176 reg = <0 0x07440000 0 0x1000>;
3177
3178 cpu = <&CPU4>;
3179
3180 clocks = <&aoss_qmp>;
3181 clock-names = "apb_pclk";
3182 arm,coresight-loses-context-with-cpu;
3183 qcom,skip-power-up;
3184
3185 out-ports {
3186 port {
3187 etm4_out: endpoint {
3188 remote-endpoint = <&apss_funnel_in4>;
3189 };
3190 };
3191 };
3192 };
3193
3194 etm@7540000 {
3195 compatible = "arm,coresight-etm4x", "arm,primecell";
3196 reg = <0 0x07540000 0 0x1000>;
3197
3198 cpu = <&CPU5>;
3199
3200 clocks = <&aoss_qmp>;
3201 clock-names = "apb_pclk";
3202 arm,coresight-loses-context-with-cpu;
3203 qcom,skip-power-up;
3204
3205 out-ports {
3206 port {
3207 etm5_out: endpoint {
3208 remote-endpoint = <&apss_funnel_in5>;
3209 };
3210 };
3211 };
3212 };
3213
3214 etm@7640000 {
3215 compatible = "arm,coresight-etm4x", "arm,primecell";
3216 reg = <0 0x07640000 0 0x1000>;
3217
3218 cpu = <&CPU6>;
3219
3220 clocks = <&aoss_qmp>;
3221 clock-names = "apb_pclk";
3222 arm,coresight-loses-context-with-cpu;
3223 qcom,skip-power-up;
3224
3225 out-ports {
3226 port {
3227 etm6_out: endpoint {
3228 remote-endpoint = <&apss_funnel_in6>;
3229 };
3230 };
3231 };
3232 };
3233
3234 etm@7740000 {
3235 compatible = "arm,coresight-etm4x", "arm,primecell";
3236 reg = <0 0x07740000 0 0x1000>;
3237
3238 cpu = <&CPU7>;
3239
3240 clocks = <&aoss_qmp>;
3241 clock-names = "apb_pclk";
3242 arm,coresight-loses-context-with-cpu;
3243 qcom,skip-power-up;
3244
3245 out-ports {
3246 port {
3247 etm7_out: endpoint {
3248 remote-endpoint = <&apss_funnel_in7>;
3249 };
3250 };
3251 };
3252 };
3253
3254 funnel@7800000 { /* APSS Funnel */
3255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3256 reg = <0 0x07800000 0 0x1000>;
3257
3258 clocks = <&aoss_qmp>;
3259 clock-names = "apb_pclk";
3260
3261 out-ports {
3262 port {
3263 apss_funnel_out: endpoint {
3264 remote-endpoint = <&apss_merge_funnel_in>;
3265 };
3266 };
3267 };
3268
3269 in-ports {
3270 #address-cells = <1>;
3271 #size-cells = <0>;
3272
3273 port@0 {
3274 reg = <0>;
3275 apss_funnel_in0: endpoint {
3276 remote-endpoint = <&etm0_out>;
3277 };
3278 };
3279
3280 port@1 {
3281 reg = <1>;
3282 apss_funnel_in1: endpoint {
3283 remote-endpoint = <&etm1_out>;
3284 };
3285 };
3286
3287 port@2 {
3288 reg = <2>;
3289 apss_funnel_in2: endpoint {
3290 remote-endpoint = <&etm2_out>;
3291 };
3292 };
3293
3294 port@3 {
3295 reg = <3>;
3296 apss_funnel_in3: endpoint {
3297 remote-endpoint = <&etm3_out>;
3298 };
3299 };
3300
3301 port@4 {
3302 reg = <4>;
3303 apss_funnel_in4: endpoint {
3304 remote-endpoint = <&etm4_out>;
3305 };
3306 };
3307
3308 port@5 {
3309 reg = <5>;
3310 apss_funnel_in5: endpoint {
3311 remote-endpoint = <&etm5_out>;
3312 };
3313 };
3314
3315 port@6 {
3316 reg = <6>;
3317 apss_funnel_in6: endpoint {
3318 remote-endpoint = <&etm6_out>;
3319 };
3320 };
3321
3322 port@7 {
3323 reg = <7>;
3324 apss_funnel_in7: endpoint {
3325 remote-endpoint = <&etm7_out>;
3326 };
3327 };
3328 };
3329 };
3330
3331 funnel@7810000 {
3332 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3333 reg = <0 0x07810000 0 0x1000>;
3334
3335 clocks = <&aoss_qmp>;
3336 clock-names = "apb_pclk";
3337
3338 out-ports {
3339 port {
3340 apss_merge_funnel_out: endpoint {
3341 remote-endpoint = <&funnel2_in2>;
3342 };
3343 };
3344 };
3345
3346 in-ports {
3347 port {
3348 apss_merge_funnel_in: endpoint {
3349 remote-endpoint = <&apss_funnel_out>;
3350 };
3351 };
3352 };
3353 };
3354
3355 remoteproc_cdsp: remoteproc@8300000 {
3356 compatible = "qcom,sm8150-cdsp-pas";
3357 reg = <0x0 0x08300000 0x0 0x4040>;
3358
3359 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3360 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3361 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3362 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3363 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3364 interrupt-names = "wdog", "fatal", "ready",
3365 "handover", "stop-ack";
3366
3367 clocks = <&rpmhcc RPMH_CXO_CLK>;
3368 clock-names = "xo";
3369
3370 power-domains = <&rpmhpd SM8150_CX>;
3371
3372 memory-region = <&cdsp_mem>;
3373
3374 qcom,qmp = <&aoss_qmp>;
3375
3376 qcom,smem-states = <&cdsp_smp2p_out 0>;
3377 qcom,smem-state-names = "stop";
3378
3379 status = "disabled";
3380
3381 glink-edge {
3382 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3383 label = "cdsp";
3384 qcom,remote-pid = <5>;
3385 mboxes = <&apss_shared 4>;
3386
3387 fastrpc {
3388 compatible = "qcom,fastrpc";
3389 qcom,glink-channels = "fastrpcglink-apps-dsp";
3390 label = "cdsp";
3391 qcom,non-secure-domain;
3392 #address-cells = <1>;
3393 #size-cells = <0>;
3394
3395 compute-cb@1 {
3396 compatible = "qcom,fastrpc-compute-cb";
3397 reg = <1>;
3398 iommus = <&apps_smmu 0x1001 0x0460>;
3399 };
3400
3401 compute-cb@2 {
3402 compatible = "qcom,fastrpc-compute-cb";
3403 reg = <2>;
3404 iommus = <&apps_smmu 0x1002 0x0460>;
3405 };
3406
3407 compute-cb@3 {
3408 compatible = "qcom,fastrpc-compute-cb";
3409 reg = <3>;
3410 iommus = <&apps_smmu 0x1003 0x0460>;
3411 };
3412
3413 compute-cb@4 {
3414 compatible = "qcom,fastrpc-compute-cb";
3415 reg = <4>;
3416 iommus = <&apps_smmu 0x1004 0x0460>;
3417 };
3418
3419 compute-cb@5 {
3420 compatible = "qcom,fastrpc-compute-cb";
3421 reg = <5>;
3422 iommus = <&apps_smmu 0x1005 0x0460>;
3423 };
3424
3425 compute-cb@6 {
3426 compatible = "qcom,fastrpc-compute-cb";
3427 reg = <6>;
3428 iommus = <&apps_smmu 0x1006 0x0460>;
3429 };
3430
3431 compute-cb@7 {
3432 compatible = "qcom,fastrpc-compute-cb";
3433 reg = <7>;
3434 iommus = <&apps_smmu 0x1007 0x0460>;
3435 };
3436
3437 compute-cb@8 {
3438 compatible = "qcom,fastrpc-compute-cb";
3439 reg = <8>;
3440 iommus = <&apps_smmu 0x1008 0x0460>;
3441 };
3442
3443 /* note: secure cb9 in downstream */
3444 };
3445 };
3446 };
3447
3448 usb_1_hsphy: phy@88e2000 {
3449 compatible = "qcom,sm8150-usb-hs-phy",
3450 "qcom,usb-snps-hs-7nm-phy";
3451 reg = <0 0x088e2000 0 0x400>;
3452 status = "disabled";
3453 #phy-cells = <0>;
3454
3455 clocks = <&rpmhcc RPMH_CXO_CLK>;
3456 clock-names = "ref";
3457
3458 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3459 };
3460
3461 usb_2_hsphy: phy@88e3000 {
3462 compatible = "qcom,sm8150-usb-hs-phy",
3463 "qcom,usb-snps-hs-7nm-phy";
3464 reg = <0 0x088e3000 0 0x400>;
3465 status = "disabled";
3466 #phy-cells = <0>;
3467
3468 clocks = <&rpmhcc RPMH_CXO_CLK>;
3469 clock-names = "ref";
3470
3471 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3472 };
3473
3474 usb_1_qmpphy: phy@88e8000 {
3475 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3476 reg = <0 0x088e8000 0 0x3000>;
3477
3478 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3479 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3480 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3481 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3482 clock-names = "aux",
3483 "ref",
3484 "com_aux",
3485 "usb3_pipe";
3486
3487 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3488 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3489 reset-names = "phy", "common";
3490
3491 #clock-cells = <1>;
3492 #phy-cells = <1>;
3493
3494 status = "disabled";
3495
3496 ports {
3497 #address-cells = <1>;
3498 #size-cells = <0>;
3499
3500 port@0 {
3501 reg = <0>;
3502
3503 usb_1_qmpphy_out: endpoint {
3504 };
3505 };
3506
3507 port@1 {
3508 reg = <1>;
3509
3510 usb_1_qmpphy_usb_ss_in: endpoint {
3511 remote-endpoint = <&usb_1_dwc3_ss>;
3512 };
3513 };
3514
3515 port@2 {
3516 reg = <2>;
3517
3518 usb_1_qmpphy_dp_in: endpoint {
3519 remote-endpoint = <&mdss_dp_out>;
3520 };
3521 };
3522 };
3523 };
3524
3525 usb_2_qmpphy: phy@88eb000 {
3526 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3527 reg = <0 0x088eb000 0 0x1000>;
3528
3529 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3530 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3531 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3532 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3533 clock-names = "aux",
3534 "ref",
3535 "com_aux",
3536 "pipe";
3537 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3538 #clock-cells = <0>;
3539 #phy-cells = <0>;
3540
3541 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3542 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3543 reset-names = "phy",
3544 "phy_phy";
3545
3546 status = "disabled";
3547 };
3548
3549 sdhc_2: mmc@8804000 {
3550 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3551 reg = <0 0x08804000 0 0x1000>;
3552
3553 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3555 interrupt-names = "hc_irq", "pwr_irq";
3556
3557 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3558 <&gcc GCC_SDCC2_APPS_CLK>,
3559 <&rpmhcc RPMH_CXO_CLK>;
3560 clock-names = "iface", "core", "xo";
3561 iommus = <&apps_smmu 0x6a0 0x0>;
3562 qcom,dll-config = <0x0007642c>;
3563 qcom,ddr-config = <0x80040868>;
3564 power-domains = <&rpmhpd 0>;
3565 operating-points-v2 = <&sdhc2_opp_table>;
3566
3567 status = "disabled";
3568
3569 sdhc2_opp_table: opp-table {
3570 compatible = "operating-points-v2";
3571
3572 opp-19200000 {
3573 opp-hz = /bits/ 64 <19200000>;
3574 required-opps = <&rpmhpd_opp_min_svs>;
3575 };
3576
3577 opp-50000000 {
3578 opp-hz = /bits/ 64 <50000000>;
3579 required-opps = <&rpmhpd_opp_low_svs>;
3580 };
3581
3582 opp-100000000 {
3583 opp-hz = /bits/ 64 <100000000>;
3584 required-opps = <&rpmhpd_opp_svs>;
3585 };
3586
3587 opp-202000000 {
3588 opp-hz = /bits/ 64 <202000000>;
3589 required-opps = <&rpmhpd_opp_svs_l1>;
3590 };
3591 };
3592 };
3593
3594 dc_noc: interconnect@9160000 {
3595 compatible = "qcom,sm8150-dc-noc";
3596 reg = <0 0x09160000 0 0x3200>;
3597 #interconnect-cells = <2>;
3598 qcom,bcm-voters = <&apps_bcm_voter>;
3599 };
3600
3601 gem_noc: interconnect@9680000 {
3602 compatible = "qcom,sm8150-gem-noc";
3603 reg = <0 0x09680000 0 0x3e200>;
3604 #interconnect-cells = <2>;
3605 qcom,bcm-voters = <&apps_bcm_voter>;
3606 };
3607
3608 usb_1: usb@a6f8800 {
3609 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3610 reg = <0 0x0a6f8800 0 0x400>;
3611 status = "disabled";
3612 #address-cells = <2>;
3613 #size-cells = <2>;
3614 ranges;
3615 dma-ranges;
3616
3617 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3618 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3619 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3620 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3621 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3622 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3623 clock-names = "cfg_noc",
3624 "core",
3625 "iface",
3626 "sleep",
3627 "mock_utmi",
3628 "xo";
3629
3630 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3631 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3632 assigned-clock-rates = <19200000>, <200000000>;
3633
3634 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3635 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3637 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3638 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3639 interrupt-names = "pwr_event",
3640 "hs_phy_irq",
3641 "dp_hs_phy_irq",
3642 "dm_hs_phy_irq",
3643 "ss_phy_irq";
3644
3645 power-domains = <&gcc USB30_PRIM_GDSC>;
3646
3647 resets = <&gcc GCC_USB30_PRIM_BCR>;
3648
3649 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3650 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3651 interconnect-names = "usb-ddr", "apps-usb";
3652
3653 usb_1_dwc3: usb@a600000 {
3654 compatible = "snps,dwc3";
3655 reg = <0 0x0a600000 0 0xcd00>;
3656 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3657 iommus = <&apps_smmu 0x140 0>;
3658 snps,dis_u2_susphy_quirk;
3659 snps,dis_enblslpm_quirk;
3660 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3661 phy-names = "usb2-phy", "usb3-phy";
3662
3663 ports {
3664 #address-cells = <1>;
3665 #size-cells = <0>;
3666
3667 port@0 {
3668 reg = <0>;
3669
3670 usb_1_dwc3_hs: endpoint {
3671 };
3672 };
3673
3674 port@1 {
3675 reg = <1>;
3676
3677 usb_1_dwc3_ss: endpoint {
3678 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3679 };
3680 };
3681 };
3682 };
3683 };
3684
3685 usb_2: usb@a8f8800 {
3686 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3687 reg = <0 0x0a8f8800 0 0x400>;
3688 status = "disabled";
3689 #address-cells = <2>;
3690 #size-cells = <2>;
3691 ranges;
3692 dma-ranges;
3693
3694 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3695 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3696 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3697 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3698 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3699 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3700 clock-names = "cfg_noc",
3701 "core",
3702 "iface",
3703 "sleep",
3704 "mock_utmi",
3705 "xo";
3706
3707 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3708 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3709 assigned-clock-rates = <19200000>, <200000000>;
3710
3711 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3712 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
3714 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3715 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
3716 interrupt-names = "pwr_event",
3717 "hs_phy_irq",
3718 "dp_hs_phy_irq",
3719 "dm_hs_phy_irq",
3720 "ss_phy_irq";
3721
3722 power-domains = <&gcc USB30_SEC_GDSC>;
3723
3724 resets = <&gcc GCC_USB30_SEC_BCR>;
3725
3726 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3727 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3728 interconnect-names = "usb-ddr", "apps-usb";
3729
3730 usb_2_dwc3: usb@a800000 {
3731 compatible = "snps,dwc3";
3732 reg = <0 0x0a800000 0 0xcd00>;
3733 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3734 iommus = <&apps_smmu 0x160 0>;
3735 snps,dis_u2_susphy_quirk;
3736 snps,dis_enblslpm_quirk;
3737 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
3738 phy-names = "usb2-phy", "usb3-phy";
3739 };
3740 };
3741
3742 videocc: clock-controller@ab00000 {
3743 compatible = "qcom,sm8150-videocc";
3744 reg = <0 0x0ab00000 0 0x10000>;
3745 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3746 <&rpmhcc RPMH_CXO_CLK>;
3747 clock-names = "iface", "bi_tcxo";
3748 power-domains = <&rpmhpd SM8150_MMCX>;
3749 required-opps = <&rpmhpd_opp_low_svs>;
3750 #clock-cells = <1>;
3751 #reset-cells = <1>;
3752 #power-domain-cells = <1>;
3753 };
3754
3755 camnoc_virt: interconnect@ac00000 {
3756 compatible = "qcom,sm8150-camnoc-virt";
3757 reg = <0 0x0ac00000 0 0x1000>;
3758 #interconnect-cells = <2>;
3759 qcom,bcm-voters = <&apps_bcm_voter>;
3760 };
3761
3762 mdss: display-subsystem@ae00000 {
3763 compatible = "qcom,sm8150-mdss";
3764 reg = <0 0x0ae00000 0 0x1000>;
3765 reg-names = "mdss";
3766
3767 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3768 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3769 interconnect-names = "mdp0-mem", "mdp1-mem";
3770
3771 power-domains = <&dispcc MDSS_GDSC>;
3772
3773 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3774 <&gcc GCC_DISP_HF_AXI_CLK>,
3775 <&gcc GCC_DISP_SF_AXI_CLK>,
3776 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3777 clock-names = "iface", "bus", "nrt_bus", "core";
3778
3779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3780 interrupt-controller;
3781 #interrupt-cells = <1>;
3782
3783 iommus = <&apps_smmu 0x800 0x420>;
3784
3785 status = "disabled";
3786
3787 #address-cells = <2>;
3788 #size-cells = <2>;
3789 ranges;
3790
3791 mdss_mdp: display-controller@ae01000 {
3792 compatible = "qcom,sm8150-dpu";
3793 reg = <0 0x0ae01000 0 0x8f000>,
3794 <0 0x0aeb0000 0 0x2008>;
3795 reg-names = "mdp", "vbif";
3796
3797 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3798 <&gcc GCC_DISP_HF_AXI_CLK>,
3799 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3800 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3801 clock-names = "iface", "bus", "core", "vsync";
3802
3803 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3804 assigned-clock-rates = <19200000>;
3805
3806 operating-points-v2 = <&mdp_opp_table>;
3807 power-domains = <&rpmhpd SM8150_MMCX>;
3808
3809 interrupt-parent = <&mdss>;
3810 interrupts = <0>;
3811
3812 ports {
3813 #address-cells = <1>;
3814 #size-cells = <0>;
3815
3816 port@0 {
3817 reg = <0>;
3818 dpu_intf1_out: endpoint {
3819 remote-endpoint = <&mdss_dsi0_in>;
3820 };
3821 };
3822
3823 port@1 {
3824 reg = <1>;
3825 dpu_intf2_out: endpoint {
3826 remote-endpoint = <&mdss_dsi1_in>;
3827 };
3828 };
3829
3830 port@2 {
3831 reg = <2>;
3832 dpu_intf0_out: endpoint {
3833 remote-endpoint = <&mdss_dp_in>;
3834 };
3835 };
3836 };
3837
3838 mdp_opp_table: opp-table {
3839 compatible = "operating-points-v2";
3840
3841 opp-171428571 {
3842 opp-hz = /bits/ 64 <171428571>;
3843 required-opps = <&rpmhpd_opp_low_svs>;
3844 };
3845
3846 opp-300000000 {
3847 opp-hz = /bits/ 64 <300000000>;
3848 required-opps = <&rpmhpd_opp_svs>;
3849 };
3850
3851 opp-345000000 {
3852 opp-hz = /bits/ 64 <345000000>;
3853 required-opps = <&rpmhpd_opp_svs_l1>;
3854 };
3855
3856 opp-460000000 {
3857 opp-hz = /bits/ 64 <460000000>;
3858 required-opps = <&rpmhpd_opp_nom>;
3859 };
3860 };
3861 };
3862
3863 mdss_dp: displayport-controller@ae90000 {
3864 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3865 reg = <0 0xae90000 0 0x200>,
3866 <0 0xae90200 0 0x200>,
3867 <0 0xae90400 0 0x600>,
3868 <0 0x0ae90a00 0 0x600>,
3869 <0 0x0ae91000 0 0x600>;
3870
3871 interrupt-parent = <&mdss>;
3872 interrupts = <12>;
3873 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3874 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3875 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3876 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3877 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3878 clock-names = "core_iface",
3879 "core_aux",
3880 "ctrl_link",
3881 "ctrl_link_iface",
3882 "stream_pixel";
3883
3884 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3885 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3886 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3887 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3888
3889 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3890 phy-names = "dp";
3891
3892 #sound-dai-cells = <0>;
3893
3894 operating-points-v2 = <&dp_opp_table>;
3895 power-domains = <&rpmhpd SM8250_MMCX>;
3896
3897 status = "disabled";
3898
3899 ports {
3900 #address-cells = <1>;
3901 #size-cells = <0>;
3902
3903 port@0 {
3904 reg = <0>;
3905 mdss_dp_in: endpoint {
3906 remote-endpoint = <&dpu_intf0_out>;
3907 };
3908 };
3909
3910 port@1 {
3911 reg = <1>;
3912
3913 mdss_dp_out: endpoint {
3914 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3915 };
3916 };
3917 };
3918
3919 dp_opp_table: opp-table {
3920 compatible = "operating-points-v2";
3921
3922 opp-160000000 {
3923 opp-hz = /bits/ 64 <160000000>;
3924 required-opps = <&rpmhpd_opp_low_svs>;
3925 };
3926
3927 opp-270000000 {
3928 opp-hz = /bits/ 64 <270000000>;
3929 required-opps = <&rpmhpd_opp_svs>;
3930 };
3931
3932 opp-540000000 {
3933 opp-hz = /bits/ 64 <540000000>;
3934 required-opps = <&rpmhpd_opp_svs_l1>;
3935 };
3936
3937 opp-810000000 {
3938 opp-hz = /bits/ 64 <810000000>;
3939 required-opps = <&rpmhpd_opp_nom>;
3940 };
3941 };
3942 };
3943
3944 mdss_dsi0: dsi@ae94000 {
3945 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3946 reg = <0 0x0ae94000 0 0x400>;
3947 reg-names = "dsi_ctrl";
3948
3949 interrupt-parent = <&mdss>;
3950 interrupts = <4>;
3951
3952 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3953 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3954 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3955 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3956 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3957 <&gcc GCC_DISP_HF_AXI_CLK>;
3958 clock-names = "byte",
3959 "byte_intf",
3960 "pixel",
3961 "core",
3962 "iface",
3963 "bus";
3964
3965 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3966 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3967 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3968 <&mdss_dsi0_phy 1>;
3969
3970 operating-points-v2 = <&dsi_opp_table>;
3971 power-domains = <&rpmhpd SM8150_MMCX>;
3972
3973 phys = <&mdss_dsi0_phy>;
3974
3975 status = "disabled";
3976
3977 #address-cells = <1>;
3978 #size-cells = <0>;
3979
3980 ports {
3981 #address-cells = <1>;
3982 #size-cells = <0>;
3983
3984 port@0 {
3985 reg = <0>;
3986 mdss_dsi0_in: endpoint {
3987 remote-endpoint = <&dpu_intf1_out>;
3988 };
3989 };
3990
3991 port@1 {
3992 reg = <1>;
3993 mdss_dsi0_out: endpoint {
3994 };
3995 };
3996 };
3997
3998 dsi_opp_table: opp-table {
3999 compatible = "operating-points-v2";
4000
4001 opp-187500000 {
4002 opp-hz = /bits/ 64 <187500000>;
4003 required-opps = <&rpmhpd_opp_low_svs>;
4004 };
4005
4006 opp-300000000 {
4007 opp-hz = /bits/ 64 <300000000>;
4008 required-opps = <&rpmhpd_opp_svs>;
4009 };
4010
4011 opp-358000000 {
4012 opp-hz = /bits/ 64 <358000000>;
4013 required-opps = <&rpmhpd_opp_svs_l1>;
4014 };
4015 };
4016 };
4017
4018 mdss_dsi0_phy: phy@ae94400 {
4019 compatible = "qcom,dsi-phy-7nm-8150";
4020 reg = <0 0x0ae94400 0 0x200>,
4021 <0 0x0ae94600 0 0x280>,
4022 <0 0x0ae94900 0 0x260>;
4023 reg-names = "dsi_phy",
4024 "dsi_phy_lane",
4025 "dsi_pll";
4026
4027 #clock-cells = <1>;
4028 #phy-cells = <0>;
4029
4030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4031 <&rpmhcc RPMH_CXO_CLK>;
4032 clock-names = "iface", "ref";
4033
4034 status = "disabled";
4035 };
4036
4037 mdss_dsi1: dsi@ae96000 {
4038 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4039 reg = <0 0x0ae96000 0 0x400>;
4040 reg-names = "dsi_ctrl";
4041
4042 interrupt-parent = <&mdss>;
4043 interrupts = <5>;
4044
4045 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4046 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4047 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4048 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4049 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4050 <&gcc GCC_DISP_HF_AXI_CLK>;
4051 clock-names = "byte",
4052 "byte_intf",
4053 "pixel",
4054 "core",
4055 "iface",
4056 "bus";
4057
4058 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4059 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4060 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4061 <&mdss_dsi1_phy 1>;
4062
4063 operating-points-v2 = <&dsi_opp_table>;
4064 power-domains = <&rpmhpd SM8150_MMCX>;
4065
4066 phys = <&mdss_dsi1_phy>;
4067
4068 status = "disabled";
4069
4070 #address-cells = <1>;
4071 #size-cells = <0>;
4072
4073 ports {
4074 #address-cells = <1>;
4075 #size-cells = <0>;
4076
4077 port@0 {
4078 reg = <0>;
4079 mdss_dsi1_in: endpoint {
4080 remote-endpoint = <&dpu_intf2_out>;
4081 };
4082 };
4083
4084 port@1 {
4085 reg = <1>;
4086 mdss_dsi1_out: endpoint {
4087 };
4088 };
4089 };
4090 };
4091
4092 mdss_dsi1_phy: phy@ae96400 {
4093 compatible = "qcom,dsi-phy-7nm-8150";
4094 reg = <0 0x0ae96400 0 0x200>,
4095 <0 0x0ae96600 0 0x280>,
4096 <0 0x0ae96900 0 0x260>;
4097 reg-names = "dsi_phy",
4098 "dsi_phy_lane",
4099 "dsi_pll";
4100
4101 #clock-cells = <1>;
4102 #phy-cells = <0>;
4103
4104 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4105 <&rpmhcc RPMH_CXO_CLK>;
4106 clock-names = "iface", "ref";
4107
4108 status = "disabled";
4109 };
4110 };
4111
4112 dispcc: clock-controller@af00000 {
4113 compatible = "qcom,sm8150-dispcc";
4114 reg = <0 0x0af00000 0 0x10000>;
4115 clocks = <&rpmhcc RPMH_CXO_CLK>,
4116 <&mdss_dsi0_phy 0>,
4117 <&mdss_dsi0_phy 1>,
4118 <&mdss_dsi1_phy 0>,
4119 <&mdss_dsi1_phy 1>,
4120 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4121 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4122 clock-names = "bi_tcxo",
4123 "dsi0_phy_pll_out_byteclk",
4124 "dsi0_phy_pll_out_dsiclk",
4125 "dsi1_phy_pll_out_byteclk",
4126 "dsi1_phy_pll_out_dsiclk",
4127 "dp_phy_pll_link_clk",
4128 "dp_phy_pll_vco_div_clk";
4129 power-domains = <&rpmhpd SM8150_MMCX>;
4130 required-opps = <&rpmhpd_opp_low_svs>;
4131 #clock-cells = <1>;
4132 #reset-cells = <1>;
4133 #power-domain-cells = <1>;
4134 };
4135
4136 pdc: interrupt-controller@b220000 {
4137 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4138 reg = <0 0x0b220000 0 0x30000>;
4139 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4140 <125 63 1>;
4141 #interrupt-cells = <2>;
4142 interrupt-parent = <&intc>;
4143 interrupt-controller;
4144 };
4145
4146 aoss_qmp: power-management@c300000 {
4147 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4148 reg = <0x0 0x0c300000 0x0 0x400>;
4149 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4150 mboxes = <&apss_shared 0>;
4151
4152 #clock-cells = <0>;
4153 };
4154
4155 sram@c3f0000 {
4156 compatible = "qcom,rpmh-stats";
4157 reg = <0 0x0c3f0000 0 0x400>;
4158 };
4159
4160 tsens0: thermal-sensor@c263000 {
4161 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4162 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4163 <0 0x0c222000 0 0x1ff>; /* SROT */
4164 #qcom,sensors = <16>;
4165 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4167 interrupt-names = "uplow", "critical";
4168 #thermal-sensor-cells = <1>;
4169 };
4170
4171 tsens1: thermal-sensor@c265000 {
4172 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4173 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4174 <0 0x0c223000 0 0x1ff>; /* SROT */
4175 #qcom,sensors = <8>;
4176 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4178 interrupt-names = "uplow", "critical";
4179 #thermal-sensor-cells = <1>;
4180 };
4181
4182 spmi_bus: spmi@c440000 {
4183 compatible = "qcom,spmi-pmic-arb";
4184 reg = <0x0 0x0c440000 0x0 0x0001100>,
4185 <0x0 0x0c600000 0x0 0x2000000>,
4186 <0x0 0x0e600000 0x0 0x0100000>,
4187 <0x0 0x0e700000 0x0 0x00a0000>,
4188 <0x0 0x0c40a000 0x0 0x0026000>;
4189 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4190 interrupt-names = "periph_irq";
4191 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4192 qcom,ee = <0>;
4193 qcom,channel = <0>;
4194 #address-cells = <2>;
4195 #size-cells = <0>;
4196 interrupt-controller;
4197 #interrupt-cells = <4>;
4198 };
4199
4200 apps_smmu: iommu@15000000 {
4201 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4202 reg = <0 0x15000000 0 0x100000>;
4203 #iommu-cells = <2>;
4204 #global-interrupts = <1>;
4205 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4286 };
4287
4288 remoteproc_adsp: remoteproc@17300000 {
4289 compatible = "qcom,sm8150-adsp-pas";
4290 reg = <0x0 0x17300000 0x0 0x4040>;
4291
4292 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4293 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4294 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4295 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4296 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4297 interrupt-names = "wdog", "fatal", "ready",
4298 "handover", "stop-ack";
4299
4300 clocks = <&rpmhcc RPMH_CXO_CLK>;
4301 clock-names = "xo";
4302
4303 power-domains = <&rpmhpd SM8150_CX>;
4304
4305 memory-region = <&adsp_mem>;
4306
4307 qcom,qmp = <&aoss_qmp>;
4308
4309 qcom,smem-states = <&adsp_smp2p_out 0>;
4310 qcom,smem-state-names = "stop";
4311
4312 status = "disabled";
4313
4314 glink-edge {
4315 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4316 label = "lpass";
4317 qcom,remote-pid = <2>;
4318 mboxes = <&apss_shared 8>;
4319
4320 fastrpc {
4321 compatible = "qcom,fastrpc";
4322 qcom,glink-channels = "fastrpcglink-apps-dsp";
4323 label = "adsp";
4324 qcom,non-secure-domain;
4325 #address-cells = <1>;
4326 #size-cells = <0>;
4327
4328 compute-cb@3 {
4329 compatible = "qcom,fastrpc-compute-cb";
4330 reg = <3>;
4331 iommus = <&apps_smmu 0x1b23 0x0>;
4332 };
4333
4334 compute-cb@4 {
4335 compatible = "qcom,fastrpc-compute-cb";
4336 reg = <4>;
4337 iommus = <&apps_smmu 0x1b24 0x0>;
4338 };
4339
4340 compute-cb@5 {
4341 compatible = "qcom,fastrpc-compute-cb";
4342 reg = <5>;
4343 iommus = <&apps_smmu 0x1b25 0x0>;
4344 };
4345 };
4346 };
4347 };
4348
4349 intc: interrupt-controller@17a00000 {
4350 compatible = "arm,gic-v3";
4351 interrupt-controller;
4352 #interrupt-cells = <3>;
4353 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4354 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4355 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4356 };
4357
4358 apss_shared: mailbox@17c00000 {
4359 compatible = "qcom,sm8150-apss-shared",
4360 "qcom,sdm845-apss-shared";
4361 reg = <0x0 0x17c00000 0x0 0x1000>;
4362 #mbox-cells = <1>;
4363 };
4364
4365 watchdog@17c10000 {
4366 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4367 reg = <0 0x17c10000 0 0x1000>;
4368 clocks = <&sleep_clk>;
4369 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4370 };
4371
4372 timer@17c20000 {
4373 #address-cells = <1>;
4374 #size-cells = <1>;
4375 ranges = <0 0 0 0x20000000>;
4376 compatible = "arm,armv7-timer-mem";
4377 reg = <0x0 0x17c20000 0x0 0x1000>;
4378 clock-frequency = <19200000>;
4379
4380 frame@17c21000 {
4381 frame-number = <0>;
4382 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4383 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4384 reg = <0x17c21000 0x1000>,
4385 <0x17c22000 0x1000>;
4386 };
4387
4388 frame@17c23000 {
4389 frame-number = <1>;
4390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4391 reg = <0x17c23000 0x1000>;
4392 status = "disabled";
4393 };
4394
4395 frame@17c25000 {
4396 frame-number = <2>;
4397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4398 reg = <0x17c25000 0x1000>;
4399 status = "disabled";
4400 };
4401
4402 frame@17c27000 {
4403 frame-number = <3>;
4404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4405 reg = <0x17c26000 0x1000>;
4406 status = "disabled";
4407 };
4408
4409 frame@17c29000 {
4410 frame-number = <4>;
4411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4412 reg = <0x17c29000 0x1000>;
4413 status = "disabled";
4414 };
4415
4416 frame@17c2b000 {
4417 frame-number = <5>;
4418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4419 reg = <0x17c2b000 0x1000>;
4420 status = "disabled";
4421 };
4422
4423 frame@17c2d000 {
4424 frame-number = <6>;
4425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4426 reg = <0x17c2d000 0x1000>;
4427 status = "disabled";
4428 };
4429 };
4430
4431 apps_rsc: rsc@18200000 {
4432 label = "apps_rsc";
4433 compatible = "qcom,rpmh-rsc";
4434 reg = <0x0 0x18200000 0x0 0x10000>,
4435 <0x0 0x18210000 0x0 0x10000>,
4436 <0x0 0x18220000 0x0 0x10000>;
4437 reg-names = "drv-0", "drv-1", "drv-2";
4438 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4439 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4440 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4441 qcom,tcs-offset = <0xd00>;
4442 qcom,drv-id = <2>;
4443 qcom,tcs-config = <ACTIVE_TCS 2>,
4444 <SLEEP_TCS 3>,
4445 <WAKE_TCS 3>,
4446 <CONTROL_TCS 1>;
4447 power-domains = <&CLUSTER_PD>;
4448
4449 rpmhcc: clock-controller {
4450 compatible = "qcom,sm8150-rpmh-clk";
4451 #clock-cells = <1>;
4452 clock-names = "xo";
4453 clocks = <&xo_board>;
4454 };
4455
4456 rpmhpd: power-controller {
4457 compatible = "qcom,sm8150-rpmhpd";
4458 #power-domain-cells = <1>;
4459 operating-points-v2 = <&rpmhpd_opp_table>;
4460
4461 rpmhpd_opp_table: opp-table {
4462 compatible = "operating-points-v2";
4463
4464 rpmhpd_opp_ret: opp1 {
4465 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4466 };
4467
4468 rpmhpd_opp_min_svs: opp2 {
4469 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4470 };
4471
4472 rpmhpd_opp_low_svs: opp3 {
4473 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4474 };
4475
4476 rpmhpd_opp_svs: opp4 {
4477 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4478 };
4479
4480 rpmhpd_opp_svs_l1: opp5 {
4481 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4482 };
4483
4484 rpmhpd_opp_svs_l2: opp6 {
4485 opp-level = <224>;
4486 };
4487
4488 rpmhpd_opp_nom: opp7 {
4489 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4490 };
4491
4492 rpmhpd_opp_nom_l1: opp8 {
4493 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4494 };
4495
4496 rpmhpd_opp_nom_l2: opp9 {
4497 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4498 };
4499
4500 rpmhpd_opp_turbo: opp10 {
4501 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4502 };
4503
4504 rpmhpd_opp_turbo_l1: opp11 {
4505 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4506 };
4507 };
4508 };
4509
4510 apps_bcm_voter: bcm-voter {
4511 compatible = "qcom,bcm-voter";
4512 };
4513 };
4514
4515 osm_l3: interconnect@18321000 {
4516 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4517 reg = <0 0x18321000 0 0x1400>;
4518
4519 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4520 clock-names = "xo", "alternate";
4521
4522 #interconnect-cells = <1>;
4523 };
4524
4525 cpufreq_hw: cpufreq@18323000 {
4526 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4527 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4528 <0 0x18327800 0 0x1400>;
4529 reg-names = "freq-domain0", "freq-domain1",
4530 "freq-domain2";
4531
4532 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", "alternate";
4534
4535 #freq-domain-cells = <1>;
4536 #clock-cells = <1>;
4537 };
4538
4539 lmh_cluster1: lmh@18350800 {
4540 compatible = "qcom,sm8150-lmh";
4541 reg = <0 0x18350800 0 0x400>;
4542 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4543 cpus = <&CPU4>;
4544 qcom,lmh-temp-arm-millicelsius = <60000>;
4545 qcom,lmh-temp-low-millicelsius = <84500>;
4546 qcom,lmh-temp-high-millicelsius = <85000>;
4547 interrupt-controller;
4548 #interrupt-cells = <1>;
4549 };
4550
4551 lmh_cluster0: lmh@18358800 {
4552 compatible = "qcom,sm8150-lmh";
4553 reg = <0 0x18358800 0 0x400>;
4554 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4555 cpus = <&CPU0>;
4556 qcom,lmh-temp-arm-millicelsius = <60000>;
4557 qcom,lmh-temp-low-millicelsius = <84500>;
4558 qcom,lmh-temp-high-millicelsius = <85000>;
4559 interrupt-controller;
4560 #interrupt-cells = <1>;
4561 };
4562
4563 wifi: wifi@18800000 {
4564 compatible = "qcom,wcn3990-wifi";
4565 reg = <0 0x18800000 0 0x800000>;
4566 reg-names = "membase";
4567 memory-region = <&wlan_mem>;
4568 clock-names = "cxo_ref_clk_pin", "qdss";
4569 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4570 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4571 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4572 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4573 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4574 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4575 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4576 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4577 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4578 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4579 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4580 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4581 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4582 iommus = <&apps_smmu 0x0640 0x1>;
4583 status = "disabled";
4584 };
4585 };
4586
4587 timer {
4588 compatible = "arm,armv8-timer";
4589 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4590 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4591 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4592 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4593 };
4594
4595 thermal-zones {
4596 cpu0-thermal {
4597 polling-delay-passive = <250>;
4598
4599 thermal-sensors = <&tsens0 1>;
4600
4601 trips {
4602 cpu0_alert0: trip-point0 {
4603 temperature = <90000>;
4604 hysteresis = <2000>;
4605 type = "passive";
4606 };
4607
4608 cpu0_alert1: trip-point1 {
4609 temperature = <95000>;
4610 hysteresis = <2000>;
4611 type = "passive";
4612 };
4613
4614 cpu0_crit: cpu-crit {
4615 temperature = <110000>;
4616 hysteresis = <1000>;
4617 type = "critical";
4618 };
4619 };
4620
4621 cooling-maps {
4622 map0 {
4623 trip = <&cpu0_alert0>;
4624 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4625 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4626 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4627 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4628 };
4629 map1 {
4630 trip = <&cpu0_alert1>;
4631 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4632 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4633 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4634 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4635 };
4636 };
4637 };
4638
4639 cpu1-thermal {
4640 polling-delay-passive = <250>;
4641
4642 thermal-sensors = <&tsens0 2>;
4643
4644 trips {
4645 cpu1_alert0: trip-point0 {
4646 temperature = <90000>;
4647 hysteresis = <2000>;
4648 type = "passive";
4649 };
4650
4651 cpu1_alert1: trip-point1 {
4652 temperature = <95000>;
4653 hysteresis = <2000>;
4654 type = "passive";
4655 };
4656
4657 cpu1_crit: cpu-crit {
4658 temperature = <110000>;
4659 hysteresis = <1000>;
4660 type = "critical";
4661 };
4662 };
4663
4664 cooling-maps {
4665 map0 {
4666 trip = <&cpu1_alert0>;
4667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4671 };
4672 map1 {
4673 trip = <&cpu1_alert1>;
4674 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4675 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4676 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4677 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4678 };
4679 };
4680 };
4681
4682 cpu2-thermal {
4683 polling-delay-passive = <250>;
4684
4685 thermal-sensors = <&tsens0 3>;
4686
4687 trips {
4688 cpu2_alert0: trip-point0 {
4689 temperature = <90000>;
4690 hysteresis = <2000>;
4691 type = "passive";
4692 };
4693
4694 cpu2_alert1: trip-point1 {
4695 temperature = <95000>;
4696 hysteresis = <2000>;
4697 type = "passive";
4698 };
4699
4700 cpu2_crit: cpu-crit {
4701 temperature = <110000>;
4702 hysteresis = <1000>;
4703 type = "critical";
4704 };
4705 };
4706
4707 cooling-maps {
4708 map0 {
4709 trip = <&cpu2_alert0>;
4710 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4711 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4712 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4713 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4714 };
4715 map1 {
4716 trip = <&cpu2_alert1>;
4717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4721 };
4722 };
4723 };
4724
4725 cpu3-thermal {
4726 polling-delay-passive = <250>;
4727
4728 thermal-sensors = <&tsens0 4>;
4729
4730 trips {
4731 cpu3_alert0: trip-point0 {
4732 temperature = <90000>;
4733 hysteresis = <2000>;
4734 type = "passive";
4735 };
4736
4737 cpu3_alert1: trip-point1 {
4738 temperature = <95000>;
4739 hysteresis = <2000>;
4740 type = "passive";
4741 };
4742
4743 cpu3_crit: cpu-crit {
4744 temperature = <110000>;
4745 hysteresis = <1000>;
4746 type = "critical";
4747 };
4748 };
4749
4750 cooling-maps {
4751 map0 {
4752 trip = <&cpu3_alert0>;
4753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4757 };
4758 map1 {
4759 trip = <&cpu3_alert1>;
4760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4764 };
4765 };
4766 };
4767
4768 cpu4-top-thermal {
4769 polling-delay-passive = <250>;
4770
4771 thermal-sensors = <&tsens0 7>;
4772
4773 trips {
4774 cpu4_top_alert0: trip-point0 {
4775 temperature = <90000>;
4776 hysteresis = <2000>;
4777 type = "passive";
4778 };
4779
4780 cpu4_top_alert1: trip-point1 {
4781 temperature = <95000>;
4782 hysteresis = <2000>;
4783 type = "passive";
4784 };
4785
4786 cpu4_top_crit: cpu-crit {
4787 temperature = <110000>;
4788 hysteresis = <1000>;
4789 type = "critical";
4790 };
4791 };
4792
4793 cooling-maps {
4794 map0 {
4795 trip = <&cpu4_top_alert0>;
4796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4800 };
4801 map1 {
4802 trip = <&cpu4_top_alert1>;
4803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4807 };
4808 };
4809 };
4810
4811 cpu5-top-thermal {
4812 polling-delay-passive = <250>;
4813
4814 thermal-sensors = <&tsens0 8>;
4815
4816 trips {
4817 cpu5_top_alert0: trip-point0 {
4818 temperature = <90000>;
4819 hysteresis = <2000>;
4820 type = "passive";
4821 };
4822
4823 cpu5_top_alert1: trip-point1 {
4824 temperature = <95000>;
4825 hysteresis = <2000>;
4826 type = "passive";
4827 };
4828
4829 cpu5_top_crit: cpu-crit {
4830 temperature = <110000>;
4831 hysteresis = <1000>;
4832 type = "critical";
4833 };
4834 };
4835
4836 cooling-maps {
4837 map0 {
4838 trip = <&cpu5_top_alert0>;
4839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4843 };
4844 map1 {
4845 trip = <&cpu5_top_alert1>;
4846 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4847 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4848 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4849 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4850 };
4851 };
4852 };
4853
4854 cpu6-top-thermal {
4855 polling-delay-passive = <250>;
4856
4857 thermal-sensors = <&tsens0 9>;
4858
4859 trips {
4860 cpu6_top_alert0: trip-point0 {
4861 temperature = <90000>;
4862 hysteresis = <2000>;
4863 type = "passive";
4864 };
4865
4866 cpu6_top_alert1: trip-point1 {
4867 temperature = <95000>;
4868 hysteresis = <2000>;
4869 type = "passive";
4870 };
4871
4872 cpu6_top_crit: cpu-crit {
4873 temperature = <110000>;
4874 hysteresis = <1000>;
4875 type = "critical";
4876 };
4877 };
4878
4879 cooling-maps {
4880 map0 {
4881 trip = <&cpu6_top_alert0>;
4882 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4883 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4884 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4885 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4886 };
4887 map1 {
4888 trip = <&cpu6_top_alert1>;
4889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4893 };
4894 };
4895 };
4896
4897 cpu7-top-thermal {
4898 polling-delay-passive = <250>;
4899
4900 thermal-sensors = <&tsens0 10>;
4901
4902 trips {
4903 cpu7_top_alert0: trip-point0 {
4904 temperature = <90000>;
4905 hysteresis = <2000>;
4906 type = "passive";
4907 };
4908
4909 cpu7_top_alert1: trip-point1 {
4910 temperature = <95000>;
4911 hysteresis = <2000>;
4912 type = "passive";
4913 };
4914
4915 cpu7_top_crit: cpu-crit {
4916 temperature = <110000>;
4917 hysteresis = <1000>;
4918 type = "critical";
4919 };
4920 };
4921
4922 cooling-maps {
4923 map0 {
4924 trip = <&cpu7_top_alert0>;
4925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4929 };
4930 map1 {
4931 trip = <&cpu7_top_alert1>;
4932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4936 };
4937 };
4938 };
4939
4940 cpu4-bottom-thermal {
4941 polling-delay-passive = <250>;
4942
4943 thermal-sensors = <&tsens0 11>;
4944
4945 trips {
4946 cpu4_bottom_alert0: trip-point0 {
4947 temperature = <90000>;
4948 hysteresis = <2000>;
4949 type = "passive";
4950 };
4951
4952 cpu4_bottom_alert1: trip-point1 {
4953 temperature = <95000>;
4954 hysteresis = <2000>;
4955 type = "passive";
4956 };
4957
4958 cpu4_bottom_crit: cpu-crit {
4959 temperature = <110000>;
4960 hysteresis = <1000>;
4961 type = "critical";
4962 };
4963 };
4964
4965 cooling-maps {
4966 map0 {
4967 trip = <&cpu4_bottom_alert0>;
4968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4972 };
4973 map1 {
4974 trip = <&cpu4_bottom_alert1>;
4975 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4976 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4977 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4978 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4979 };
4980 };
4981 };
4982
4983 cpu5-bottom-thermal {
4984 polling-delay-passive = <250>;
4985
4986 thermal-sensors = <&tsens0 12>;
4987
4988 trips {
4989 cpu5_bottom_alert0: trip-point0 {
4990 temperature = <90000>;
4991 hysteresis = <2000>;
4992 type = "passive";
4993 };
4994
4995 cpu5_bottom_alert1: trip-point1 {
4996 temperature = <95000>;
4997 hysteresis = <2000>;
4998 type = "passive";
4999 };
5000
5001 cpu5_bottom_crit: cpu-crit {
5002 temperature = <110000>;
5003 hysteresis = <1000>;
5004 type = "critical";
5005 };
5006 };
5007
5008 cooling-maps {
5009 map0 {
5010 trip = <&cpu5_bottom_alert0>;
5011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5015 };
5016 map1 {
5017 trip = <&cpu5_bottom_alert1>;
5018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5022 };
5023 };
5024 };
5025
5026 cpu6-bottom-thermal {
5027 polling-delay-passive = <250>;
5028
5029 thermal-sensors = <&tsens0 13>;
5030
5031 trips {
5032 cpu6_bottom_alert0: trip-point0 {
5033 temperature = <90000>;
5034 hysteresis = <2000>;
5035 type = "passive";
5036 };
5037
5038 cpu6_bottom_alert1: trip-point1 {
5039 temperature = <95000>;
5040 hysteresis = <2000>;
5041 type = "passive";
5042 };
5043
5044 cpu6_bottom_crit: cpu-crit {
5045 temperature = <110000>;
5046 hysteresis = <1000>;
5047 type = "critical";
5048 };
5049 };
5050
5051 cooling-maps {
5052 map0 {
5053 trip = <&cpu6_bottom_alert0>;
5054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5058 };
5059 map1 {
5060 trip = <&cpu6_bottom_alert1>;
5061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5065 };
5066 };
5067 };
5068
5069 cpu7-bottom-thermal {
5070 polling-delay-passive = <250>;
5071
5072 thermal-sensors = <&tsens0 14>;
5073
5074 trips {
5075 cpu7_bottom_alert0: trip-point0 {
5076 temperature = <90000>;
5077 hysteresis = <2000>;
5078 type = "passive";
5079 };
5080
5081 cpu7_bottom_alert1: trip-point1 {
5082 temperature = <95000>;
5083 hysteresis = <2000>;
5084 type = "passive";
5085 };
5086
5087 cpu7_bottom_crit: cpu-crit {
5088 temperature = <110000>;
5089 hysteresis = <1000>;
5090 type = "critical";
5091 };
5092 };
5093
5094 cooling-maps {
5095 map0 {
5096 trip = <&cpu7_bottom_alert0>;
5097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5098 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5099 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5100 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5101 };
5102 map1 {
5103 trip = <&cpu7_bottom_alert1>;
5104 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5105 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5106 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5107 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5108 };
5109 };
5110 };
5111
5112 aoss0-thermal {
5113 polling-delay-passive = <250>;
5114
5115 thermal-sensors = <&tsens0 0>;
5116
5117 trips {
5118 aoss0_alert0: trip-point0 {
5119 temperature = <90000>;
5120 hysteresis = <2000>;
5121 type = "hot";
5122 };
5123 };
5124 };
5125
5126 cluster0-thermal {
5127 polling-delay-passive = <250>;
5128
5129 thermal-sensors = <&tsens0 5>;
5130
5131 trips {
5132 cluster0_alert0: trip-point0 {
5133 temperature = <90000>;
5134 hysteresis = <2000>;
5135 type = "hot";
5136 };
5137 cluster0_crit: cluster0-crit {
5138 temperature = <110000>;
5139 hysteresis = <2000>;
5140 type = "critical";
5141 };
5142 };
5143 };
5144
5145 cluster1-thermal {
5146 polling-delay-passive = <250>;
5147
5148 thermal-sensors = <&tsens0 6>;
5149
5150 trips {
5151 cluster1_alert0: trip-point0 {
5152 temperature = <90000>;
5153 hysteresis = <2000>;
5154 type = "hot";
5155 };
5156 cluster1_crit: cluster1-crit {
5157 temperature = <110000>;
5158 hysteresis = <2000>;
5159 type = "critical";
5160 };
5161 };
5162 };
5163
5164 gpu-top-thermal {
5165 polling-delay-passive = <250>;
5166
5167 thermal-sensors = <&tsens0 15>;
5168
5169 cooling-maps {
5170 map0 {
5171 trip = <&gpu_top_alert0>;
5172 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5173 };
5174 };
5175
5176 trips {
5177 gpu_top_alert0: trip-point0 {
5178 temperature = <85000>;
5179 hysteresis = <1000>;
5180 type = "passive";
5181 };
5182
5183 trip-point1 {
5184 temperature = <90000>;
5185 hysteresis = <1000>;
5186 type = "hot";
5187 };
5188
5189 trip-point2 {
5190 temperature = <110000>;
5191 hysteresis = <1000>;
5192 type = "critical";
5193 };
5194 };
5195 };
5196
5197 aoss1-thermal {
5198 polling-delay-passive = <250>;
5199
5200 thermal-sensors = <&tsens1 0>;
5201
5202 trips {
5203 aoss1_alert0: trip-point0 {
5204 temperature = <90000>;
5205 hysteresis = <2000>;
5206 type = "hot";
5207 };
5208 };
5209 };
5210
5211 wlan-thermal {
5212 polling-delay-passive = <250>;
5213
5214 thermal-sensors = <&tsens1 1>;
5215
5216 trips {
5217 wlan_alert0: trip-point0 {
5218 temperature = <90000>;
5219 hysteresis = <2000>;
5220 type = "hot";
5221 };
5222 };
5223 };
5224
5225 video-thermal {
5226 polling-delay-passive = <250>;
5227
5228 thermal-sensors = <&tsens1 2>;
5229
5230 trips {
5231 video_alert0: trip-point0 {
5232 temperature = <90000>;
5233 hysteresis = <2000>;
5234 type = "hot";
5235 };
5236 };
5237 };
5238
5239 mem-thermal {
5240 polling-delay-passive = <250>;
5241
5242 thermal-sensors = <&tsens1 3>;
5243
5244 trips {
5245 mem_alert0: trip-point0 {
5246 temperature = <90000>;
5247 hysteresis = <2000>;
5248 type = "hot";
5249 };
5250 };
5251 };
5252
5253 q6-hvx-thermal {
5254 polling-delay-passive = <250>;
5255
5256 thermal-sensors = <&tsens1 4>;
5257
5258 trips {
5259 q6_hvx_alert0: trip-point0 {
5260 temperature = <90000>;
5261 hysteresis = <2000>;
5262 type = "hot";
5263 };
5264 };
5265 };
5266
5267 camera-thermal {
5268 polling-delay-passive = <250>;
5269
5270 thermal-sensors = <&tsens1 5>;
5271
5272 trips {
5273 camera_alert0: trip-point0 {
5274 temperature = <90000>;
5275 hysteresis = <2000>;
5276 type = "hot";
5277 };
5278 };
5279 };
5280
5281 compute-thermal {
5282 polling-delay-passive = <250>;
5283
5284 thermal-sensors = <&tsens1 6>;
5285
5286 trips {
5287 compute_alert0: trip-point0 {
5288 temperature = <90000>;
5289 hysteresis = <2000>;
5290 type = "hot";
5291 };
5292 };
5293 };
5294
5295 modem-thermal {
5296 polling-delay-passive = <250>;
5297
5298 thermal-sensors = <&tsens1 7>;
5299
5300 trips {
5301 modem_alert0: trip-point0 {
5302 temperature = <90000>;
5303 hysteresis = <2000>;
5304 type = "hot";
5305 };
5306 };
5307 };
5308
5309 npu-thermal {
5310 polling-delay-passive = <250>;
5311
5312 thermal-sensors = <&tsens1 8>;
5313
5314 trips {
5315 npu_alert0: trip-point0 {
5316 temperature = <90000>;
5317 hysteresis = <2000>;
5318 type = "hot";
5319 };
5320 };
5321 };
5322
5323 modem-vec-thermal {
5324 polling-delay-passive = <250>;
5325
5326 thermal-sensors = <&tsens1 9>;
5327
5328 trips {
5329 modem_vec_alert0: trip-point0 {
5330 temperature = <90000>;
5331 hysteresis = <2000>;
5332 type = "hot";
5333 };
5334 };
5335 };
5336
5337 modem-scl-thermal {
5338 polling-delay-passive = <250>;
5339
5340 thermal-sensors = <&tsens1 10>;
5341
5342 trips {
5343 modem_scl_alert0: trip-point0 {
5344 temperature = <90000>;
5345 hysteresis = <2000>;
5346 type = "hot";
5347 };
5348 };
5349 };
5350
5351 gpu-bottom-thermal {
5352 polling-delay-passive = <250>;
5353
5354 thermal-sensors = <&tsens1 11>;
5355
5356 cooling-maps {
5357 map0 {
5358 trip = <&gpu_bottom_alert0>;
5359 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5360 };
5361 };
5362
5363 trips {
5364 gpu_bottom_alert0: trip-point0 {
5365 temperature = <85000>;
5366 hysteresis = <1000>;
5367 type = "passive";
5368 };
5369
5370 trip-point1 {
5371 temperature = <90000>;
5372 hysteresis = <1000>;
5373 type = "hot";
5374 };
5375
5376 trip-point2 {
5377 temperature = <110000>;
5378 hysteresis = <1000>;
5379 type = "critical";
5380 };
5381 };
5382 };
5383 };
5384 };
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